Path file updated
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..c66c17f 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,53 @@
`else
`include "user_project_wrapper.v"
`include "user_proj_example.v"
-`endif
\ No newline at end of file
+ `include "FPU/beh_lib.v"
+ `include "FPU/Dec_gpr_ctl.v"
+ `include "FPU/Execution.v"
+ `include "FPU/FMADD_Add_Post_Normalization.v"
+ `include "FPU/FMADD_exponent_addition.v"
+ `include "FPU/FMADD_Exponent_Matching.v"
+ `include "FPU/FMADD_extender.v"
+ `include "FPU/FMADD_LZD_L0.v"
+ `include "FPU/FMADD_LZD_L1.v"
+ `include "FPU/FMADD_LZD_L2.v"
+ `include "FPU/FMADD_LZD_L3.v"
+ `include "FPU/FMADD_LZD_L4.v"
+ `include "FPU/FMADD_LZD_main.v"
+ `include "FPU/FMADD_mantissa_addition.v"
+ `include "FPU/FMADD_mantissa_generator.v"
+ `include "FPU/FMADD_mantissa_multiplication.v"
+ `include "FPU/FMADD_Mul_Post_Normalization.v"
+ `include "FPU/FMADD_rounding_block_Addition.v"
+ `include "FPU/FMADD_rounding_block_Multiplication.v"
+ `include "FPU/FMADD_Top_Single_Cycle.v"
+ `include "FPU/FPU_comparison.v"
+ `include "FPU/FPU_CSR.v"
+ `include "FPU/FPU_dec_ctl.v"
+ `include "FPU/FPU_decode.v"
+ `include "FPU/FPU_exu.v"
+ `include "FPU/FPU_F2I.v"
+ `include "FPU/FPU_Fclass.v"
+ `include "FPU/FPU_fpr_ctl.v"
+ `include "FPU/FPU_FSM_Control_Decode.v"
+ `include "FPU/FPU_FSM_TOP.v"
+ `include "FPU/FPU_Input_Validation.v"
+ `include "FPU/FPU_move.v"
+ `include "FPU/FPU_sign_injection.v"
+ `include "FPU/FPU_Too_Single_Cycle.v"
+ `include "FPU/I2F_main.v"
+ `include "FPU/iccm_controller.v"
+ `include "FPU/inst_checker.v"
+ `include "FPU/LZD_comb.v"
+ `include "FPU/LZD_layer0.v"
+ `include "FPU/LZD_layer1.v"
+ `include "FPU/LZD_layer2.v"
+ `include "FPU/LZD_layer3.v"
+ `include "FPU/LZD_layer4.v"
+ `include "FPU/LZD_main.v"
+ `include "FPU/LZD_mux.v"
+ `include "FPU/Main_Decode.v"
+ `include "FPU/uart_rx_prob.v"
+ `include "FPU/Sky130_SRAM_1kbyte_Memory.v"
+
+`endif
