commit 7076ceea0a5c2fd31fc827797b957bbd7cc78e52
author hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 19:20:18 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 19:20:18 2022 +0500
tree d84a327deb6f9f4cce3c57b4515aa7ecb3cc8fae
parent fd6d4a69e41cf084edcfa7e776c405f83b7f243a

Testbench Update

verilog/dv/FPU_Half/FPU_Half_tb.v

diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index a1bf0f2..23db252 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -107,7 +107,7 @@
             wait(mprj_io_0 == 16'h0002);
             */
             // Observe Output pins [23:8] for Comparison and Min/Max
-            
+            /*
             wait(mprj_io_0 == 16'h0001);
             wait(mprj_io_0 == 16'h0001);
             wait(mprj_io_0 == 16'h0001);
@@ -123,7 +123,16 @@
             wait(mprj_io_0 == 16'hDC87);
             wait(mprj_io_0 == 16'hB03E);
             wait(mprj_io_0 == 16'hBCF0);
-            
+            */
+            // Observe Output pins [23:8] for FMUL
+            wait(mprj_io_0 == 16'h60C2);
+            wait(mprj_io_0 == 16'h30A7);
+            wait(mprj_io_0 == 16'h67FF);
+            wait(mprj_io_0 == 16'h78DF);
+            wait(mprj_io_0 == 16'h7C00);
+            wait(mprj_io_0 == 16'h5124);
+            wait(mprj_io_0 == 16'h6058);
+            wait(mprj_io_0 == 16'h0000);
             
             $display("MPRJ-IO state = %h", mprj_io[23:8]);