Updated the tb and c file
diff --git a/verilog/dv/FPU_Half/FPU_Half.c b/verilog/dv/FPU_Half/FPU_Half.c
index 99b9a94..55b8f94 100644
--- a/verilog/dv/FPU_Half/FPU_Half.c
+++ b/verilog/dv/FPU_Half/FPU_Half.c
@@ -13,8 +13,8 @@
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
void main()
{
@@ -44,18 +44,18 @@
reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+ //reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
//reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -63,16 +63,21 @@
reg_mprj_xfer = 1;
while(reg_mprj_xfer == 1);
- reg_la2_oenb = reg_la2_iena = 0x00000002;
- reg_la2_data = 0x00000000; // reset
- reg_la2_data = 0x00000001;
- reg_la2_oenb = reg_la2_iena = 0x00000003;
-
- reg_la1_oenb = reg_la1_iena = 0x00000000;
- reg_la1_data = 0x00000015C; // Clk_per_bit
+ // Configure LA probes as inputs to the cpu put zero
+ // Configure LA probes as outputs from the cpu put one
- reg_la0_oenb = reg_la0_iena = 0x00000002;
- reg_la0_data = 0x00000000;
+ reg_la2_oenb = reg_la2_iena = 0x00000002; // 64 bit as input to user proj and output from cpu
+ reg_la2_data = 0x00000000; // reset
+ reg_la2_data = 0x00000001;
+ reg_la2_oenb = reg_la2_iena = 0x00000003; // 64 anf 65 bit as input to user proj and output from cpu
+
+ //reg_la1_oenb = reg_la1_iena = 0x00000000;
+ //reg_la1_data = 0x00000015C; // Clk_per_bit
+
+ //reg_la0_oenb = reg_la0_iena = 0x00000002;
+ //reg_la0_data = 0x00000000;
+
+ // sending mprj ready signal
reg_mprj_datah = 0x20;
}
diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v
index 9a01a9b..09e34d2 100644
--- a/verilog/dv/FPU_Half/FPU_Half_tb.v
+++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -32,10 +32,10 @@
wire gpio;
wire [37:0] mprj_io;
- wire [27:0] mprj_io_0;
+ wire [15:0] mprj_io_0;
wire mprj_ready;
- assign mprj_io_0 = mprj_io[35:8];
+ assign mprj_io_0 = mprj_io[23:8];
assign mprj_ready = mprj_io[37];
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -82,13 +82,13 @@
wait(mprj_io_0 == 28'd11);
wait(mprj_io_0 == 28'd13);
*/
- // Observe Output pins [35:8] for multliplication_table
- wait(mprj_io_0 == 28'd5);
- wait(mprj_io_0 == 28'd10);
- wait(mprj_io_0 == 28'd15);
- wait(mprj_io_0 == 28'd20);
- wait(mprj_io_0 == 28'd25);
- wait(mprj_io_0 == 28'd30);
+ // Observe Output pins [23:8] for multliplication_table
+ wait(mprj_io_0 == 16'd5);
+ wait(mprj_io_0 == 16'd10);
+ wait(mprj_io_0 == 16'd15);
+ wait(mprj_io_0 == 16'd20);
+ wait(mprj_io_0 == 16'd25);
+ wait(mprj_io_0 == 16'd30);
// Observe Output pins [35:8] for mean & Determinant
// wait(mprj_io_0 == 28'd5);
@@ -125,7 +125,7 @@
//wait(mprj_io_0 == 28'd2);
//wait(mprj_io_0 == 28'd1);
//wait(mprj_io_0 == 28'd0);
- $display("MPRJ-IO state = %d", mprj_io[35:8]);
+ $display("MPRJ-IO state = %d", mprj_io[23:8]);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
@@ -161,7 +161,7 @@
end
always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[35:8], $time);
+ #1 $display("MPRJ-IO state = %d, at time = %0t ", mprj_io[23:8], $time);
end
wire flash_csb;
@@ -170,32 +170,33 @@
wire flash_io1;
wire r_Rx_Serial;
assign mprj_io[5] = r_Rx_Serial;
- assign mprj_io[3:0] = 4'h0;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
-
- caravel uut (
+ caravel uut (
.vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
.vssio (VSS),
+ .vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
- .vdda1 (USER_VDD3V3),
- .vdda2 (USER_VDD3V3),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
.vssa1 (VSS),
+ .vssa1_2 (VSS),
.vssa2 (VSS),
- .vccd1 (USER_VDD1V8),
- .vccd2 (USER_VDD1V8),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
- .clock (clock),
+ .clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
