commit 3eeabd4833c2216c64cf30d9285cafb36f89f979
author hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 12:22:58 2022 +0500
committer hamzashabbir517 <shabbirhamza517@gmail.com> Sat May 21 12:22:58 2022 +0500
tree cde6a6c1685b5c4fe7217daa06b311a3120df510
parent 260b1757d9b4d713cad89860012052a456e9c452

Define added

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index ad7cc28..d369405 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -34,6 +34,7 @@
  *
  *-------------------------------------------------------------
  */
+`define MPRJ_IO_PADS 38
 
 module user_proj_example #(
     parameter BITS = 32