New files updated
diff --git a/verilog/dv/FPU_Half/FPU_Half_tb.v b/verilog/dv/FPU_Half/FPU_Half_tb.v index e5e9efc..fc60c6e 100644 --- a/verilog/dv/FPU_Half/FPU_Half_tb.v +++ b/verilog/dv/FPU_Half/FPU_Half_tb.v
@@ -136,7 +136,7 @@ wait(mprj_io_0 == 16'h0000); */ // Observe Output pins [23:8] for FADD/FSUB - + /* wait(mprj_io_0 == 16'h5848); wait(mprj_io_0 == 16'h3CE7); wait(mprj_io_0 == 16'h5A92); @@ -153,6 +153,44 @@ wait(mprj_io_0 == 16'hDCD8); wait(mprj_io_0 == 16'hDF04); wait(mprj_io_0 == 16'hBD78); + */ + // Observe Output pins [23:8] for FMADD/FMSUB + /* + wait(mprj_io_0 == 16'h60CB); + wait(mprj_io_0 == 16'h3475); + wait(mprj_io_0 == 16'h6805); + wait(mprj_io_0 == 16'h78E5); + wait(mprj_io_0 == 16'h7C00); + wait(mprj_io_0 == 16'hDC34); + wait(mprj_io_0 == 16'h5698); + wait(mprj_io_0 == 16'hBD78); + wait(mprj_io_0 == 16'h60B9); + wait(mprj_io_0 == 16'h2252); + wait(mprj_io_0 == 16'h67F5); + wait(mprj_io_0 == 16'h78d8); + wait(mprj_io_0 == 16'h7c00); + wait(mprj_io_0 == 16'h5d7e); + wait(mprj_io_0 == 16'h63dc); + wait(mprj_io_0 == 16'h3d78); + */ + // Observe Output pins [23:8] for FNMADD/FNMSUB + + wait(mprj_io_0 == 16'hE0B9); + wait(mprj_io_0 == 16'hA252); + wait(mprj_io_0 == 16'hE7F5); + wait(mprj_io_0 == 16'hF8D8); + wait(mprj_io_0 == 16'hFC00); + wait(mprj_io_0 == 16'hDD7E); + wait(mprj_io_0 == 16'hE3DC); + wait(mprj_io_0 == 16'hBD78); + wait(mprj_io_0 == 16'hE0CB); + wait(mprj_io_0 == 16'hB475); + wait(mprj_io_0 == 16'hE805); + wait(mprj_io_0 == 16'hF8E5); + wait(mprj_io_0 == 16'hfc00); + wait(mprj_io_0 == 16'h5c34); + wait(mprj_io_0 == 16'hd698); + wait(mprj_io_0 == 16'h3d78); $display("MPRJ-IO state = %h", mprj_io[23:8]);
diff --git a/verilog/rtl/FPU/Execution.v b/verilog/rtl/FPU/Execution.v index 25c7e48..b7c4601 100644 --- a/verilog/rtl/FPU/Execution.v +++ b/verilog/rtl/FPU/Execution.v
@@ -1,6 +1,6 @@ -module Execution(clk,rst_l,RS1_d,RS2_d,result,Flag_ADDI,Flag_LI,Activation_Signal,Flag_Reset,fpu_active,illegal_config,valid_execution,fs1_data,fs2_data,fs3_data,sfpu_op,fpu_pre,fpu_rounding,float_control,fpu_result_1,S_flag,dec_i0_rs1_en_d,dec_i0_rs2_en_d,IV_exception,fpu_complete,fpu_sel,fpu_result_rd_w,fpu_complete_rd); - input clk,rst_l,Flag_ADDI,Flag_LI,Flag_Reset,fpu_active,illegal_config,valid_execution,dec_i0_rs1_en_d,dec_i0_rs2_en_d; - input [31:0]RS1_d,RS2_d; +module Execution(clk,rst_l,RS1_d_w,RS2_d_w,result,Flag_ADDI_w,Flag_LI_w,Activation_Signal,Flag_Reset_w,fpu_active,illegal_config,valid_execution,fs1_data,fs2_data,fs3_data,sfpu_op,fpu_pre,fpu_rounding,float_control,fpu_result_1,S_flag,dec_i0_rs1_en_d,dec_i0_rs2_en_d,IV_exception,fpu_complete,fpu_sel,fpu_result_rd_w,fpu_complete_rd); + input clk,rst_l,Flag_ADDI_w,Flag_LI_w,Flag_Reset_w,fpu_active,illegal_config,valid_execution,dec_i0_rs1_en_d,dec_i0_rs2_en_d; + input [31:0]RS1_d_w,RS2_d_w; input [15:0]fs1_data,fs2_data,fs3_data; input [23:0]sfpu_op; input [2:0]fpu_pre,fpu_rounding; @@ -15,9 +15,33 @@ output [31:0]fpu_result_rd_w; output fpu_complete_rd; + reg [31:0]RS1_d,RS2_d; + reg Flag_ADDI,Flag_LI,Flag_Reset; + wire [31:0]result_w; wire complete; + always @(posedge clk) + begin + if(rst_l == 1'b0) + begin + RS1_d <= 32'h00000000; + RS2_d <= 32'h00000000; + Flag_ADDI <= 1'b0; + Flag_LI <= 1'b0; + Flag_Reset <= 1'b0; + end + else + begin + RS1_d <= RS1_d_w; + RS2_d <= RS2_d_w; + Flag_ADDI <= Flag_ADDI_w; + Flag_LI <= Flag_LI_w; + Flag_Reset <= Flag_Reset_w; + end + + end + FPU_exu FPU_Execution( .clk(clk), .rst_l(rst_l), @@ -29,8 +53,8 @@ .fpu_pre(fpu_pre), .dec_i0_rs1_en_d(dec_i0_rs1_en_d), // Qualify GPR RS1 data .dec_i0_rs2_en_d(dec_i0_rs2_en_d), // Qualify GPR RS2 data - .gpr_i0_rs1_d(RS1_d), // DEC data gpr - .gpr_i0_rs2_d(RS2_d), // DEC data gpr + .gpr_i0_rs1_d(RS1_d_w), // DEC data gpr + .gpr_i0_rs2_d(RS2_d_w), // DEC data gpr .fs1_data(fs1_data), .fs2_data(fs2_data), .fs3_data(fs3_data),
diff --git a/verilog/rtl/FPU/FPU_CSR.v b/verilog/rtl/FPU/FPU_CSR.v index fd3fa85..93812c9 100644 --- a/verilog/rtl/FPU/FPU_CSR.v +++ b/verilog/rtl/FPU/FPU_CSR.v
@@ -33,7 +33,10 @@ begin fflag <= (fflag_w & CSR_Write) ? CSR_Write_Data[4:0] : (fcsr_w & CSR_Write) ? CSR_Write_Data[4:0] : (fpu_complete) ? (fflag[4:0] | S_flag[4:0]) : fflag; frm <= (frm_w & CSR_Write) ? CSR_Write_Data[2:0] : (fcsr_w & CSR_Write) ? CSR_Write_Data[7:5] : frm; - fcsr <= (fcsr_w & CSR_Write) ? {24'h00000,CSR_Write_Data[7:0]} : (fpu_complete) ? ({24'h000000,frm,(fflag[4:0] | S_flag[4:0])}) : fcsr; + fcsr <= (fcsr_w & CSR_Write) ? {24'h00000,CSR_Write_Data[7:0]} : + (frm_w & CSR_Write) ? ({24'h000000,CSR_Write_Data[2:0],fflag[4:0]}) : + (fflag_w & CSR_Write) ? ({24'h000000,frm,CSR_Write_Data[4:0]}) : + (fpu_complete) ? ({24'h000000,frm,(fflag[4:0] | S_flag[4:0])}) : fcsr; end end
diff --git a/verilog/rtl/FPU/FPU_FSM_Control_Decode.v b/verilog/rtl/FPU/FPU_FSM_Control_Decode.v index 8bd5804..ef6757c 100644 --- a/verilog/rtl/FPU/FPU_FSM_Control_Decode.v +++ b/verilog/rtl/FPU/FPU_FSM_Control_Decode.v
@@ -2,103 +2,28 @@ input clk,rst_l,Activation_Signal,Active_Process,Multi_Cycle; input [31:0]Instruction; output Memory_Activation; - //output [23:0]Output_1_Hot_Encoded_Opcode; output reg[31:0]PC; output [31:0]Instruction_out; - //wire [23:0]Uncontrolled_Opcode; - reg [1:0]State; - wire [1:0]Next_State; + reg [2:0]State; + wire [2:0]Next_State; wire [4:0]Input_Opcode; wire Exception; - /* - sfpu[0] = Fadd - sfpu[1] = Fsubb - sfpu[2] = Fmul - sfpu[3] = Fdiv - sfpu[4] = Fsqrt - sfpu[5] = Fmin - sfpu[6] = Fmax - sfpu[7] = Fmvx - sfpu[8] = Fmvf - sfpu[9] = feq - sfpu[10] = flt - sfpu[11] = fle - sfpu[12] = Fmadd - sfpu[13] = Fmsubb - sfpu[14] = FCVT.W.P - sfpu[15] = FCVT.P.W - sfpu[16] = Fnmsubb - sfpu[17] = Fnmadd - sfpu[18] = fsgnj - sfpu[19] = fsgnjn - sfpu[20] = fsgnjx - sfpu[21] = fclass - sfpu[22] = unsign - sfpu[23] = sign - */ - /* - assign Input_Opcode = Instruction[4:0]; - - assign Output_1_Hot_Encoded_Opcode[0] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[1] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[2] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[3] = ~Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[4] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[5] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[6] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[7] = ~Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[8] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[9] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[10] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[11] = ~Input_Opcode[4] & Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[12] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[13] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[14] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[15] = ~Input_Opcode[4] & Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[16] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[17] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[18] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[19] = Input_Opcode[4] & ~Input_Opcode[3] & ~Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[20] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[21] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & ~Input_Opcode[1] & Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[22] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & ~Input_Opcode[0]; - assign Output_1_Hot_Encoded_Opcode[23] = Input_Opcode[4] & ~Input_Opcode[3] & Input_Opcode[2] & Input_Opcode[1] & Input_Opcode[0]; - - //assign Single_Cycle = (Output_1_Hot_Encoded_Opcode[0] | Output_1_Hot_Encoded_Opcode[1] | Output_1_Hot_Encoded_Opcode[2] | Output_1_Hot_Encoded_Opcode[5] | Output_1_Hot_Encoded_Opcode[6] | Output_1_Hot_Encoded_Opcode[7] | Output_1_Hot_Encoded_Opcode[8] | Output_1_Hot_Encoded_Opcode[9] | Output_1_Hot_Encoded_Opcode[10] | Output_1_Hot_Encoded_Opcode[11] | Output_1_Hot_Encoded_Opcode[14] | Output_1_Hot_Encoded_Opcode[15] | Output_1_Hot_Encoded_Opcode[18] | Output_1_Hot_Encoded_Opcode[19] | Output_1_Hot_Encoded_Opcode[20] | Output_1_Hot_Encoded_Opcode[21] | Output_1_Hot_Encoded_Opcode[22] | Output_1_Hot_Encoded_Opcode[23]); - assign Multi_Cycle = (Output_1_Hot_Encoded_Opcode[3] | Output_1_Hot_Encoded_Opcode[4] | Output_1_Hot_Encoded_Opcode[12] | Output_1_Hot_Encoded_Opcode[13] | Output_1_Hot_Encoded_Opcode[16] | Output_1_Hot_Encoded_Opcode[17]); - */ - //assign Multi_Cycle = 1'b0; - assign Memory_Activation = (((~Next_State[1]) & (Next_State[0])) & (Active_Process)); - assign Next_State[0] = (((~State[0]) & (State[1] | Active_Process)) | ((State[1] & State[0]) & ((~Activation_Signal) | (Activation_Signal & (~Multi_Cycle))))); - assign Next_State[1] = (((~State[1]) & (State[0])) | ((State[1]) & (~State[0])) | (State[1] & State[0] & (~Activation_Signal))); - assign Instruction_out = (~rst_l) ? 32'h00000000 : (State == 2'b10) ? Instruction : 32'h00000000; + assign Memory_Activation = (((~Next_State[2]) & (~Next_State[1]) & (Next_State[0])) & (Active_Process)); + assign Next_State[0] = ((((~State[2]) & (~State[0])) & (State[0] | Active_Process)) | ((State[2]) & (~State[1]) & (~State[0]) & (~Multi_Cycle) & (Activation_Signal))); + assign Next_State[1] = (((~State[2]) & (~State[1]) & (State[0])) | ((~State[2]) & (State[1]) & (~State[0]))); + assign Next_State[2] = (((~State[2]) & (State[1]) & (State[0])) | ((State[2]) & (~State[1]) & (~State[0]) & (~Activation_Signal))); + assign Instruction_out = (~rst_l) ? 32'h00000000 : (State == 3'b010) ? Instruction : 32'h00000000; always @(posedge clk) - PC <= (~rst_l) ? 32'h00000000 : ((State == 2'b01) ? (PC[31:0] + 4'h4) : (Instruction == 32'h00000010) ? 32'h00000000 : PC); + PC <= (~rst_l) ? 32'h00000000 : ((State == 3'b001) ? (PC[31:0] + 4'h4) : (Instruction == 32'h00000010) ? 32'h00000000 : PC); //sequential State register block always @(posedge clk) - State <= (~rst_l) ? 2'b00 : Next_State; - - - //combinational State assignment block - /*always @(posedge clk) - begin - if(Next_State==2'b00) - Output_1_Hot_Encoded_Opcode <= 24'h000000; - else if(State==2'b01) - Output_1_Hot_Encoded_Opcode <= Uncontrolled_Opcode; - else - Output_1_Hot_Encoded_Opcode <= Uncontrolled_Opcode; - end*/ - - /*initial - begin - $dumpfile("FPU_FSM.vcd"); - $dumpvars(0); - end*/ + State <= (~rst_l) ? 3'b000 : Next_State; endmodule + +
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v index e381fda..bc26f76 100644 --- a/verilog/rtl/FPU/FPU_FSM_TOP.v +++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -100,9 +100,13 @@ wire IV_exception; wire[2:0]fpu_sel; wire [31:0]fpu_result_rd_w; + + + assign FPU_hp_result = (rst_l == 1'b0) ? 16'h0000 : (fpu_complete_rd & Active_Process) ? fpu_result_rd_w[15:0] : (fpu_complete & ~fpu_complete_rd & Active_Process) ? fpu_result_1 : 16'h0000; + FPU_FSM FSM( .clk(clk), .rst_l(rst_l), @@ -189,13 +193,13 @@ Execution Excecution_Unit( .clk(clk), .rst_l(rst_l), - .RS1_d(RS1_d), - .RS2_d(RS2_d), + .RS1_d_w(RS1_d), + .RS2_d_w(RS2_d), .result(result), - .Flag_ADDI(Flag_ADDI), - .Flag_LI(Flag_LI), + .Flag_ADDI_w(Flag_ADDI), + .Flag_LI_w(Flag_LI), .Activation_Signal(Activation_Signal), - .Flag_Reset(Flag_Reset), + .Flag_Reset_w(Flag_Reset), .fpu_active(fpu_active), .illegal_config(illegal_config), .valid_execution(valid_execution),
diff --git a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v index 79cf168..17379a5 100644 --- a/verilog/rtl/FPU/FPU_Top_Single_Cycle.v +++ b/verilog/rtl/FPU/FPU_Top_Single_Cycle.v
@@ -13,7 +13,7 @@ `include "LZD_comb.v" `include "LZD_mux.v"*/ -module FPU_Top (Operand_A,Operand_B,Operand_C, clk,rst_l, frm, sfpu_op,vfpu_op,fpu_sel,FPU_resultant, S_Flags, Exception_flag, interupt_Pin,FPU_Result_rd,Operand_Int); +module FPU_Top (Operand_A_w,Operand_B_w,Operand_C_w, clk,rst_l, frm_w, sfpu_op_w,vfpu_op_w,fpu_sel_w,FPU_resultant, S_Flags, Exception_flag, interupt_Pin,FPU_Result_rd,Operand_Int_w); parameter std= 15; parameter man = 9; @@ -23,13 +23,13 @@ //inputs -input [std:0] Operand_A,Operand_B,Operand_C; +input [std:0] Operand_A_w,Operand_B_w,Operand_C_w; input clk,rst_l; -input [2:0] frm; -input [23:0] sfpu_op; -input [2:0] fpu_sel; -input [27:0] vfpu_op; -input [31:0] Operand_Int; +input [2:0] frm_w; +input [23:0] sfpu_op_w; +input [2:0] fpu_sel_w; +input [27:0] vfpu_op_w; +input [31:0] Operand_Int_w; //output output [std:0] FPU_resultant; @@ -42,7 +42,38 @@ reg [std:0] FPU_resultant_reg; reg[31:0] FPU_Result_rd_reg; reg [4:0] S_Flags_reg; +reg [std:0] Operand_A,Operand_B,Operand_C; +reg [2:0] frm; +reg [23:0] sfpu_op; +reg [2:0] fpu_sel; +reg [27:0] vfpu_op; +reg [31:0] Operand_Int; + always @(posedge clk) + begin + if(rst_l == 1'b0) + begin + Operand_A <= {(std+1){1'b0}}; + Operand_B <= {(std+1){1'b0}}; + Operand_C <= {(std+1){1'b0}}; + frm <= 3'b000; + sfpu_op <= 24'h000000; + fpu_sel <= 3'b000; + vfpu_op <= 28'h0000000; + Operand_Int <= 32'h00000000; + end + else + begin + Operand_A <= Operand_A_w; + Operand_B <= Operand_B_w; + Operand_C <= Operand_C_w; + frm <= frm_w; + sfpu_op <= sfpu_op_w; + fpu_sel <= fpu_sel_w; + vfpu_op <= vfpu_op_w; + Operand_Int <= Operand_Int_w; + end + end //assigment of interim register on outptu ports assign FPU_resultant = (rst_l) ? FPU_resultant_reg:32'h00000000; assign S_Flags = (rst_l) ? S_Flags_reg:5'b00000 ;
diff --git a/verilog/rtl/FPU/FPU_exu.v b/verilog/rtl/FPU/FPU_exu.v index eaa4786..479cfdf 100644 --- a/verilog/rtl/FPU/FPU_exu.v +++ b/verilog/rtl/FPU/FPU_exu.v
@@ -36,6 +36,8 @@ wire [4:0] fpu_flags; wire [31:0]FPU_Result_rd,Operand_Int; +reg [23:0] sfpu_op_r2; + // sfpu_op [0] = fadd // sfpu_op [1] = fsub // sfpu_op [2] = fmul @@ -61,16 +63,19 @@ // sfpu_op [22] = unsign // sfpu_op [23] = sign - rvdffe #(24) sfpu_op_ff (.*, .clk(clk), .en(valid_execution & fpu_sel[0]), .din(sfpu_op), .dout(sfpu_op_r)); + rvdffsc #(24) sfpu_op_ff (.clk(clk), .rst_l(rst_l), .en(valid_execution & fpu_sel[0]), .clear((/*(~valid_execution & ~fpu_active) & */fpu_complete)), .din(sfpu_op), .dout(sfpu_op_r)); + //rvdffe #(24) sfpu_op_ff (.*, .clk(clk), .en(valid_execution & fpu_sel[0]), .din(sfpu_op), .dout(sfpu_op_r)); //rvdffe #(FPLEN) fpu_result_ff (.*, .clk(clk), .en(fpu_complete), .din(fpu_result_exu), .dout(fpu_result_1)); rvdffs #(5) fpu_flags_ff (.*, .clk(clk), .en(fpu_complete), .din(fpu_flags), .dout(sflags)); always @(posedge clk) begin if(rst_l == 1'b0) begin sfpu_alu_valid_r <= 1'b0; + sfpu_op_r2 <= 24'h000000; end else begin - sfpu_alu_valid_r <= (|sfpu_op[2:0]) | (|sfpu_op[17:5]) | (|sfpu_op[21:18]); + sfpu_alu_valid_r <= (|sfpu_op_r[2:0]) | (|sfpu_op_r[17:5]) | (|sfpu_op_r[21:18]); + sfpu_op_r2 <= sfpu_op_r; end end @@ -87,19 +92,19 @@ FPU_Top Floating_Top ( .clk(clk), .rst_l(rst_l), - .frm(fpu_rnd), - .sfpu_op(sfpu_op), - .vfpu_op(28'h0000000), - .fpu_sel(fpu_sel), - .Operand_A(fs1_d), - .Operand_B(fs2_d), - .Operand_C(fs3_d), + .frm_w(fpu_rnd), + .sfpu_op_w(sfpu_op), + .vfpu_op_w(28'h0000000), + .fpu_sel_w(fpu_sel), + .Operand_A_w(fs1_d), + .Operand_B_w(fs2_d), + .Operand_C_w(fs3_d), .FPU_resultant(fpu_result_top), .S_Flags(fpu_flags), .Exception_flag(IV_exception), .interupt_Pin(), .FPU_Result_rd(FPU_Result_rd), - .Operand_Int(Operand_Int) + .Operand_Int_w(Operand_Int) ); @@ -107,11 +112,11 @@ assign fpu_complete = (rst_l == 1'b0) ? 1'b0 : (sfpu_alu_valid_r) ? 1'b1 : 1'b0; // FPU FPR Result - assign fpu_result_1 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (fpu_complete & (|sfpu_op_r[2:0] | (|sfpu_op_r[17:15]) | sfpu_op_r[7] | (|sfpu_op_r[20:18]) | (|sfpu_op_r[6:5]) | (|sfpu_op_r[13:12]))) ? fpu_result_top : {FPLEN{1'b0}}; + assign fpu_result_1 = (rst_l == 1'b0) ? {FPLEN{1'b0}} : (fpu_complete & (|sfpu_op_r2[2:0] | (|sfpu_op_r2[17:15]) | sfpu_op_r2[7] | (|sfpu_op_r2[20:18]) | (|sfpu_op_r2[6:5]) | (|sfpu_op_r2[13:12]))) ? fpu_result_top : {FPLEN{1'b0}}; // FPU GPR result - assign fpu_result_rd = (rst_l == 1'b0) ? {32{1'b0}} : (fpu_complete & ((|sfpu_op_r[11:9]) | sfpu_op_r[14] | sfpu_op_r[8] | sfpu_op_r[21])) ? FPU_Result_rd : + assign fpu_result_rd = (rst_l == 1'b0) ? {32{1'b0}} : (fpu_complete & ((|sfpu_op_r2[11:9]) | sfpu_op_r2[14] | sfpu_op_r2[8] | sfpu_op_r2[21])) ? FPU_Result_rd : {32{1'b0}}; - assign fpu_complete_rd = (~rst_l) ? 1'b0 : (fpu_complete & ((|sfpu_op_r[11:8]) | sfpu_op_r[14] | sfpu_op_r[21])) ? 1'b1 : 1'b0; + assign fpu_complete_rd = (~rst_l) ? 1'b0 : (fpu_complete & ((|sfpu_op_r2[11:8]) | sfpu_op_r2[14] | sfpu_op_r2[21])) ? 1'b1 : 1'b0; endmodule
diff --git a/verilog/rtl/FPU/Main_Decode.v b/verilog/rtl/FPU/Main_Decode.v index 95a0e39..37cf693 100644 --- a/verilog/rtl/FPU/Main_Decode.v +++ b/verilog/rtl/FPU/Main_Decode.v
@@ -17,10 +17,9 @@ wire [2:0] fpu_rnd,Fpu_Frm; wire [11:0]IMM_ADDI,CSR_Addr; wire [31:0]IMM_LI; - reg [4:0]rd; + reg [4:0]rd,rd_wb; wire [4:0] rd_address; wire [4:0]rs1,rs2,rs1_address,rs2_address; - //reg [31:0]Instruction_reg; wire [31:0]gpr_rs1,gpr_rs2; wire [2:0] Function_CSR; wire [31:0] CSR_Read_Data,CSR_Write_Data; @@ -32,20 +31,21 @@ wire write_en; wire illegal_instr; wire [23:0]sfpu_op_w; + wire Flag_CSR_r1; + wire CSR_Read_r1; + wire [31:0] CSR_Read_Data_r1; + rvdffsc #(1) CSR_Flag_ff (.clk(clk), .rst_l(rst_l), .en(Flag_CSR), .clear(~Flag_CSR), .din(Flag_CSR), .dout(Flag_CSR_r1)); + rvdffsc #(1) CSR_Read_ff (.clk(clk), .rst_l(rst_l), .en(Flag_CSR), .clear(~Flag_CSR), .din((CSR_Read & ~fpu_active)), .dout(CSR_Read_r1)); + rvdffsc #(32) CSR_Read_Data_ff (.clk(clk), .rst_l(rst_l), .en(Flag_CSR), .clear(~Flag_CSR), .din(CSR_Read_Data), .dout(CSR_Read_Data_r1)); + always @(posedge clk) begin - /* if (rst_l) - Instruction_reg <= Instruction; - else - Instruction_reg <= 32'h00000000; - */ - if (rst_l) begin - CSR_Read_Data_r <= CSR_Read_Data; - CSR_Read_r <= (CSR_Read & ~fpu_active); - Flag_CSR_r <= Flag_CSR; + CSR_Read_Data_r <= CSR_Read_Data_r1; + CSR_Read_r <= CSR_Read_r1; + Flag_CSR_r <= Flag_CSR_r1; end else begin @@ -54,12 +54,8 @@ Flag_CSR_r <= 1'b0; end - rd = (~rst_l) ? 5'b00000 : (Instruction[11:7] != 5'b00000) ? Instruction[11:7] : 5'b00000; - - //Flag_ADDI = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0010011) ? 1'b1 : 1'b0; - //Flag_LI = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b0110111) ? 1'b1 : 1'b0; - //RS2_d = (~rst_l) ? 32'h00000000 : Flag_LI ? IMM_LI : (Flag_ADDI) ? {{20{IMM_ADDI[11]}},IMM_ADDI} : gpr_rs2; - //RS1_d = (~rst_l) ? 32'h00000000 : gpr_rs1; + rd <= (~rst_l) ? 5'b00000 : (Instruction[11:7] != 5'b00000) ? Instruction[11:7] : 5'b00000; + rd_wb <= (~rst_l) ? 5'b00000 : rd; end @@ -71,7 +67,7 @@ .raddr0(rs1), .raddr1(rs2), .wen0(write_en), - .waddr0(rd), + .waddr0(rd_wb), .wd0((CSR_Read_r) ? CSR_Read_Data_r : (fpu_complete_rd & (~Activation_Signal) & (~CSR_Read_r)) ? fpu_result_rd_w : result), .rd0(gpr_rs1), .rd1(gpr_rs2), @@ -129,8 +125,8 @@ // INTEGER REGISTER FILE ASSIGNEMENTS - assign rs1_en = (~rst_l) ? 1'b0 : ((Instruction[11:7] != 5'b00000) & (~fpu_active)) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[0] : 1'b0; - assign rs2_en = (~rst_l) ? 1'b0 : (Instruction[11:7] != 5'b00000) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[1] : 1'b0; + assign rs1_en = (~rst_l) ? 1'b0 : ((Instruction[19:15] != 5'b00000) & (~fpu_active)) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[0] : 1'b0; + assign rs2_en = (~rst_l) ? 1'b0 : ((Instruction[24:20] != 5'b00000) & (~fpu_active) & (~Flag_CSR)) ? 1'b1 : (fpu_active & ~illegal_instr) ? scalar_control[1] : 1'b0; assign rs1 = (~rst_l) ? 5'b00000 : (Flag_ADDI) ? Instruction[19:15] : ((Function_CSR == 3'b001) & Flag_CSR) ? Instruction[19:15] : (fpu_active & ~illegal_instr) ? rs1_address : 5'b00000; assign rs2 = (~rst_l) ? 5'b00000 : (fpu_active & ~illegal_instr) ? rs2_address : 5'b00000; assign RS2_d = (~rst_l) ? 32'h00000000 : Flag_LI ? IMM_LI : (Flag_ADDI) ? {{20{IMM_ADDI[11]}},IMM_ADDI} : gpr_rs2; @@ -140,7 +136,7 @@ // CSRRW & CSRRWI instructions ASSIGNEMENTS assign Flag_CSR = (~rst_l) ? 1'b0 : (Instruction[6:0] == 7'b1110011) ? 1'b1 : 1'b0; assign Function_CSR = (~rst_l) ? 3'b000 : (Flag_CSR) ? Instruction[14:12] : 3'b000; - assign CSR_Addr = (~rst_l) ? 12'h000 : (fpu_active & (~illegal_instr) & (~fpu_complete)) ? 12'h001 : Instruction[31:20]; + assign CSR_Addr = (~rst_l) ? 12'h000 : (fpu_active & (~illegal_instr) & (~fpu_complete)) ? 12'h002 : Instruction[31:20]; assign CSR_Read = (~rst_l) ? 1'b0 : ((Instruction[11:7] != 5'b00000) & Flag_CSR) ? 1'b1 : (fpu_active & (~illegal_instr) & (~fpu_complete)) ? 1'b1 : 1'b0; assign CSR_Write = (~rst_l) ? 1'b0 : (Flag_CSR) ? 1'b1 : (fpu_active & (~illegal_instr) & fpu_complete) ? 1'b1 : 1'b0; assign CSR_Write_Data = (~rst_l) ? 32'h00000000 : (Flag_CSR & (Function_CSR == 3'b101)) ? {27'h0000000,Instruction[19:15]} : RS1_d;