Updation in RTL files
diff --git a/verilog/dv/FPU_Half/FPU_Half.c b/verilog/dv/FPU_Half/FPU_Half.c
index 55b8f94..42cd35c 100644
--- a/verilog/dv/FPU_Half/FPU_Half.c
+++ b/verilog/dv/FPU_Half/FPU_Half.c
@@ -66,9 +66,9 @@
// Configure LA probes as inputs to the cpu put zero
// Configure LA probes as outputs from the cpu put one
- reg_la2_oenb = reg_la2_iena = 0x00000002; // 64 bit as input to user proj and output from cpu
+ reg_la2_oenb = reg_la2_iena = 0x00000002; // 65 bit as input to user proj and output from cpu for reset
reg_la2_data = 0x00000000; // reset
- reg_la2_data = 0x00000001;
+ reg_la2_data = 0x00000002;
reg_la2_oenb = reg_la2_iena = 0x00000003; // 64 anf 65 bit as input to user proj and output from cpu
//reg_la1_oenb = reg_la1_iena = 0x00000000;
diff --git a/verilog/rtl/FPU/FPU_FSM_TOP.v b/verilog/rtl/FPU/FPU_FSM_TOP.v
index 6c200da..1e01b07 100644
--- a/verilog/rtl/FPU/FPU_FSM_TOP.v
+++ b/verilog/rtl/FPU/FPU_FSM_TOP.v
@@ -49,14 +49,20 @@
`include "LZD_comb.v"
*/
-module FPU_FSM_TOP(r_Rx_Serial,clk,rst_l);
+module FPU_FSM_TOP(vccd1,vssd1,r_Rx_Serial,clk,rst_l,FPU_hp_result);
+`ifdef USE_POWER_PINS
+ inout vccd1; // User area 1 1.8V supply
+ inout vssd1; // User area 1 digital ground
+`endif
// FPU UART
input r_Rx_Serial;
// FPU UART
// FPU FSM
input clk,rst_l;
+
+ output [15:0] FPU_hp_result;
// FPU FSM
wire o_Rx_DV;
@@ -93,6 +99,10 @@
wire[2:0]fpu_sel;
wire [31:0]fpu_result_rd_w;
+
+
+ assign FPU_hp_result = (rst_l == 1'b0) ? 16'h0000 : (fpu_result_rd_w & Active_Process) ? fpu_complete_rd[15:0] : (fpu_complete & ~fpu_result_rd_w & Active_Process) ? fpu_result_1 : 16'h0000;
+
FPU_FSM FSM(
.clk(clk),
.rst_l(rst_l),
@@ -106,6 +116,10 @@
);
sky130_sram_1kbyte_1rw1r_32x256_8 SKY130(
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V supply
+ .vssd1(vssd1), // User area 1 digital ground
+ `endif
.clk0(clk),
.csb0(~we_o),
.web0(~we_o),
@@ -213,10 +227,6 @@
.fpu_active(fpu_active)
);
- initial
- begin
- $dumpfile("FPU_FSM.vcd");
- $dumpvars(0);
- end
+
endmodule
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..9224a38 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -70,96 +70,44 @@
);
wire clk;
wire rst;
+ wire rx_i;
+ wire [15:0] FPU_hp_result;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
- wire [31:0] rdata;
- wire [31:0] wdata;
- wire [BITS-1:0] count;
- wire valid;
- wire [3:0] wstrb;
- wire [31:0] la_write;
-
- // WB MI A
- assign valid = wbs_cyc_i && wbs_stb_i;
- assign wstrb = wbs_sel_i & {4{wbs_we_i}};
- assign wbs_dat_o = rdata;
- assign wdata = wbs_dat_i;
-
- // IO
- assign io_out = count;
- assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+ // IO for input mode set 1 and for output mode set 0
+ assign io_oeb[5] = 1'b1;
+ assign io_oeb[23:8] = 16'h0000;
+ assign io_out[23:8] = FPU_hp_result;
+
+ // Uart Pin
+ assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];
// IRQ
assign irq = 3'b000; // Unused
// LA
- assign la_data_out = {{(127-BITS){1'b0}}, count};
- // Assuming LA probes [63:32] are for controlling the count register
- assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+ assign la_data_out = {{127{1'b0}}};
+
// Assuming LA probes [65:64] are for controlling the count clk & reset
- assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+ assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
+ assign rst = (~la_oenb[65]) ? la_data_in[65] : ~wb_rst_i;
- counter #(
- .BITS(BITS)
- ) counter(
- .clk(clk),
- .reset(rst),
- .ready(wbs_ack_o),
- .valid(valid),
- .rdata(rdata),
- .wdata(wbs_dat_i),
- .wstrb(wstrb),
- .la_write(la_write),
- .la_input(la_data_in[63:32]),
- .count(count)
- );
+ // Initiation of TOP Module
+ FPU_FSM_TOP FPU_Half_Precision_Top (
+ `ifdef USE_POWER_PINS
+ .vccd1(vccd1), // User area 1 1.8V supply
+ .vssd1(vssd1), // User area 1 digital ground
+ `endif
+ .clk(clk),
+ .rst_l(rst),
+ .r_Rx_Serial(rx_i),
+ .FPU_hp_result(FPU_hp_result)
+ );
endmodule
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
- end
-
-endmodule
`default_nettype wire
