initial commit
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
+ Apache License
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diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..664859b
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,141 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+PDK_ROOT?=/usr/local/share/pdk/sky130A
+INPUT_DIRECTORY?=/home/krishna/Z_submit
+CARAVEL_ROOT?=/home/krishna/Z_submit
+PRECHECK_ROOT?=/home/krishna/mpw_precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1)
+ CARAVEL_NAME := caravel-lite
+ CARAVEL_REPO := https://github.com/efabless/caravel-lite
+ CARAVEL_TAG := 'mpw-5a'
+else
+ CARAVEL_NAME := caravel
+ CARAVEL_REPO := https://github.com/efabless/caravel
+ CARAVEL_TAG := 'mpw-5a'
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : ./verilog/dv/%
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+ cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ @echo "Installing $(CARAVEL_NAME).."
+ @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+ $(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+ mkdir -p openlane
+ cd openlane &&\
+ ln -sf $(MAKEFILE_PATH) Makefile
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+ rm -rf $(CARAVEL_ROOT)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+ @git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+ @docker pull efabless/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-pdk check-precheck
+ $(eval INPUT_DIRECTORY := $(shell pwd))
+ cd $(PRECHECK_ROOT) && \
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+
+# Clean
+.PHONY: clean
+clean:
+ cd ./verilog/dv/ && \
+ $(MAKE) -j$(THREADS) clean
+
+check-caravel:
+ @if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+ echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-precheck:
+ @if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+ echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+check-pdk:
+ @if [ ! -d "$(PDK_ROOT)" ]; then \
+ echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+ exit 1; \
+ fi
+
+.PHONY: help
+help:
+ cd $(CARAVEL_ROOT) && $(MAKE) help
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..c553d66
--- /dev/null
+++ b/README.md
@@ -0,0 +1,19 @@
+# CMOS Rail-To-Rail Comparator
+This project is the implementation of a simple rail-to-rail comparator with its bias circuitry using Skywater 130nm technology.
+The purpose of this project is to test the open source tools provided with the PDK and to go through all the steps of the analog design flow.
+Two different circuits are instantiated in the analog version of the caravel:
+- A CMOS push-pull comparator with 2 differential pairs (NMOS and PMOS).
+- A bootstrap current reference.
+
+## CMOS Comparator
+The schematic of the comparator was deisgned as follows :
+
+
+## Bias circuit
+The schematic of the bias circuit was deisgned as follows :
+
+
+## Simulation
+We simulated the comparator with a voltage ramp at the negative input and a sinusoidal signal at the positive input. The output is a digital signal that triggers at the intersection of the 2 analog input signals.
+
+
diff --git a/docs/Makefile b/docs/Makefile
new file mode 100644
index 0000000..c715218
--- /dev/null
+++ b/docs/Makefile
@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS ?=
+SPHINXBUILD ?= sphinx-build
+SOURCEDIR = source
+BUILDDIR = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+ @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+ @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
diff --git a/docs/environment.yml b/docs/environment.yml
new file mode 100644
index 0000000..2bddf94
--- /dev/null
+++ b/docs/environment.yml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+ - -r file:requirements.txt
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 0000000..f5c5383
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,6 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
diff --git a/docs/source/conf.py b/docs/source/conf.py
new file mode 100644
index 0000000..f960f13
--- /dev/null
+++ b/docs/source/conf.py
@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+ 'sphinxcontrib.wavedrom',
+ 'sphinx.ext.mathjax',
+ 'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+ 'build',
+ 'Thumbs.db',
+ # Files included in other rst files.
+ 'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+ 'header_links' : [
+ ("Home", 'index', False, 'home'),
+ ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+ ],
+ 'hide_symbiflow_links': True,
+ 'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages. See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True
diff --git a/docs/source/index.rst b/docs/source/index.rst
new file mode 100644
index 0000000..b5f711d
--- /dev/null
+++ b/docs/source/index.rst
@@ -0,0 +1,337 @@
+.. raw:: html
+
+ <!---
+ # SPDX-FileCopyrightText: 2020 Efabless Corporation
+ #
+ # Licensed under the Apache License, Version 2.0 (the "License");
+ # you may not use this file except in compliance with the License.
+ # You may obtain a copy of the License at
+ #
+ # http://www.apache.org/licenses/LICENSE-2.0
+ #
+ # Unless required by applicable law or agreed to in writing, software
+ # distributed under the License is distributed on an "AS IS" BASIS,
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
+ #
+ # SPDX-License-Identifier: Apache-2.0
+ -->
+
+Caravel Analog User Project
+===========================
+
+|License| |User CI| |Caravan Build|
+
+Table of contents
+=================
+
+- `Overview <#overview>`__
+- `Install Caravel <#install-caravel>`__
+- `Caravel Integration <#caravel-integration>`__
+
+ - `User Project: Power on Reset <#user-project-power-on-reset>`_
+ - `Verilog Integration <#verilog-integration>`__
+
+- `Running Full Chip Simulation <#running-full-chip-simulation>`__
+- `Analog Design Flow <#analog-design-flow>`__
+- `Other Miscellaneous Targets <#other-miscellaneous-targets>`_
+- `Checklist for Open-MPW
+ Submission <#checklist-for-open-mpw-submission>`__
+
+Overview
+========
+
+This repo contains a sample user project that utilizes the caravan chip (analog version of `caravel <https://github.com/efabless/caravel.git>`__) user space. The user project is a simple power-on-reset that showcases how to make use of caravan's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the open-mpw **analog** projects.
+
+Install Caravel
+===============
+
+To setup caravel, run the following:
+
+.. code:: bash
+
+ # By default, CARAVEL_ROOT is set to $(pwd)/caravel
+ # If you want to install caravel at a different location, run "export CARAVEL_ROOT=<caravel-path>"
+ # Disable submodule installation if needed by, run "export SUBMODULE=0"
+
+ git clone https://github.com/efabless/caravel_user_project_analog.git
+ cd caravel_user_project_analog
+ make install
+
+To update the installed caravel to the latest, run:
+
+.. code:: bash
+
+ make update_caravel
+
+To remove caravel, run
+
+.. code:: bash
+
+ make uninstall
+
+By default
+`caravel-lite <https://github.com/efabless/caravel-lite.git>`__ is
+installed. To install the full version of caravel, run this prior to
+calling make install.
+
+.. code:: bash
+
+ export CARAVEL_LITE=0
+
+Caravel Integration
+=====================
+
+
+User Project: Power on Reset
+----------------------------
+
+This is an example user analog project which breaks out the power-on-reset
+circuit used by the management SoC for power-up behavior so that the circuit
+input and output can be independently controlled and measured.
+
+The power-on-reset circuit itself is a simple, non-temperature-compensated
+analog delay calibrated to 15ms under nominal conditions, with a Schmitt
+trigger inverter to provide hysteresis around the trigger point to provide
+a clean output reset signal.
+
+The circuit provides a single high-voltage (3.3V domain) sense-inverted reset
+signal "porb_h" and complementary low-voltage (1.8V domain) reset signals
+"por_l" and "porb_l".
+
+The only input to the circuit is the 3.3V domain power supply itself.
+
+
+Verilog Integration
+-------------------
+
+You need to create a wrapper around your macro that adheres to the
+template at
+`user\_analog_project\_wrapper <https://github.com/efabless/caravel/blob/master/verilog/rtl/__user_analog_project_wrapper.v>`__.
+The wrapper top module must be named ``user_analog_project_wrapper`` and must
+have the same input and output ports as the analog wrapper template. The wrapper gives access to the
+user space utilities provided by caravel like IO ports, logic analyzer
+probes, and wishbone bus connection to the management SoC.
+
+The verilog modules instantiated in the wrapper module should represent
+the analog project; they need not be more than empty blocks, but it is
+encouraged to write a simple behavioral description of the analog circuit
+in standard verilog, using real-valued wires when necessary. This allows
+the whole system to be run in a verilog testbench and verify the connectivity
+to the padframe and management SoC, even if the testbench C code does nothing
+more than set the mode of each GPIO pin. The example top-level verilog code
+emulates the behavior of the power-on-reset delay after applying a valid
+power supply to the circuit.
+
+
+Building the PDK
+================
+
+You have two options for building the pdk:
+
+- Build the pdk natively.
+
+Make sure you have `Magic VLSI Layout Tool <http://opencircuitdesign.com/magic/index.html>`__ `version 8.3.160 <https://github.com/RTimothyEdwards/magic/tree/8.3.160>`__ installed on your machine before building the pdk.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk
+
+- Build the pdk using openlane's docker image which has magic installed.
+
+.. code:: bash
+
+ # set PDK_ROOT to the path you wish to use for the pdk
+ export PDK_ROOT=<pdk-installation-path>
+
+ # you can optionally specify skywater-pdk and open-pdks commit used
+ # by setting and exporting SKYWATER_COMMIT and OPEN_PDKS_COMMIT
+ # if you do not set them, they default to the last verfied commits tested for this project
+
+ make pdk-nonnative
+
+Running Full Chip Simulation
+============================
+
+First, you will need to install the simulation environment, by
+
+.. code:: bash
+
+ make simenv
+
+This will pull a docker image with the needed tools installed.
+
+To install the simulation environment locally, refer to `README <https://github.com/efabless/caravel_user_project_analog/blob/main/verilog/dv/README.md>`__
+
+Then, run the RTL and GL simulation by
+
+.. code:: bash
+
+ export PDK_ROOT=<pdk-installation-path>
+ export CARAVEL_ROOT=$(pwd)/caravel
+ # specify simulation mode: RTL/GL
+ export SIM=RTL
+ # Run the mprj_por testbench, make verify-mprj_por
+ make verify-<testbench-name>
+
+The verilog test-benches are under this directory
+`verilog/dv <https://github.com/efabless/caravel_user_project_analog/tree/main/verilog/dv>`__.
+
+
+Analog Design Flow
+===================
+
+The example project uses a very simple analog design flow with schematics
+made with xschem, simulation done using ngspice, layout done with magic,
+and LVS verification done with netgen. Sources for the power-on-reset
+circuit are in the "xschem/" directory, which also includes a schematic
+representing the wrapper with all of its ports, for use in a testbench
+circuit. There are several testbenches in the example, starting from
+tests of the component devices to a full test of the completed project
+inside the wrapper.
+
+There is no automation in this project; the schematic and layout were
+done by hand, including both the power-on-reset block and the power and
+signal routing to the pins on the wrapper.
+
+The power-on-reset circuit itself is simple and is not compensated for
+temperature or voltage variation. When the power supply reaches a
+sufficient level, the voltage divider sets the gate voltage on an nFET
+device to draw a current of nominally 240nA. The testbench
+"threshold_test_tb.spice" does a DC sweep to find the gate voltage that
+produces this value. Next, a cascaded current mirror divides down the
+current by a factor of (roughly) 400. The testbench current_test.spice
+checks the current division value. Finally, the output ~600pA from the
+end of the current mirror is accumulated on a capacitor until the value
+trips the input of the 3.3V Schmitt trigger buffer from the
+sky130_fd_sd_hvl library. The capacitor is sized to peg the nominal
+time to trigger at 15ms. The schematic "example_por_tb.sch" sets up
+the testbench for this timing test.
+
+The output of the Schmitt trigger buffer becomes the high-voltage
+output, and is input to a standard buffer and inverter used as
+level shifters from the 3.3V domain to the 1.8V domain, producing
+complementary low-voltage outputs.
+
+The user project is formed from two power-on-reset circuits, one of
+which is connected to the user area VDDA1 power supply, and the other
+of which is connected to one of the analog I/O pads, used as a power
+supply input and connected to its voltage ESD clamp circuit. The
+3.3V domain outputs are connected directly to GPIO pads through the
+ESD (150 ohm series) connection. The 1.8V domain outputs are connected
+to GPIO pads through the usual I/O connections, with the corresponding
+user output enable (sense inverted) held low to keep the output always
+active.
+
+The C code testbench is in "verilog/dv/mprj_por/mprj_por.c" and only
+sets the GPIO pins used to the correct state (user output function).
+The POR circuit outputs are monitored by the testbench verilog file
+"mprj_por_tb.v" which will fail if the connections are wrong or if
+the behavioral POR verilog does not work as intended.
+
+Note that to properly test this circuit, the GPIO pins have to be
+configured for output to be seen and measured, implying that the
+management SoC power supply must be stable and the C program running
+off of the SPI flash before the user area power supplies are raised.
+
+**NOTE**
+
+ When running spice extraction on the user_analog_project_wrapper layout, it is recommended to use `ext2spice short resistor`.
+ This is to preserve all the different port names in the extracted netlist. In case you have two ports that are electrically shorted
+ in the layout, the `short resistor` option will tell magic not to merge the two shorted ports instead it adds zero-ohm ideal resistors
+ between the net names so that they can be kept as separate nets.
+
+
+Running Open-MPW Precheck Locally
+=================================
+
+You can install the precheck by running
+
+.. code:: bash
+
+ # By default, this install the precheck in your home directory
+ # To change the installtion path, run "export PRECHECK_ROOT=<precheck installation path>"
+ make precheck
+
+This will clone the precheck repo and pull the latest precheck docker image.
+
+
+Then, you can run the precheck by running
+Specify CARAVEL_ROOT before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+ make run-precheck
+
+This will run all the precheck checks on your project and will retain the logs under the ``checks`` directory.
+
+Other Miscellaneous Targets
+============================
+
+The makefile provides a number of useful that targets that can run compress, uncompress, and run XOR checks on your design.
+
+Compress gds files and any file larger than 100MB (GH file size limit),
+
+.. code:: bash
+
+ make compress
+
+Uncompress files,
+
+.. code:: bash
+
+ make uncompress
+
+
+Specify ``CARAVEL_ROOT`` before running any of the following,
+
+.. code:: bash
+
+ # export CARAVEL_ROOT=$(pwd)/caravel
+ export CARAVEL_ROOT=<path-to-caravel>
+
+Run XOR check,
+
+.. code:: bash
+
+ make xor-analog-wrapper
+
+Checklist for Open-MPW Submission
+=================================
+
+
+|:heavy_check_mark:| The project repo adheres to the same directory structure in this repo.
+
+|:heavy_check_mark:| The project repo contain info.yaml at the project root.
+
+|:heavy_check_mark:| Top level macro is named ``user_analog_project_wrapper``.
+
+|:heavy_check_mark:| Full Chip Simulation passes for RTL and GL (gate-level)
+
+|:heavy_check_mark:| The project contains a spice netlist for the ``user_analog_project_wrapper`` at netgen/user_analog_project_wrapper.spice
+
+|:heavy_check_mark:| The hardened Macros are LVS and DRC clean
+
+|:heavy_check_mark:| The ``user_analog_project_wrapper`` adheres to empty wrapper template order specified at `user_analog_project_wrapper_empty <https://github.com/efabless/caravel/blob/master/mag/user_analog_project_wrapper_empty.mag>`__
+
+|:heavy_check_mark:| XOR check passes with zero total difference.
+
+|:heavy_check_mark:| Open-MPW-Precheck tool runs successfully.
+
+
+.. |License| image:: https://img.shields.io/badge/License-Apache%202.0-blue.svg
+ :target: https://opensource.org/licenses/Apache-2.0
+.. |User CI| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/user_project_ci.yml
+.. |Caravan Build| image:: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml/badge.svg
+ :target: https://github.com/efabless/caravel_user_project_analog/actions/workflows/caravan_build.yml
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
new file mode 100644
index 0000000..47d8b0f
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..05e4c09
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+ description: "CMOS Rail-to-Rail Comparator"
+ foundry: "SkyWater"
+ git_url: "https://github.com/maherbenhouria/caravel_user_project_analog.git"
+ organization: "Efabless"
+ organization_url: "http://efabless.com"
+ owner: "Maher Benhouria"
+ process: "SKY130"
+ project_name: "Caravel"
+ project_id: "00000000"
+ tags:
+ - "Open MPW"
+ - "Comparator"
+ category: "Comparator"
+ top_level_netlist: "caravel/verilog/gl/caravel.v"
+ user_level_netlist: "verilog/rtl/user_project_wrapper.v"
+ version: "1.00"
+ cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git "a/mag/buffer_1\0430.ext" "b/mag/buffer_1\0430.ext"
new file mode 100644
index 0000000..fc4c98e
--- /dev/null
+++ "b/mag/buffer_1\0430.ext"
@@ -0,0 +1,22 @@
+timestamp 1646324508
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W2 inv_W2_0 1 0 588 0 1 72
+use inv_W1 inv_W1_0 1 0 100 0 1 72
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W2_0/GND" "inv_W2_0/Vin" 32.2784
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "inv_W2_0/VDD" 116.829
+cap "inv_W2_0/GND" "inv_W1_0/Vin" 2.90674
+cap "inv_W2_0/Vin" "inv_W2_0/VDD" 33.1221
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "inv_W2_0/Vin" 23.6443
+cap "inv_W2_0/GND" "inv_W2_0/VDD" -1.77636e-15
+cap "inv_W2_0/Vin" "inv_W1_0/Vin" 11.0875
+merge "inv_W1_0/VSUBS" "inv_W2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VSUBS" "VSUBS"
+merge "inv_W1_0/Vout" "inv_W2_0/Vin" -32.196 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1120 -152 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/w_156_432#" "inv_W2_0/VDD" -52.545 0 0 0 0 -7640 -804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1000 -140 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VDD" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#"
+merge "inv_W1_0/GND" "inv_W2_0/GND" -30.482 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1040 -144 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/buffer_1\0430.mag" "b/mag/buffer_1\0430.mag"
new file mode 100755
index 0000000..9a3422f
--- /dev/null
+++ "b/mag/buffer_1\0430.mag"
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+timestamp 1646324508
+use inv_W1 inv_W1_0
+timestamp 1645263751
+transform 1 0 50 0 1 36
+box -50 -36 194 439
+use inv_W2 inv_W2_0
+timestamp 1646324451
+transform 1 0 294 0 1 36
+box -60 -36 202 439
+<< end >>
diff --git "a/mag/buffer_2\0430.ext" "b/mag/buffer_2\0430.ext"
new file mode 100644
index 0000000..319dcb9
--- /dev/null
+++ "b/mag/buffer_2\0430.ext"
@@ -0,0 +1,27 @@
+timestamp 1646326308
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W16 inv_W16_0 1 0 1708 0 1 0
+use inv_W8 inv_W8_0 1 0 -354 0 1 0
+node "Vout" 15 44.2028 4850 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1666_500#" 1943 420 1666 500 nw 0 0 0 0 140000 1500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W16_0/a_82_816#" "inv_W8_0/a_466_816#" 1.35641
+cap "inv_W16_0/a_468_358#" "inv_W16_0/li_n14_902#" 15.1736
+cap "inv_W16_0/a_468_358#" "inv_W8_0/a_466_816#" 16.3371
+cap "inv_W16_0/a_468_358#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 48.7475
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 120.656
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 105.456
+cap "inv_W16_0/li_n14_0#" "inv_W16_0/a_468_358#" -0.171875
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "inv_W16_0/li_n14_902#" 16.9157
+merge "inv_W8_0/VSUBS" "inv_W16_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/VSUBS" "VSUBS"
+merge "inv_W8_0/li_512_546#" "inv_W16_0/a_468_358#" -8.3746 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/li_354_0#" "inv_W16_0/li_n14_0#" -8.0948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/w_354_500#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 271.488 0 0 0 0 90496 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_1666_500#"
+merge "inv_W8_0/li_354_902#" "inv_W16_0/li_n14_902#" -25.0105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/li_128_546#" "Vout" -44.2028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2576 -204 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/buffer_2\0430.mag" "b/mag/buffer_2\0430.mag"
new file mode 100755
index 0000000..12f4f9a
--- /dev/null
+++ "b/mag/buffer_2\0430.mag"
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1646326308
+<< nwell >>
+rect 833 250 1008 450
+<< locali >>
+rect 2425 218 2448 246
+use inv_W8 inv_W8_0
+timestamp 1646325197
+transform 1 0 -177 0 1 0
+box 177 0 1025 477
+use inv_W16 inv_W16_0
+timestamp 1646325283
+transform 1 0 854 0 1 0
+box -7 0 1594 477
+<< labels >>
+rlabel locali 2448 232 2448 232 3 Vout
+<< end >>
diff --git "a/mag/buffer_2\0431.ext" "b/mag/buffer_2\0431.ext"
new file mode 100644
index 0000000..319dcb9
--- /dev/null
+++ "b/mag/buffer_2\0431.ext"
@@ -0,0 +1,27 @@
+timestamp 1646326308
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W16 inv_W16_0 1 0 1708 0 1 0
+use inv_W8 inv_W8_0 1 0 -354 0 1 0
+node "Vout" 15 44.2028 4850 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1666_500#" 1943 420 1666 500 nw 0 0 0 0 140000 1500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W16_0/a_82_816#" "inv_W8_0/a_466_816#" 1.35641
+cap "inv_W16_0/a_468_358#" "inv_W16_0/li_n14_902#" 15.1736
+cap "inv_W16_0/a_468_358#" "inv_W8_0/a_466_816#" 16.3371
+cap "inv_W16_0/a_468_358#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 48.7475
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 120.656
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 105.456
+cap "inv_W16_0/li_n14_0#" "inv_W16_0/a_468_358#" -0.171875
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "inv_W16_0/li_n14_902#" 16.9157
+merge "inv_W8_0/VSUBS" "inv_W16_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/VSUBS" "VSUBS"
+merge "inv_W8_0/li_512_546#" "inv_W16_0/a_468_358#" -8.3746 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/li_354_0#" "inv_W16_0/li_n14_0#" -8.0948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/w_354_500#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 271.488 0 0 0 0 90496 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_1666_500#"
+merge "inv_W8_0/li_354_902#" "inv_W16_0/li_n14_902#" -25.0105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/li_128_546#" "Vout" -44.2028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2576 -204 0 0 0 0 0 0 0 0 0 0 0 0
diff --git "a/mag/buffer_2\0431.mag" "b/mag/buffer_2\0431.mag"
new file mode 100755
index 0000000..12f4f9a
--- /dev/null
+++ "b/mag/buffer_2\0431.mag"
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1646326308
+<< nwell >>
+rect 833 250 1008 450
+<< locali >>
+rect 2425 218 2448 246
+use inv_W8 inv_W8_0
+timestamp 1646325197
+transform 1 0 -177 0 1 0
+box 177 0 1025 477
+use inv_W16 inv_W16_0
+timestamp 1646325283
+transform 1 0 854 0 1 0
+box -7 0 1594 477
+<< labels >>
+rlabel locali 2448 232 2448 232 3 Vout
+<< end >>
diff --git a/mag/compaartor_v4.ext b/mag/compaartor_v4.ext
new file mode 100644
index 0000000..7d8c86e
--- /dev/null
+++ b/mag/compaartor_v4.ext
@@ -0,0 +1,204 @@
+timestamp 1647355571
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use preamp_part2 preamp_part2_0 1 0 138 0 1 1376
+use preamp_part1 preamp_part1_0 1 0 720 0 1 260
+use latch_2 latch_2_0 1 0 86 0 1 2636
+use SR_latch SR_latch_0 1 0 394 0 1 4454
+node "Vp" 0 260.94 1116 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68400 1056 0 0 0 0 0 0 0 0 0 0
+node "Vn" 0 255.186 296 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65856 1036 0 0 0 0 0 0 0 0 0 0
+node "m1_1202_1938#" 4 908.66 1202 1938 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116940 4188 0 0 0 0 0 0 0 0 0 0
+node "m1_n58_544#" 4 796.655 -58 544 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 103856 3792 0 0 0 0 0 0 0 0 0 0
+node "li_n270_1084#" 81 171.975 -270 1084 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16600 764 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_80_2410#" 45 114.13 80 2410 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 508 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outn" 16 78.185 1090 4862 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7400 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outp" 47 151.78 514 4852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17816 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "GND" 275 15303.5 -2592 -884 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8321428 28096 1349808 13232 1349808 13232 1349808 13232 1349808 13232 7977560 15376 0 0
+node "CLK" 1734 16650.3 510 2494 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36516 2152 0 0 639860 8112 668136 8828 4400052 39184 3850892 21796 0 0 0 0 0 0
+node "CLKBAR" 106 660.252 760 3478 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92288 1272 0 0 17784 540 17784 540 0 0 0 0 0 0 0 0 0 0
+node "a_1048_4532#" 499 2915.6 1048 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20788 952 0 0 8368 504 409552 11360 0 0 0 0 0 0 0 0 0 0
+node "a_366_4532#" 479 3259.19 366 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18592 828 0 0 15984 888 477728 14188 0 0 0 0 0 0 0 0 0 0
+node "a_652_4812#" 181 21.536 652 4812 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 240 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_176_778#" 2240 186.719 176 778 nw 0 0 0 0 61180 992 0 0 29264 732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49492 928 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_178_2078#" 7877 1405.51 178 2078 nw 0 0 0 0 468504 3540 0 0 16296 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36828 768 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 2644 17443.9 -348 3152 nw 0 0 0 0 206336 1824 0 0 11696 480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8050900 29500 1134468 14080 7917664 20416 1048924 11588 7700232 15292 0 0 0 0
+node "w_782_5052#" 3460 140.755 782 5052 nw 0 0 0 0 44872 884 0 0 17784 612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21640 756 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_86_n24#" 0 0 86 -24 ppd 0 0 0 0 0 0 0 0 0 0 12672 496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16760 636 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n270_1084#" "a_366_4532#" 68.9
+cap "li_n270_1084#" "GND" 28.8316
+cap "CLK" "a_1048_4532#" 387.157
+cap "m1_n58_544#" "CLK" 69.5648
+cap "w_178_2078#" "CLK" 179.767
+cap "CLK" "m1_1202_1938#" 70.9
+cap "CLK" "VDD" 722.286
+cap "CLK" "Vp" 19.2233
+cap "Vn" "CLK" 17.8378
+cap "CLK" "a_366_4532#" 383.156
+cap "CLK" "GND" 922.096
+cap "CLK" "li_n270_1084#" 6.34615
+cap "Outn" "Outp" 6.09554
+cap "a_652_4812#" "a_366_4532#" 2.94872
+cap "a_1048_4532#" "m1_1202_1938#" 775.227
+cap "a_1048_4532#" "VDD" 252.22
+cap "VDD" "w_782_5052#" 88.3518
+cap "a_1048_4532#" "a_366_4532#" 498.297
+cap "m1_n58_544#" "a_366_4532#" 965.934
+cap "VDD" "m1_1202_1938#" 63.0768
+cap "m1_n58_544#" "GND" 63.0768
+cap "li_80_2410#" "GND" 12.6718
+cap "a_366_4532#" "VDD" 242.961
+cap "m1_n58_544#" "li_n270_1084#" 57.08
+cap "VDD" "CLKBAR" 408.264
+cap "a_366_4532#" "GND" 272.129
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/a_n656_268#" -1.84932
+cap "preamp_part1_0/GND" "preamp_part1_0/li_n718_44#" 9.59016
+cap "preamp_part1_0/GND" "preamp_part1_0/a_n434_n260#" 12.0214
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 3.64525
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/GND" 3.17114
+cap "preamp_part1_0/w_n720_482#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 8.7473
+cap "preamp_part1_0/a_n656_268#" "preamp_part1_0/w_n720_482#" 1.51622
+cap "preamp_part1_0/a_n434_n260#" "preamp_part1_0/a_80_n258#" -16.9725
+cap "preamp_part1_0/a_388_n260#" "preamp_part1_0/a_80_n258#" -17.0868
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 3.64525
+cap "preamp_part1_0/GND" "preamp_part1_0/a_n434_n260#" 12.0214
+cap "preamp_part1_0/a_864_270#" "preamp_part1_0/li_954_42#" 5.45455
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/GND" 3.17114
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/w_n720_482#" 8.58247
+cap "preamp_part2_0/GND" "preamp_part1_0/w_n720_482#" 12.1579
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 9.51429
+cap "preamp_part1_0/li_n718_44#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 33.6017
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 10.373
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part1_0/VDD" 34
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_148_644#" -4.01786
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_380_480#" 1.02273
+cap "preamp_part1_0/a_506_940#" "preamp_part2_0/GND" 9.42857
+cap "preamp_part1_0/li_n718_44#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 27.951
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/a_380_480#" 3.43678
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part1_0/a_506_940#" 14.3915
+cap "preamp_part1_0/VDD" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 18.5052
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 116.488
+cap "preamp_part2_0/a_380_480#" "preamp_part1_0/li_954_42#" 2.46575
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/GND" 54.9816
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 0.849201
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 9.51429
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 23.1489
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/VDD" 22.8118
+cap "preamp_part1_0/VDD" "preamp_part2_0/GND" 105.774
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/a_864_270#" 11.261
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/VDD" 17.7837
+cap "latch_2_0/inv_W2_0/Vout" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 3.12657
+cap "latch_2_0/inv_W2_0/VDD" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 11.1654
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "latch_2_0/inv_W2_0/GND" 10.7442
+cap "latch_2_0/inv_W2_0/Vout" "latch_2_0/inv_W2_0/Vin" 1.76966
+cap "preamp_part2_0/VDD" "preamp_part2_0/a_1170_652#" 70.8502
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 1.13687e-13
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_380_480#" 9.71591
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/VDD" 58.8309
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 71.7475
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/VDD" 17.4747
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_148_644#" 28.125
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 4.78585
+cap "preamp_part2_0/VDD" "preamp_part2_0/a_148_644#" 40.4353
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 3.5283
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "latch_2_0/inv_W2_1/GND" 41.9954
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 5.62327
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/VDD" 1.73684
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/Vout" 3.22414
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/Vin" 3.22414
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/GND" 285.214
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 26.2619
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" 68.9902
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/Vin" 251.915
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 3.5283
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "latch_2_0/inv_W2_1/GND" 36.0938
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 18.9908
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 0.849201
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 3.12657
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/GND" 263.571
+cap "latch_2_0/inv_W2_1/GND" "latch_2_0/inv_W2_1/Vin" 34.2451
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 32.8186
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/Vin" 1.42109e-14
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/Vin" 15.3012
+cap "w_178_2078#" "preamp_part2_0/a_1170_652#" -56.62
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 33.0927
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 6.62791
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/Vin" -90.8303
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 16.5
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_0/Vout" 9.83654
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/VDD" 20.7692
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/Vout" 7.58427
+cap "latch_2_0/inv_W2_0/VDD" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 111.593
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/VDD" 15.9256
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/inv_W2_1/VDD" 193.292
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/Vin" 15.3429
+cap "SR_latch_0/GND" "SR_latch_0/a_518_392#" 4.38728
+cap "latch_2_0/inv_W2_1/VDD" "latch_2_0/inv_W2_1/Vin" 0.931034
+cap "SR_latch_0/GND" "latch_2_0/inv_W2_1/Vout" 26.4556
+cap "SR_latch_0/GND" "latch_2_0/inv_W2_1/Vin" 8.2
+cap "SR_latch_0/GND" "SR_latch_0/a_262_508#" 2.96629
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 10.9802
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 4.65183e-14
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/inv_W2_1/Vout" 0.0472214
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/Vin" 30.5365
+cap "latch_2_0/inv_W2_1/Vout" "SR_latch_0/a_518_392#" 0.402439
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 21.4286
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/Vout" 7.75862
+cap "SR_latch_0/a_262_508#" "SR_latch_0/VDD" 96.8724
+cap "SR_latch_0/GND" "SR_latch_0/a_518_392#" 4.38728
+cap "SR_latch_0/a_262_508#" "SR_latch_0/GND" 2.96629
+cap "SR_latch_0/a_262_508#" "SR_latch_0/a_518_392#" -6.09554
+cap "SR_latch_0/a_518_392#" "SR_latch_0/VDD" 58.2776
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "CLKBAR" -242.167 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -49044 -496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/VSUBS" "SR_latch_0/GND" -531.134 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85778 -2136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/GND" "latch_2_0/inv_W2_1/GND"
+merge "latch_2_0/inv_W2_1/GND" "latch_2_0/VSUBS"
+merge "latch_2_0/VSUBS" "latch_2_0/inv_W2_0/GND"
+merge "latch_2_0/inv_W2_0/GND" "preamp_part2_0/VSUBS"
+merge "preamp_part2_0/VSUBS" "preamp_part2_0/GND"
+merge "preamp_part2_0/GND" "preamp_part1_0/VSUBS"
+merge "preamp_part1_0/VSUBS" "preamp_part1_0/GND"
+merge "preamp_part1_0/GND" "a_86_n24#"
+merge "a_86_n24#" "GND"
+merge "preamp_part2_0/a_380_480#" "preamp_part1_0/a_864_270#" -259.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40000 -1138 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_864_270#" "m1_1202_1938#"
+merge "preamp_part1_0/a_n434_n260#" "Vn" -118.824 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -19992 -788 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/a_518_392#" "Outp" -217.253 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -129376 -476 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/VDD" "SR_latch_0/w_0_524#" -2214.62 0 0 0 0 -460960 -5368 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -22780 -3720 58548 -552 131714 -1040 0 0 0 0 0 0 0 0
+merge "SR_latch_0/w_0_524#" "w_782_5052#"
+merge "w_782_5052#" "latch_2_0/m1_718_782#"
+merge "latch_2_0/m1_718_782#" "preamp_part2_0/VDD"
+merge "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "li_80_2410#"
+merge "li_80_2410#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "w_178_2078#"
+merge "w_178_2078#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#"
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "preamp_part1_0/VDD"
+merge "preamp_part1_0/VDD" "VDD"
+merge "VDD" "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "li_n270_1084#"
+merge "li_n270_1084#" "preamp_part1_0/w_n720_482#"
+merge "preamp_part1_0/w_n720_482#" "w_176_778#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/a_n656_268#" -47.3206 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1680 -292 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_n656_268#" "m1_n58_544#"
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "a_652_4812#" 75.6763 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2580 -140 0 0 -11076 -388 41724 -196 0 0 0 0 0 0 0 0 0 0
+merge "a_652_4812#" "latch_2_0/inv_W2_1/Vout"
+merge "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_0/Vin"
+merge "latch_2_0/inv_W2_0/Vin" "preamp_part1_0/li_n718_44#"
+merge "preamp_part1_0/li_n718_44#" "a_366_4532#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -1966.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13884 -268 0 0 0 0 -53924 -836 -1223534 -4500 -375200 -2800 0 0 0 0 0 0
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part1_0/a_506_940#"
+merge "preamp_part1_0/a_506_940#" "preamp_part2_0/a_1170_652#"
+merge "preamp_part2_0/a_1170_652#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part1_0/a_n302_940#"
+merge "preamp_part1_0/a_n302_940#" "preamp_part2_0/a_148_644#"
+merge "preamp_part2_0/a_148_644#" "preamp_part1_0/a_80_n258#"
+merge "preamp_part1_0/a_80_n258#" "CLK"
+merge "preamp_part1_0/a_388_n260#" "Vp" -101.695 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12012 -800 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "latch_2_0/inv_W2_1/Vin" -737.106 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -153428 -60 0 0 -140572 -192 -102904 -204 0 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/inv_W2_1/Vin" "preamp_part1_0/li_954_42#"
+merge "preamp_part1_0/li_954_42#" "a_1048_4532#"
+merge "SR_latch_0/a_262_508#" "Outn" -54.8902 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10584 -220 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/compaartor_v4.mag b/mag/compaartor_v4.mag
new file mode 100644
index 0000000..f94d57b
--- /dev/null
+++ b/mag/compaartor_v4.mag
@@ -0,0 +1,803 @@
+magic
+tech sky130A
+timestamp 1647355571
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+rect -1256 1240 -1131 1413
+rect -856 1240 -731 1413
+rect -407 1139 -294 1270
+rect -1256 690 -1131 863
+rect -856 690 -731 863
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+rect 2114 1728 2226 1848
+rect 262 1278 288 1282
+rect 262 1259 265 1278
+rect 265 1259 283 1278
+rect 283 1259 288 1278
+rect 262 1256 288 1259
+rect 552 1278 578 1282
+rect 552 1259 555 1278
+rect 555 1259 573 1278
+rect 573 1259 578 1278
+rect 552 1256 578 1259
+rect 212 603 240 634
+rect 405 630 433 634
+rect 405 609 409 630
+rect 409 609 429 630
+rect 429 609 433 630
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+rect 1193 644 1305 659
+rect 1714 498 1826 618
+rect 2114 498 2226 618
+rect -407 -182 -294 -51
+rect 406 5 455 49
+<< metal2 >>
+rect 1664 2727 2266 2778
+rect 1664 2607 1714 2727
+rect 1826 2607 2114 2727
+rect 2226 2607 2266 2727
+rect -1285 2319 -1102 2342
+rect -1285 2146 -1256 2319
+rect -1131 2146 -1102 2319
+rect -1285 2113 -1102 2146
+rect -885 2319 -702 2342
+rect -885 2146 -856 2319
+rect -731 2146 -702 2319
+rect -885 2113 -702 2146
+rect 402 1851 516 1859
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+rect -1285 1413 -1102 1438
+rect -1285 1240 -1256 1413
+rect -1131 1240 -1102 1413
+rect -1285 1207 -1102 1240
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+rect -460 1279 -259 1471
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+rect 1306 1293 1340 1424
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+rect 255 1282 292 1288
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+rect 206 634 243 652
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+rect 400 605 405 634
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+rect 613 605 617 634
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+rect -1285 213 -1102 238
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+rect -1131 40 -1102 213
+rect -1285 7 -1102 40
+rect -885 213 -702 238
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+rect -731 40 -702 213
+rect -885 7 -702 40
+rect -460 -51 -259 548
+rect -460 -182 -407 -51
+rect -294 -105 -259 -51
+rect 397 49 464 55
+rect 397 5 406 49
+rect 455 5 464 49
+rect 397 -105 464 5
+rect -294 -150 465 -105
+rect -294 -182 -259 -150
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+rect 1139 -268 1340 644
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+rect 1664 1148 1714 1268
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+rect 2226 1148 2266 1268
+rect 1664 618 2266 1148
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+rect 1826 498 2114 618
+rect 2226 498 2266 618
+rect -460 -412 1341 -268
+rect 1664 -403 2266 498
+rect 1664 -437 2251 -403
+<< via2 >>
+rect 1714 2607 1826 2727
+rect 2114 2607 2226 2727
+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect 1714 1728 1826 1848
+rect 2114 1728 2226 1848
+rect -1256 1240 -1131 1413
+rect -856 1240 -731 1413
+rect 1193 1293 1306 1424
+rect -407 1139 -294 1270
+rect -1256 690 -1131 863
+rect -856 690 -731 863
+rect -407 548 -294 679
+rect 1193 659 1306 775
+rect 1193 644 1305 659
+rect -1256 40 -1131 213
+rect -856 40 -731 213
+rect -407 -182 -294 -51
+rect 1714 1148 1826 1268
+rect 2114 1148 2226 1268
+rect 1714 498 1826 618
+rect 2114 498 2226 618
+<< metal3 >>
+rect 1679 2727 1857 2757
+rect 1679 2607 1714 2727
+rect 1826 2607 1857 2727
+rect 1679 2574 1857 2607
+rect 2078 2727 2257 2757
+rect 2078 2607 2114 2727
+rect 2226 2607 2257 2727
+rect 2078 2574 2257 2607
+rect -1285 2319 -1102 2342
+rect -1285 2146 -1256 2319
+rect -1131 2146 -1102 2319
+rect -1285 2113 -1102 2146
+rect -885 2319 -702 2342
+rect -885 2146 -856 2319
+rect -731 2146 -702 2319
+rect -885 2113 -702 2146
+rect 1678 1848 1857 1878
+rect 1678 1728 1714 1848
+rect 1826 1728 1857 1848
+rect 1678 1695 1857 1728
+rect 2078 1848 2257 1878
+rect 2078 1728 2114 1848
+rect 2226 1728 2257 1848
+rect 2078 1695 2257 1728
+rect -1285 1413 -1102 1438
+rect -1285 1240 -1256 1413
+rect -1131 1240 -1102 1413
+rect -1285 1207 -1102 1240
+rect -885 1413 -702 1438
+rect -885 1240 -856 1413
+rect -731 1240 -702 1413
+rect -885 1207 -702 1240
+rect -462 1270 -255 1474
+rect 1139 1472 1342 1480
+rect -462 1139 -407 1270
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+rect -1285 863 -1102 888
+rect -1285 690 -1256 863
+rect -1131 690 -1102 863
+rect -1285 657 -1102 690
+rect -885 863 -702 888
+rect -885 690 -856 863
+rect -731 690 -702 863
+rect -885 657 -702 690
+rect -462 679 -255 1139
+rect -462 548 -407 679
+rect -294 548 -255 679
+rect -1285 213 -1102 238
+rect -1285 40 -1256 213
+rect -1131 40 -1102 213
+rect -1285 7 -1102 40
+rect -885 213 -702 238
+rect -885 40 -856 213
+rect -731 40 -702 213
+rect -885 7 -702 40
+rect -462 -51 -255 548
+rect -462 -182 -407 -51
+rect -294 -182 -255 -51
+rect -462 -278 -255 -182
+rect 1138 1424 1342 1472
+rect 1138 1293 1193 1424
+rect 1306 1293 1342 1424
+rect 1138 775 1342 1293
+rect 1678 1268 1857 1298
+rect 1678 1148 1714 1268
+rect 1826 1148 1857 1268
+rect 1678 1115 1857 1148
+rect 2078 1268 2257 1298
+rect 2078 1148 2114 1268
+rect 2226 1148 2257 1268
+rect 2078 1115 2257 1148
+rect 1138 644 1193 775
+rect 1306 659 1342 775
+rect 1305 644 1342 659
+rect 1138 -55 1342 644
+rect 1678 618 1857 649
+rect 1678 498 1714 618
+rect 1826 498 1857 618
+rect 1678 465 1857 498
+rect 2078 618 2257 649
+rect 2078 498 2114 618
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+rect 2078 465 2257 498
+rect 1138 -178 1341 -55
+rect 1138 -278 1342 -178
+rect -462 -323 1342 -278
+rect -460 -412 1342 -323
+<< via3 >>
+rect 1714 2607 1826 2727
+rect 2114 2607 2226 2727
+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect 1714 1728 1826 1848
+rect 2114 1728 2226 1848
+rect -1256 1240 -1131 1413
+rect -856 1240 -731 1413
+rect -1256 690 -1131 863
+rect -856 690 -731 863
+rect -1256 40 -1131 213
+rect -856 40 -731 213
+rect 1714 1148 1826 1268
+rect 2114 1148 2226 1268
+rect 1714 498 1826 618
+rect 2114 498 2226 618
+<< metal4 >>
+rect 1662 2727 2269 2778
+rect 1662 2675 1714 2727
+rect 1664 2607 1714 2675
+rect 1826 2607 2114 2727
+rect 2226 2607 2269 2727
+rect 1664 2527 2269 2607
+rect 1663 2458 2269 2527
+rect 1664 2389 2269 2458
+rect -1285 2319 -1102 2342
+rect -1285 2146 -1256 2319
+rect -1131 2146 -1102 2319
+rect -1285 2113 -1102 2146
+rect -885 2319 -702 2342
+rect -885 2146 -856 2319
+rect -731 2146 -702 2319
+rect -885 2113 -702 2146
+rect 1668 1848 2266 2389
+rect 1668 1728 1714 1848
+rect 1826 1728 2114 1848
+rect 2226 1728 2266 1848
+rect -1285 1413 -1102 1438
+rect -1285 1240 -1256 1413
+rect -1131 1240 -1102 1413
+rect -1285 1207 -1102 1240
+rect -885 1413 -702 1438
+rect -885 1240 -856 1413
+rect -731 1240 -702 1413
+rect -885 1207 -702 1240
+rect 1668 1268 2266 1728
+rect 1668 1148 1714 1268
+rect 1826 1148 2114 1268
+rect 2226 1148 2266 1268
+rect -1285 863 -1102 888
+rect -1285 690 -1256 863
+rect -1131 690 -1102 863
+rect -1285 657 -1102 690
+rect -885 863 -702 888
+rect -885 690 -856 863
+rect -731 690 -702 863
+rect -885 657 -702 690
+rect 1668 618 2266 1148
+rect 1668 498 1714 618
+rect 1826 498 2114 618
+rect 2226 498 2266 618
+rect -1285 213 -1102 238
+rect -1285 40 -1256 213
+rect -1131 40 -1102 213
+rect -1285 7 -1102 40
+rect -885 213 -702 238
+rect -885 40 -856 213
+rect -731 40 -702 213
+rect -885 7 -702 40
+rect 1668 -403 2266 498
+rect 1668 -437 2251 -403
+<< via4 >>
+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect -1256 1240 -1131 1413
+rect -856 1240 -731 1413
+rect -1256 690 -1131 863
+rect -856 690 -731 863
+rect -1256 40 -1131 213
+rect -856 40 -731 213
+<< metal5 >>
+rect -1299 2536 -675 2778
+rect -1296 2319 -677 2536
+rect -1296 2146 -1256 2319
+rect -1131 2146 -856 2319
+rect -731 2146 -677 2319
+rect -1296 1413 -677 2146
+rect -1296 1240 -1256 1413
+rect -1131 1240 -856 1413
+rect -731 1240 -677 1413
+rect -1296 863 -677 1240
+rect -1296 690 -1256 863
+rect -1131 690 -856 863
+rect -731 690 -677 863
+rect -1296 213 -677 690
+rect -1296 40 -1256 213
+rect -1131 40 -856 213
+rect -731 40 -677 213
+rect -1296 -442 -677 40
+use SR_latch SR_latch_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646810677
+transform 1 0 197 0 1 2227
+box 0 0 436 474
+use latch_2 latch_2_0 ~/mycomparator/layout/latch
+timestamp 1647355571
+transform 1 0 43 0 1 1318
+box 0 0 801 501
+use preamp_part1 preamp_part1_0 ~/mycomparator/layout/preamp
+timestamp 1646810354
+transform 1 0 360 0 1 130
+box -360 -130 510 508
+use preamp_part2 preamp_part2_0 ~/mycomparator/layout/preamp
+timestamp 1646810398
+transform 1 0 69 0 1 688
+box 58 1 641 544
+<< labels >>
+rlabel metal3 413 -412 413 -412 5 CLK
+rlabel metal1 220 -58 220 -58 5 Vn
+rlabel metal1 640 -58 640 -58 5 Vp
+rlabel locali 257 2431 257 2431 7 Outp
+rlabel locali 595 2448 595 2448 3 Outn
+rlabel metal5 -988 -442 -988 -442 5 GND
+rlabel metal4 2008 -437 2008 -437 5 VDD
+rlabel poly 483 1945 483 1945 1 CLKBAR
+<< end >>
diff --git a/mag/compaartor_v4.spice b/mag/compaartor_v4.spice
new file mode 100644
index 0000000..b11a90e
--- /dev/null
+++ b/mag/compaartor_v4.spice
@@ -0,0 +1,145 @@
+* SPICE3 file created from compaartor_v4.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/Vin inv_W2_1/GND sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_0/Vin inv_W2_1/Vout VSUBS
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vin inv_W2_0/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vout inv_W2_1/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_1/VDD
++ inv_W2_1/VDD m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+C0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# VSUBS 2.01fF
+.ends
+
+.subckt compaartor_v4 GND CLK VDD Vn Vp CLKBAR Outp Outn
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin Outn VDD VDD GND GND
++ SR_latch
+Xpreamp_part1_0 latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin m1_n58_544# CLK CLK
++ VDD Vn CLK m1_1202_1938# VDD Vp GND GND preamp_part1
+Xlatch_2_0 VDD latch_2_0/inv_W2_1/Vin GND VDD CLKBAR latch_2_0/inv_W2_0/Vin latch_2_0/inv_W2_0/Vin
++ GND latch_2
+C0 latch_2_0/inv_W2_1/Vin GND 2.84fF
+C1 latch_2_0/inv_W2_0/Vin GND 4.28fF
+C2 CLK GND 17.54fF
+C3 VDD GND 22.81fF
+C4 m1_n58_544# GND 2.08fF
+.ends
+
diff --git a/mag/comparator_testlay2.spice b/mag/comparator_testlay2.spice
new file mode 100644
index 0000000..fc81b13
--- /dev/null
+++ b/mag/comparator_testlay2.spice
@@ -0,0 +1,165 @@
+* SPICE3 file created from comparator_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# li_202_260# li_n100_828#
++ li_n100_n72# a_84_352# VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 li_n100_828# li_202_260# a_84_352# li_n100_828#
++ li_n100_828# li_202_260# a_84_352# li_n100_n72# li_n100_828# sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ li_n100_828# li_n100_n72# VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_84_352# a_84_352# li_n100_n72# li_n100_n72# li_202_260#
++ VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/li_202_260# li_480_436# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ li_520_0# sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# VSUBS inv_W2_0/a_84_352#
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# li_480_436# li_502_900# li_520_0#
++ inv_W2_0/a_84_352# VSUBS inv_W2
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/li_202_260# li_502_900#
++ li_520_0# li_480_436# VSUBS inv_W2
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# li_502_900#
++ li_502_900# m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+C0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# VSUBS 2.01fF
+.ends
+
+Vdd VDD GND 1.8
+Vn Vn Vp pulse(-100m 100m 1ps 1ps 1ps 5ns 10ns)
+Vcm Vp GND 1.2
+V1 CLK GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+V2 CLKBAR GND pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+.control
+tran 0.01n 50n
+save all
+write comp_testlay2.raw
+.endc
+**** end user architecture code
+**.ends
+.GLOBAL GND
+.GLOBAL VDD
+* Top level circuit comparator_v2
+
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp Dn Dp Outn VDD VDD GND GND SR_latch
+Xpreamp_part1_0 Dn Dp m1_n58_544# CLK CLK VDD Vn CLK m1_1202_1938# VDD Vp GND GND
++ preamp_part1
+Xlatch_2_0 VDD Dp Dn VDD GND CLKBAR GND Dp latch_2
+C0 Dn GND 3.25fF
+C1 Dp GND 4.66fF
+C2 CLK GND 14.89fF
+C3 VDD GND 17.60fF
+C4 m1_n58_544# GND 2.08fF
+.end
+
diff --git a/mag/comparator_v1.mag b/mag/comparator_v1.mag
new file mode 100755
index 0000000..dd73611
--- /dev/null
+++ b/mag/comparator_v1.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+timestamp 1646599058
+<< poly >>
+rect 263 2110 303 2122
+rect 263 2093 273 2110
+rect 290 2107 303 2110
+rect 364 2107 379 2121
+rect 661 2110 701 2122
+rect 661 2108 671 2110
+rect 290 2093 379 2107
+rect 263 2091 379 2093
+rect 562 2093 671 2108
+rect 688 2093 701 2110
+rect 562 2092 701 2093
+rect 263 2080 303 2091
+rect 661 2080 701 2092
+<< polycont >>
+rect 273 2093 290 2110
+rect 671 2093 688 2110
+<< locali >>
+rect 263 2110 298 2118
+rect 263 2093 273 2110
+rect 290 2093 298 2110
+rect 263 2089 298 2093
+rect 661 2110 696 2118
+rect 661 2093 671 2110
+rect 688 2093 696 2110
+rect 661 2089 696 2093
+rect 823 1514 851 1564
+rect 823 1497 828 1514
+rect 846 1497 851 1514
+rect 823 1496 851 1497
+<< viali >>
+rect 153 1539 178 1562
+rect 692 1539 717 1562
+rect 828 1497 846 1514
+<< metal1 >>
+rect 263 2113 303 2122
+rect -104 2087 303 2113
+rect -104 1564 -64 2087
+rect 263 2080 303 2087
+rect 661 2116 701 2122
+rect 661 2089 986 2116
+rect 661 2080 701 2089
+rect 136 1564 187 1572
+rect -104 1562 187 1564
+rect -104 1539 153 1562
+rect 178 1539 187 1562
+rect -104 1536 187 1539
+rect -104 199 -64 1536
+rect 136 1515 187 1536
+rect 684 1562 726 1572
+rect 684 1539 692 1562
+rect 717 1561 726 1562
+rect 946 1561 986 2089
+rect 717 1539 987 1561
+rect 684 1536 987 1539
+rect 684 1530 726 1536
+rect 823 1515 852 1520
+rect 136 1514 852 1515
+rect 136 1497 828 1514
+rect 846 1497 852 1514
+rect 946 1501 987 1536
+rect 136 1496 852 1497
+rect 823 1490 852 1496
+rect -29 965 153 996
+rect 601 969 903 1000
+rect -29 293 -1 965
+rect 130 950 153 965
+rect 130 944 152 950
+rect 875 293 903 969
+rect -29 272 20 293
+rect 858 272 903 293
+rect 947 206 987 1501
+rect -104 171 35 199
+rect 819 178 987 206
+use SR_latch SR_latch_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646507701
+transform 1 0 235 0 1 2046
+box 0 0 436 474
+use latch_2 latch_2_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646503715
+transform 1 0 43 0 1 1318
+box 0 0 801 501
+use preamp_part1 preamp_part1_0 ~/mycomparator_copy1/layout/preamp
+timestamp 1646568821
+transform 1 0 360 0 1 130
+box -360 -130 510 508
+use preamp_part2 preamp_part2_0 ~/mycomparator_copy1/layout/preamp
+timestamp 1646595273
+transform 1 0 69 0 1 688
+box 58 1 641 544
+<< end >>
diff --git a/mag/comparator_v2.ext b/mag/comparator_v2.ext
new file mode 100644
index 0000000..ba1927b
--- /dev/null
+++ b/mag/comparator_v2.ext
@@ -0,0 +1,200 @@
+timestamp 1646831950
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use preamp_part2 preamp_part2_0 1 0 138 0 1 1376
+use preamp_part1 preamp_part1_0 1 0 720 0 1 260
+use latch_2 latch_2_0 1 0 86 0 1 2636
+use SR_latch SR_latch_0 1 0 394 0 1 4454
+node "Vp" 0 260.94 1116 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68400 1056 0 0 0 0 0 0 0 0 0 0
+node "Vn" 0 255.186 296 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65856 1036 0 0 0 0 0 0 0 0 0 0
+node "m1_1202_1938#" 4 908.66 1202 1938 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116940 4188 0 0 0 0 0 0 0 0 0 0
+node "m1_n58_544#" 4 796.655 -58 544 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 103856 3792 0 0 0 0 0 0 0 0 0 0
+node "li_n270_1084#" 81 171.975 -270 1084 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16600 764 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_80_2410#" 45 114.13 80 2410 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 508 0 0 0 0 0 0 0 0 0 0 0 0
+node "GND" 1016 12747.3 -1770 14 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1244580 20556 676368 6624 676368 6624 676368 6624 676368 6624 2332764 11800 0 0
+node "Outp" 16 78.185 1090 4862 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7400 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outn" 47 129.217 514 4852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17816 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "CLK" 1740 14455.7 510 2494 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36516 2152 0 0 639860 8112 668136 8828 1373928 26720 3844396 21764 0 0 0 0 0 0
+node "CLKBAR" 77 283.304 762 3056 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31360 728 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Dn" 499 2917.56 1048 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20788 952 0 0 8368 504 410056 11368 0 0 0 0 0 0 0 0 0 0
+node "Dp" 762 3610.51 154 4842 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31728 1388 0 0 21580 1008 506096 14484 0 0 0 0 0 0 0 0 0 0
+node "w_176_778#" 2240 186.719 176 778 nw 0 0 0 0 61180 992 0 0 29264 732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49492 928 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_178_2078#" 7877 1405.51 178 2078 nw 0 0 0 0 468504 3540 0 0 16296 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36828 768 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 3707 11759.6 -348 3152 nw 0 0 0 0 206336 1824 0 0 11696 480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 960552 20944 479344 6840 573632 9552 393800 4348 2109944 11652 0 0 0 0
+node "w_782_5052#" 3460 140.755 782 5052 nw 0 0 0 0 44872 884 0 0 17784 612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21640 756 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_86_n24#" 0 0 86 -24 ppd 0 0 0 0 0 0 0 0 0 0 12672 496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16760 636 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VDD" "CLK" 555.182
+cap "CLK" "m1_n58_544#" 69.5648
+cap "li_n270_1084#" "m1_n58_544#" 57.08
+cap "VDD" "w_782_5052#" 2.70896
+cap "Dp" "GND" 298.981
+cap "CLK" "Dn" 387.157
+cap "CLK" "li_n270_1084#" 6.34615
+cap "VDD" "Dp" 242.961
+cap "CLK" "Vn" 17.8378
+cap "VDD" "m1_1202_1938#" 63.0768
+cap "GND" "li_80_2410#" 12.6718
+cap "Dp" "m1_n58_544#" 965.934
+cap "Dp" "Dn" 495.406
+cap "CLK" "Dp" 383.156
+cap "CLK" "w_178_2078#" 179.767
+cap "Dp" "li_n270_1084#" 68.9
+cap "Outp" "Outn" 6.09554
+cap "GND" "m1_n58_544#" 63.0768
+cap "Dn" "m1_1202_1938#" 775.227
+cap "CLK" "m1_1202_1938#" 70.9
+cap "Dp" "Outn" 95.676
+cap "CLK" "GND" 553.317
+cap "li_n270_1084#" "GND" 28.8316
+cap "VDD" "Dn" 252.22
+cap "Vp" "CLK" 19.2233
+cap "preamp_part1_0/a_n656_268#" "preamp_part1_0/w_n720_482#" 1.51622
+cap "preamp_part1_0/GND" "preamp_part1_0/a_n434_n260#" 24.0429
+cap "preamp_part1_0/a_n434_n260#" "preamp_part1_0/a_80_n258#" -16.9725
+cap "preamp_part1_0/GND" "preamp_part1_0/li_n718_44#" 9.59016
+cap "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "preamp_part1_0/li_n718_44#" 7.2905
+cap "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "preamp_part1_0/w_n720_482#" 9.12086
+cap "preamp_part1_0/a_80_n258#" "preamp_part1_0/a_388_n260#" -8.54339
+cap "preamp_part1_0/a_n656_268#" "preamp_part1_0/li_n718_44#" -1.84932
+cap "preamp_part1_0/a_80_n258#" "preamp_part1_0/a_388_n260#" -8.54339
+cap "preamp_part1_0/GND" "preamp_part1_0/li_954_42#" 6.34228
+cap "preamp_part1_0/a_864_270#" "preamp_part1_0/li_954_42#" 5.45455
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 108.311
+cap "preamp_part2_0/GND" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" -2.13163e-14
+cap "preamp_part1_0/li_n718_44#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 61.5527
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 0.849201
+cap "preamp_part2_0/a_148_644#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" -4.01786
+cap "preamp_part2_0/a_380_480#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 3.43678
+cap "preamp_part1_0/w_n720_482#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 34
+cap "preamp_part1_0/w_n720_482#" "preamp_part2_0/GND" 81.9789
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 10.373
+cap "preamp_part2_0/GND" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 54.9816
+cap "preamp_part1_0/w_n720_482#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 18.5052
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 19.0286
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 23.1489
+cap "preamp_part2_0/a_380_480#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 2.55682
+cap "preamp_part1_0/w_n720_482#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 28.9599
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part1_0/a_506_940#" 7.19573
+cap "preamp_part1_0/VDD" "preamp_part2_0/a_380_480#" -2.13163e-14
+cap "preamp_part1_0/VDD" "preamp_part2_0/a_792_2#" 2.43443
+cap "preamp_part1_0/a_506_940#" "preamp_part2_0/GND" 9.42857
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/a_792_2#" 10.2158
+cap "preamp_part1_0/a_506_940#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 7.19573
+cap "preamp_part1_0/li_954_42#" "preamp_part2_0/a_380_480#" 11.261
+cap "preamp_part1_0/VDD" "preamp_part2_0/GND" 35.9526
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_148_644#" 28.125
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 26.2619
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 0.849201
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 8.33173
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "latch_2_0/li_520_0#" 3.5283
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_0/a_84_352#" 137.05
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" 11.5596
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 5.62327
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 61.2497
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "latch_2_0/li_520_0#" 181.609
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 162.487
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "preamp_part2_0/a_148_644#" 116.625
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 68.9902
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" -39.6
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" 8.15698
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "latch_2_0/li_520_0#" 41.9954
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" 17.7406
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_380_480#" 8.18182
+cap "latch_2_0/li_520_0#" "latch_2_0/inv_W2_0/a_84_352#" 147.857
+cap "latch_2_0/inv_W2_1/a_84_352#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 3.22414
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "preamp_part2_0/a_1170_652#" 70.8489
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_1/li_202_260#" 173.503
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 130.849
+cap "latch_2_0/m1_718_782#" "latch_2_0/inv_W2_1/li_202_260#" 7.43119
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 3.5283
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/VDD" 97.0475
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/li_202_260#" 3.22414
+cap "latch_2_0/inv_W2_1/a_84_352#" "preamp_part2_0/VDD" 1.42109e-14
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 4.78585
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 2.5288
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 33.9877
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" "latch_2_0/inv_W2_1/li_202_260#" 24.0698
+cap "preamp_part2_0/VDD" "preamp_part2_0/a_1170_652#" 0.00129717
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" -25.3
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 36.0938
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 65.2145
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "latch_2_0/inv_W2_1/li_202_260#" 148.807
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" 38.4692
+cap "SR_latch_0/a_518_392#" "SR_latch_0/GND" 4.38728
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 18.6923
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_0/a_84_352#" 13.6517
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "latch_2_0/inv_W2_0/a_84_352#" 2.84217e-14
+cap "latch_2_0/inv_W2_0/a_84_352#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" 0.0628415
+cap "SR_latch_0/GND" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" 3.73757
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 150.151
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 7.10543e-15
+cap "SR_latch_0/a_262_508#" "SR_latch_0/GND" 2.96629
+cap "latch_2_0/inv_W2_1/li_202_260#" "latch_2_0/inv_W2_1/a_84_352#" 13.9655
+cap "latch_2_0/inv_W2_1/a_84_352#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 0.0628415
+cap "latch_2_0/inv_W2_1/a_84_352#" "SR_latch_0/GND" 8.2
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" 19.2857
+cap "SR_latch_0/a_518_392#" "SR_latch_0/GND" 4.38728
+cap "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 0.0628415
+cap "SR_latch_0/a_262_508#" "SR_latch_0/a_518_392#" -3.04777
+cap "SR_latch_0/a_262_508#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 17.6972
+cap "SR_latch_0/a_518_392#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 12.7602
+cap "SR_latch_0/a_262_508#" "SR_latch_0/VDD" 80.5225
+cap "SR_latch_0/VDD" "SR_latch_0/a_518_392#" 58.2776
+cap "SR_latch_0/VDD" "SR_latch_0/a_262_508#" 16.3499
+cap "SR_latch_0/VDD" "SR_latch_0/a_518_392#" 5.68434e-14
+cap "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 0.0628415
+cap "SR_latch_0/a_518_392#" "SR_latch_0/a_262_508#" -3.04777
+cap "SR_latch_0/GND" "SR_latch_0/a_262_508#" 2.96629
+cap "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "SR_latch_0/a_518_392#" 0.425926
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "CLKBAR" -89.0118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1212 -456 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part2_0/a_380_480#" "preamp_part1_0/a_864_270#" -155.387 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24596 -680 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_864_270#" "m1_1202_1938#"
+merge "preamp_part1_0/a_n434_n260#" "Vn" -125.189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -29784 -788 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/a_262_508#" "Outp" -32.5792 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13536 -220 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/VSUBS" "SR_latch_0/GND" -554.213 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -319052 -1196 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/GND" "latch_2_0/VSUBS"
+merge "latch_2_0/VSUBS" "latch_2_0/li_520_0#"
+merge "latch_2_0/li_520_0#" "preamp_part2_0/VSUBS"
+merge "preamp_part2_0/VSUBS" "preamp_part2_0/GND"
+merge "preamp_part2_0/GND" "preamp_part1_0/GND"
+merge "preamp_part1_0/GND" "GND"
+merge "GND" "preamp_part1_0/VSUBS"
+merge "preamp_part1_0/VSUBS" "a_86_n24#"
+merge "SR_latch_0/VDD" "SR_latch_0/w_0_524#" -1732.88 0 0 0 0 -272672 -5000 0 0 16896 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -341530 -2216 -338092 -552 -56458 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/w_0_524#" "w_782_5052#"
+merge "w_782_5052#" "preamp_part2_0/VDD"
+merge "preamp_part2_0/VDD" "latch_2_0/m1_718_782#"
+merge "latch_2_0/m1_718_782#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#"
+merge "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "li_80_2410#"
+merge "li_80_2410#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "w_178_2078#"
+merge "w_178_2078#" "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "VDD"
+merge "VDD" "preamp_part1_0/VDD"
+merge "preamp_part1_0/VDD" "li_n270_1084#"
+merge "li_n270_1084#" "preamp_part1_0/w_n720_482#"
+merge "preamp_part1_0/w_n720_482#" "w_176_778#"
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "latch_2_0/inv_W2_1/li_202_260#" 131.577 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -19992 -92 0 0 -388 -388 672132 -196 0 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/inv_W2_1/li_202_260#" "latch_2_0/inv_W2_0/a_84_352#"
+merge "latch_2_0/inv_W2_0/a_84_352#" "preamp_part1_0/li_n718_44#"
+merge "preamp_part1_0/li_n718_44#" "Dp"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/a_n656_268#" -48.8884 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32068 -292 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_n656_268#" "m1_n58_544#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -2053.77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -39260 -268 0 0 0 0 -48888 -836 -583454 -772 -750564 -4434 0 0 0 0 0 0
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part1_0/a_506_940#"
+merge "preamp_part1_0/a_506_940#" "preamp_part1_0/a_n302_940#"
+merge "preamp_part1_0/a_n302_940#" "preamp_part2_0/a_1170_652#"
+merge "preamp_part2_0/a_1170_652#" "preamp_part2_0/a_148_644#"
+merge "preamp_part2_0/a_148_644#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part1_0/a_80_n258#"
+merge "preamp_part1_0/a_80_n258#" "CLK"
+merge "SR_latch_0/a_518_392#" "Outn" -236.141 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -149616 -476 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "latch_2_0/inv_W2_1/a_84_352#" -332.284 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 -51824 -192 1032 -204 0 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/inv_W2_1/a_84_352#" "preamp_part1_0/li_954_42#"
+merge "preamp_part1_0/li_954_42#" "Dn"
+merge "preamp_part1_0/a_388_n260#" "Vp" -121.834 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18972 -800 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/comparator_v2.mag b/mag/comparator_v2.mag
new file mode 100644
index 0000000..86bce9b
--- /dev/null
+++ b/mag/comparator_v2.mag
@@ -0,0 +1,633 @@
+magic
+tech sky130A
+timestamp 1646832626
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+rect 1159 775 1335 800
+rect 1159 644 1193 775
+rect 1306 644 1335 775
+rect 1159 619 1335 644
+rect 1678 618 1857 649
+rect 1678 498 1714 618
+rect 1826 498 1857 618
+rect 1678 465 1857 498
+rect -104 171 35 199
+rect 819 178 987 206
+rect -885 7 -702 40
+rect -441 -51 -265 -26
+rect -441 -182 -407 -51
+rect -294 -182 -265 -51
+rect 148 -58 295 54
+rect 558 -58 708 56
+rect -441 -208 -265 -182
+<< via1 >>
+rect -856 1990 -731 2163
+rect 433 1811 485 1851
+rect -856 1240 -731 1413
+rect -407 1139 -294 1270
+rect -856 690 -731 863
+rect -407 548 -294 679
+rect -856 40 -731 213
+rect 1714 1728 1826 1848
+rect 262 1278 288 1282
+rect 262 1259 265 1278
+rect 265 1259 283 1278
+rect 283 1259 288 1278
+rect 262 1256 288 1259
+rect 552 1278 578 1282
+rect 552 1259 555 1278
+rect 555 1259 573 1278
+rect 573 1259 578 1278
+rect 552 1256 578 1259
+rect 212 603 240 634
+rect 405 630 433 634
+rect 405 609 409 630
+rect 409 609 429 630
+rect 429 609 433 630
+rect 405 605 433 609
+rect 617 605 645 634
+rect 1193 1293 1306 1424
+rect 1714 1148 1826 1268
+rect 1193 659 1306 775
+rect 1193 644 1305 659
+rect 1714 498 1826 618
+rect -407 -182 -294 -51
+rect 406 5 455 49
+<< metal2 >>
+rect -885 2163 -702 2188
+rect -885 1990 -856 2163
+rect -731 1990 -702 2163
+rect -885 1957 -702 1990
+rect 402 1851 516 1859
+rect 402 1811 433 1851
+rect 485 1843 516 1851
+rect 1678 1848 1857 1878
+rect 1678 1843 1714 1848
+rect 485 1811 1714 1843
+rect 402 1810 1714 1811
+rect 402 1801 516 1810
+rect 1678 1728 1714 1810
+rect 1826 1728 1857 1848
+rect 1678 1695 1857 1728
+rect -885 1413 -702 1438
+rect -885 1240 -856 1413
+rect -731 1240 -702 1413
+rect 1159 1433 1335 1449
+rect 1159 1424 1337 1433
+rect -885 1207 -702 1240
+rect -441 1279 -265 1295
+rect 1159 1293 1193 1424
+rect 1306 1409 1337 1424
+rect 1306 1314 1335 1409
+rect 1306 1293 1334 1314
+rect 1159 1290 1334 1293
+rect 578 1289 1334 1290
+rect 255 1282 292 1288
+rect 255 1279 262 1282
+rect -441 1270 262 1279
+rect -441 1139 -407 1270
+rect -294 1256 262 1270
+rect 288 1256 292 1282
+rect -294 1255 292 1256
+rect -294 1139 -265 1255
+rect 255 1247 292 1255
+rect 545 1282 1334 1289
+rect 545 1256 552 1282
+rect 578 1268 1334 1282
+rect 1678 1268 1857 1298
+rect 578 1263 1325 1268
+rect 578 1256 582 1263
+rect 545 1247 582 1256
+rect -441 1114 -265 1139
+rect -397 1046 -308 1114
+rect 1194 1048 1309 1263
+rect 1678 1148 1714 1268
+rect 1826 1148 1857 1268
+rect 1678 1115 1857 1148
+rect -397 1013 185 1046
+rect 660 1016 1309 1048
+rect -397 1012 -274 1013
+rect 660 1012 1267 1016
+rect -885 863 -702 888
+rect -885 690 -856 863
+rect -731 690 -702 863
+rect 1159 775 1335 800
+rect -885 657 -702 690
+rect -441 679 -265 704
+rect 1159 685 1193 775
+rect -441 548 -407 679
+rect -294 676 -265 679
+rect 400 677 436 678
+rect 206 676 436 677
+rect -294 652 436 676
+rect -294 548 -265 652
+rect 206 634 243 652
+rect 206 603 212 634
+rect 240 603 243 634
+rect 206 600 243 603
+rect 400 634 436 652
+rect 617 660 1193 685
+rect 617 638 647 660
+rect 400 605 405 634
+rect 433 605 436 634
+rect 400 600 436 605
+rect 613 634 647 638
+rect 613 605 617 634
+rect 645 605 647 634
+rect 1159 644 1193 660
+rect 1306 659 1335 775
+rect 1159 619 1305 644
+rect 613 600 647 605
+rect 1678 618 1857 649
+rect -441 523 -265 548
+rect 1678 498 1714 618
+rect 1826 498 1857 618
+rect 1678 465 1857 498
+rect -885 213 -702 238
+rect -885 40 -856 213
+rect -731 40 -702 213
+rect -885 7 -702 40
+rect 397 49 464 55
+rect 397 5 406 49
+rect 455 5 464 49
+rect -441 -51 -265 -26
+rect -441 -182 -407 -51
+rect -294 -105 -265 -51
+rect 397 -105 464 5
+rect -294 -150 465 -105
+rect -294 -182 -265 -150
+rect -441 -208 -265 -182
+<< via2 >>
+rect -856 1990 -731 2163
+rect 1714 1728 1826 1848
+rect -856 1240 -731 1413
+rect 1193 1293 1306 1424
+rect -407 1139 -294 1270
+rect 1714 1148 1826 1268
+rect -856 690 -731 863
+rect -407 548 -294 679
+rect 1193 659 1306 775
+rect 1193 644 1305 659
+rect 1714 498 1826 618
+rect -856 40 -731 213
+rect -407 -182 -294 -51
+<< metal3 >>
+rect -885 2163 -702 2188
+rect -885 1990 -856 2163
+rect -731 1990 -702 2163
+rect -885 1957 -702 1990
+rect 1678 1848 1857 1878
+rect 1678 1728 1714 1848
+rect 1826 1728 1857 1848
+rect 1678 1695 1857 1728
+rect -885 1413 -702 1438
+rect -885 1240 -856 1413
+rect -731 1240 -702 1413
+rect -885 1207 -702 1240
+rect -462 1270 -255 1474
+rect -462 1139 -407 1270
+rect -294 1139 -255 1270
+rect -885 863 -702 888
+rect -885 690 -856 863
+rect -731 690 -702 863
+rect -885 657 -702 690
+rect -462 679 -255 1139
+rect -462 548 -407 679
+rect -294 548 -255 679
+rect -885 213 -702 238
+rect -885 40 -856 213
+rect -731 40 -702 213
+rect -885 7 -702 40
+rect -462 -51 -255 548
+rect -462 -182 -407 -51
+rect -294 -182 -255 -51
+rect -462 -278 -255 -182
+rect 1138 1424 1342 1472
+rect 1138 1293 1193 1424
+rect 1306 1293 1342 1424
+rect 1138 775 1342 1293
+rect 1678 1268 1857 1298
+rect 1678 1148 1714 1268
+rect 1826 1148 1857 1268
+rect 1678 1115 1857 1148
+rect 1138 644 1193 775
+rect 1306 659 1342 775
+rect 1305 644 1342 659
+rect 1138 -55 1342 644
+rect 1678 618 1857 649
+rect 1678 498 1714 618
+rect 1826 498 1857 618
+rect 1678 465 1857 498
+rect 1138 -178 1341 -55
+rect 1138 -278 1342 -178
+rect -462 -323 1342 -278
+rect -460 -412 1342 -323
+<< via3 >>
+rect -856 1990 -731 2163
+rect 1714 1728 1826 1848
+rect -856 1240 -731 1413
+rect -856 690 -731 863
+rect -856 40 -731 213
+rect 1714 1148 1826 1268
+rect 1714 498 1826 618
+<< metal4 >>
+rect -885 2163 -702 2188
+rect -885 1990 -856 2163
+rect -731 1990 -702 2163
+rect -885 1957 -702 1990
+rect 1670 1848 1864 2283
+rect 1670 1728 1714 1848
+rect 1826 1728 1864 1848
+rect -885 1413 -702 1438
+rect -885 1240 -856 1413
+rect -731 1240 -702 1413
+rect -885 1207 -702 1240
+rect 1670 1268 1864 1728
+rect 1670 1148 1714 1268
+rect 1826 1148 1864 1268
+rect -885 863 -702 888
+rect -885 690 -856 863
+rect -731 690 -702 863
+rect -885 657 -702 690
+rect 1670 618 1864 1148
+rect 1670 498 1714 618
+rect 1826 498 1864 618
+rect -885 213 -702 238
+rect -885 40 -856 213
+rect -731 40 -702 213
+rect -885 7 -702 40
+rect 1670 -436 1864 498
+<< via4 >>
+rect -856 1990 -731 2163
+rect -856 1240 -731 1413
+rect -856 690 -731 863
+rect -856 40 -731 213
+<< metal5 >>
+rect -897 2163 -666 2283
+rect -897 1990 -856 2163
+rect -731 1990 -666 2163
+rect -897 1702 -666 1990
+rect -889 1413 -679 1702
+rect -889 1240 -856 1413
+rect -731 1240 -679 1413
+rect -889 863 -679 1240
+rect -889 690 -856 863
+rect -731 690 -679 863
+rect -889 213 -679 690
+rect -889 40 -856 213
+rect -731 40 -679 213
+rect -889 -436 -679 40
+use SR_latch SR_latch_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646810677
+transform 1 0 197 0 1 2227
+box 0 0 436 474
+use latch_2 latch_2_0 ~/mycomparator/layout/latch
+timestamp 1646831438
+transform 1 0 43 0 1 1318
+box 0 0 801 501
+use preamp_part1 preamp_part1_0 ~/mycomparator/layout/preamp
+timestamp 1646810354
+transform 1 0 360 0 1 130
+box -360 -130 510 508
+use preamp_part2 preamp_part2_0 ~/mycomparator/layout/preamp
+timestamp 1646810398
+transform 1 0 69 0 1 688
+box 58 1 641 544
+<< labels >>
+rlabel metal5 -785 -436 -785 -436 5 GND
+rlabel metal3 394 -412 394 -412 5 CLK
+rlabel metal4 1760 -436 1760 -436 5 VDD
+rlabel metal1 215 -58 215 -58 5 Vn
+rlabel metal1 633 -58 633 -58 5 Vp
+rlabel poly 430 1528 430 1528 5 CLKBAR
+rlabel metal1 966 2018 966 2018 1 Dn
+rlabel metal1 -84 2018 -84 2018 1 Dp
+rlabel locali 257 2432 257 2432 7 Outp
+rlabel locali 595 2449 595 2449 3 Outn
+<< end >>
diff --git a/mag/comparator_v2.spice b/mag/comparator_v2.spice
new file mode 100644
index 0000000..e95388a
--- /dev/null
+++ b/mag/comparator_v2.spice
@@ -0,0 +1,148 @@
+* SPICE3 file created from comparator_v2.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# li_202_260# li_n100_828#
++ li_n100_n72# a_84_352# VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 li_n100_828# li_202_260# a_84_352# li_n100_828#
++ li_n100_828# li_202_260# a_84_352# li_n100_n72# li_n100_828# sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ li_n100_828# li_n100_n72# VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_84_352# a_84_352# li_n100_n72# li_n100_n72# li_202_260#
++ VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/li_202_260# li_480_436# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ li_520_0# sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# VSUBS inv_W2_0/a_84_352#
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# li_480_436# li_502_900# li_520_0#
++ inv_W2_0/a_84_352# VSUBS inv_W2
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/li_202_260# li_502_900#
++ li_520_0# li_480_436# VSUBS inv_W2
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# li_502_900#
++ li_502_900# m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+C0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# VSUBS 2.01fF
+.ends
+
+
+* Top level circuit comparator_v2
+
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp Dn Dp Outn VDD VDD GND GND SR_latch
+Xpreamp_part1_0 Dn Dp m1_n58_544# CLK CLK VDD Vn CLK m1_1202_1938# VDD Vp GND GND
++ preamp_part1
+Xlatch_2_0 VDD Dp Dn VDD GND CLKBAR GND Dp latch_2
+C0 Dn GND 3.25fF
+C1 Dp GND 4.66fF
+C2 CLK GND 14.89fF
+C3 VDD GND 17.60fF
+C4 m1_n58_544# GND 2.08fF
+.end
+
diff --git a/mag/comparator_v3.ext b/mag/comparator_v3.ext
new file mode 100644
index 0000000..218b16b
--- /dev/null
+++ b/mag/comparator_v3.ext
@@ -0,0 +1,274 @@
+timestamp 1647011741
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use preamp_part1 preamp_part1_0 1 0 720 0 1 260
+use preamp_part2 preamp_part2_0 1 0 138 0 1 1376
+use latch_2 latch_2_0 1 0 86 0 1 2636
+use SR_latch SR_latch_0 1 0 394 0 1 4454
+use inv_W1 inv_W1_0 -1 0 2630 0 1 4030
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0 1 0 2400 0 1 6112
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1 1 0 1689 0 1 6111
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2 1 0 915 0 1 6111
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3 1 0 -17 0 1 6109
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0 1 0 2400 0 1 6834
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1 1 0 1758 0 1 6836
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2 1 0 928 0 1 6830
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3 1 0 -6 0 1 6840
+node "Vp" 0 260.94 1116 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68400 1056 0 0 0 0 0 0 0 0 0 0
+node "Vn" 0 255.186 296 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65856 1036 0 0 0 0 0 0 0 0 0 0
+node "m1_1202_1938#" 4 908.66 1202 1938 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116940 4188 0 0 0 0 0 0 0 0 0 0
+node "m1_n58_544#" 4 796.655 -58 544 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 103856 3792 0 0 0 0 0 0 0 0 0 0
+node "li_n270_1084#" 81 171.975 -270 1084 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16600 764 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_80_2410#" 45 114.13 80 2410 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 508 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outn" 16 78.185 1090 4862 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7400 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outp" 47 129.217 514 4852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17816 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_1802_6060#" 37 439.053 1802 6060 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 272 87384 1588 0 0 0 0 0 0 0 0 0 0
+node "li_1028_6060#" 37 461.178 1028 6060 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 272 87360 1696 0 0 0 0 0 0 0 0 0 0
+node "li_96_6058#" 38 535.336 96 6058 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 272 104312 2004 0 0 0 0 0 0 0 0 0 0
+node "li_2252_6784#" 35 413.156 2252 6784 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3672 276 80256 1480 0 0 0 0 0 0 0 0 0 0
+node "li_1610_6784#" 37 509.904 1610 6784 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3468 272 110600 1860 0 0 0 0 0 0 0 0 0 0
+node "li_780_6778#" 36 559.518 780 6778 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3744 280 123736 2052 0 0 0 0 0 0 0 0 0 0
+node "GND" 446 23061.1 -2594 5526 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8510640 35608 2348956 24244 1867920 17304 1867920 17304 1867920 17304 10398476 19284 0 0
+node "a_760_3478#" 164 1690.48 760 3478 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92288 1272 0 0 34164 1052 34164 1052 278424 4388 0 0 0 0 0 0 0 0
+node "CLK" 1945 17800.5 510 2494 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44772 2516 0 0 655348 8640 683472 9356 4415388 39712 4510628 25052 0 0 0 0 0 0
+node "a_1048_4532#" 499 2892.55 1048 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20788 952 0 0 8368 504 410056 11368 0 0 0 0 0 0 0 0 0 0
+node "a_154_4842#" 762 3622.56 154 4842 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31728 1388 0 0 21580 1008 506096 14484 0 0 0 0 0 0 0 0 0 0
+node "w_176_778#" 2240 186.719 176 778 nw 0 0 0 0 61180 992 0 0 29264 732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49492 928 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_178_2078#" 7877 1405.51 178 2078 nw 0 0 0 0 468504 3540 0 0 16296 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36828 768 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 2799 23307 -348 3152 nw 0 0 0 0 206336 1824 0 0 11696 480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8599340 36872 1777240 20620 8283216 24104 1513572 15444 10022708 19108 0 0 0 0
+node "w_782_5052#" 3460 140.755 782 5052 nw 0 0 0 0 44872 884 0 0 17784 612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21640 756 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_86_n24#" 0 0 86 -24 ppd 0 0 0 0 0 0 0 0 0 0 12672 496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16760 636 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VDD" "m1_1202_1938#" 63.0768
+cap "a_154_4842#" "li_n270_1084#" 68.9
+cap "a_154_4842#" "CLK" 383.156
+cap "VDD" "a_1048_4532#" 252.22
+cap "li_1802_6060#" "li_1028_6060#" 108
+cap "w_178_2078#" "CLK" 179.767
+cap "a_154_4842#" "Outp" 95.676
+cap "GND" "li_n270_1084#" 28.8316
+cap "GND" "CLK" 942.403
+cap "GND" "li_780_6778#" 155.25
+cap "li_n270_1084#" "CLK" 6.34615
+cap "li_96_6058#" "li_1028_6060#" 116.591
+cap "GND" "li_80_2410#" 12.6718
+cap "Vp" "CLK" 19.2233
+cap "a_154_4842#" "VDD" 242.961
+cap "m1_1202_1938#" "a_1048_4532#" 775.227
+cap "GND" "a_760_3478#" 159.885
+cap "VDD" "li_2252_6784#" 141.75
+cap "GND" "li_96_6058#" 106.2
+cap "a_760_3478#" "CLK" 267.484
+cap "a_154_4842#" "m1_n58_544#" 965.934
+cap "GND" "VDD" 11
+cap "w_782_5052#" "VDD" 88.3518
+cap "VDD" "CLK" 1004.74
+cap "Outn" "Outp" 6.09554
+cap "GND" "m1_n58_544#" 63.0768
+cap "li_n270_1084#" "m1_n58_544#" 57.08
+cap "m1_n58_544#" "CLK" 69.5648
+cap "a_154_4842#" "a_1048_4532#" 495.406
+cap "VDD" "a_760_3478#" 534.931
+cap "li_1610_6784#" "li_2252_6784#" 165
+cap "m1_1202_1938#" "CLK" 70.9
+cap "Vn" "CLK" 17.8378
+cap "GND" "a_1048_4532#" 73.1798
+cap "a_1048_4532#" "CLK" 387.157
+cap "li_780_6778#" "li_1610_6784#" 116.667
+cap "a_760_3478#" "a_1048_4532#" 177.556
+cap "GND" "a_154_4842#" 304.711
+cap "preamp_part1_0/GND" "preamp_part1_0/a_n434_n260#" 12.0214
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/a_n656_268#" 0.0513699
+cap "preamp_part1_0/GND" "preamp_part1_0/li_n718_44#" 9.59016
+cap "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "preamp_part1_0/li_n718_44#" 3.64525
+cap "preamp_part1_0/a_n656_268#" "preamp_part1_0/w_n720_482#" 1.51622
+cap "preamp_part1_0/a_388_n260#" "preamp_part1_0/a_80_n258#" -17.0868
+cap "preamp_part1_0/w_n720_482#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 9.25261
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 3.64525
+cap "preamp_part1_0/a_864_270#" "preamp_part1_0/li_954_42#" 1.17647
+cap "preamp_part1_0/GND" "preamp_part1_0/a_n434_n260#" 12.0214
+cap "preamp_part1_0/a_n434_n260#" "preamp_part1_0/a_80_n258#" -16.9725
+cap "preamp_part1_0/GND" "preamp_part1_0/li_954_42#" 0.882353
+cap "preamp_part1_0/GND" "preamp_part1_0/li_954_42#" 6.34228
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/a_864_270#" 13.4494
+cap "preamp_part1_0/a_n656_268#" "preamp_part1_0/w_n720_482#" 8.58247
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part1_0/a_n656_268#" 9.51429
+cap "preamp_part2_0/GND" "preamp_part1_0/w_n720_482#" 10.9421
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/a_n656_268#" 30.1842
+cap "preamp_part1_0/a_n656_268#" "preamp_part1_0/a_n302_940#" 116.488
+cap "preamp_part1_0/a_506_940#" "preamp_part1_0/a_n302_940#" 14.3915
+cap "preamp_part2_0/GND" "preamp_part1_0/a_n302_940#" 54.9816
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/a_864_270#" 1.17647
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "preamp_part1_0/a_n302_940#" 23.1489
+cap "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "preamp_part1_0/VDD" 9.25261
+cap "preamp_part1_0/a_864_270#" "preamp_part1_0/a_n656_268#" 8.69318
+cap "preamp_part1_0/VDD" "preamp_part1_0/a_n656_268#" 22.8118
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 10.373
+cap "preamp_part1_0/a_864_270#" "preamp_part1_0/a_n302_940#" 3.43678
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/a_n656_268#" 27.951
+cap "preamp_part2_0/GND" "preamp_part1_0/VDD" 106.989
+cap "preamp_part2_0/GND" "preamp_part1_0/a_506_940#" 9.42857
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part1_0/a_n656_268#" 9.51429
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 0.849201
+cap "preamp_part1_0/a_n656_268#" "preamp_part2_0/a_148_644#" 6.20942
+cap "preamp_part1_0/VDD" "preamp_part1_0/a_n302_940#" 34
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/a_864_270#" -9.08143
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "latch_2_0/inv_W2_0/li_n100_n72#" 8.05814
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 5.5618
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 32.1006
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 28.1683
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 7.88618
+cap "latch_2_0/li_520_0#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 3.5283
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part2_0/VDD" 26.2619
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/VDD" 71.7475
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 18.9908
+cap "latch_2_0/li_520_0#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 3.5283
+cap "latch_2_0/li_520_0#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 36.0938
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/a_84_352#" 14.375
+cap "latch_2_0/li_520_0#" "preamp_part2_0/VDD" 285.214
+cap "latch_2_0/inv_W2_0/a_84_352#" "preamp_part2_0/VDD" 3.22414
+cap "latch_2_0/li_520_0#" "latch_2_0/inv_W2_0/a_84_352#" 241.071
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 4.99342
+cap "preamp_part2_0/a_380_480#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 2.04545
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 57.4356
+cap "preamp_part2_0/a_148_644#" "preamp_part2_0/VDD" 40.4353
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "preamp_part2_0/VDD" 0.849201
+cap "preamp_part2_0/a_1170_652#" "preamp_part2_0/VDD" 70.8502
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/a_84_352#" 7.88618
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_148_644#" 28.125
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 4.78585
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 5.62327
+cap "latch_2_0/inv_W2_1/a_84_352#" "preamp_part2_0/VDD" 3.22414
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "preamp_part2_0/VDD" 1.13687e-13
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part2_0/VDD" 68.9902
+cap "latch_2_0/li_520_0#" "latch_2_0/inv_W2_1/a_84_352#" 28.3272
+cap "latch_2_0/inv_W2_0/a_84_352#" "latch_2_0/inv_W2_1/a_84_352#" 248.561
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "latch_2_0/li_520_0#" 41.9954
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/li_202_260#" 8.02326
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/a_84_352#" 1.42109e-14
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 19.186
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 38.652
+cap "w_178_2078#" "preamp_part2_0/a_1170_652#" -53.96
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/a_84_352#" 28.1842
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_1/li_202_260#" -71.796
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "latch_2_0/inv_W2_1/li_202_260#" 55.5927
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_0/a_84_352#" 10.3846
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "latch_2_0/inv_W2_0/a_84_352#" 3.79213
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 90.6575
+cap "GND" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 9.0973
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 5.07692
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/inv_W2_0/a_84_352#" 7.79713
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 10.9802
+cap "SR_latch_0/a_262_508#" "SR_latch_0/GND" 2.96629
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_0/a_84_352#" 7.41074e-15
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 15.877
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "SR_latch_0/GND" 165.397
+cap "latch_2_0/inv_W2_1/a_84_352#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 25.7769
+cap "SR_latch_0/a_518_392#" "SR_latch_0/GND" 4.38728
+cap "latch_2_0/inv_W2_1/a_84_352#" "SR_latch_0/GND" 8.2
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/inv_W2_0/a_84_352#" 0.0472214
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 193.292
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_0/a_84_352#" 9.41469e-14
+cap "latch_2_0/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "GND" 124.865
+cap "inv_W1_0/Vout" "inv_W1_0/VDD" 42.4228
+cap "inv_W1_0/Vin" "inv_W1_0/GND" 258.193
+cap "inv_W1_0/Vin" "inv_W1_0/VDD" 424.46
+cap "latch_2_0/inv_W2_1/li_202_260#" "latch_2_0/inv_W2_1/a_84_352#" 3.87931
+cap "inv_W1_0/Vin" "inv_W1_0/Vout" 171.326
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "inv_W1_0/GND" 8.91892
+cap "inv_W1_0/Vout" "inv_W1_0/GND" -4.2547
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/a_84_352#" 10.7143
+cap "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/a_n45_n45#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/w_n183_n183#" 248.986
+cap "SR_latch_0/a_262_508#" "SR_latch_0/VDD" 96.8724
+cap "SR_latch_0/a_518_392#" "SR_latch_0/a_262_508#" -6.09554
+cap "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" 0.125683
+cap "SR_latch_0/a_518_392#" "SR_latch_0/GND" 4.38728
+cap "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "SR_latch_0/a_262_508#" 17.6972
+cap "SR_latch_0/a_518_392#" "SR_latch_0/VDD" 58.2776
+cap "SR_latch_0/GND" "SR_latch_0/a_262_508#" 2.96629
+cap "SR_latch_0/a_518_392#" "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 12.7602
+cap "inv_W1_0/VDD" "inv_W1_0/Vin" 3.95212
+cap "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0/w_n183_n183#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1/a_n45_n45#" -386.942
+cap "inv_W1_0/VDD" "inv_W1_0/Vout" 2.75387
+cap "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3/a_n45_n45#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/w_n183_n183#" 277.417
+cap "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0/w_n183_n183#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0/a_n45_n45#" 262.437
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0/w_n183_n183#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1/a_n45_n45#" -2435.06 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -168179 -9432 -331210 -2352 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1/a_n45_n45#" "li_2252_6784#"
+merge "li_2252_6784#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0/a_n45_n45#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2/w_n183_n183#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3/a_n45_n45#" "li_780_6778#"
+merge "li_780_6778#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2/a_n45_n45#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1/w_n183_n183#" "li_1610_6784#"
+merge "li_1610_6784#" "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3/w_n183_n183#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0/w_n183_n183#" "SR_latch_0/VDD"
+merge "SR_latch_0/VDD" "SR_latch_0/w_0_524#"
+merge "SR_latch_0/w_0_524#" "w_782_5052#"
+merge "w_782_5052#" "inv_W1_0/VDD"
+merge "inv_W1_0/VDD" "latch_2_0/m1_718_782#"
+merge "latch_2_0/m1_718_782#" "preamp_part2_0/VDD"
+merge "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "li_80_2410#"
+merge "li_80_2410#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "w_178_2078#"
+merge "w_178_2078#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#"
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "preamp_part1_0/VDD"
+merge "preamp_part1_0/VDD" "VDD"
+merge "VDD" "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "li_n270_1084#"
+merge "li_n270_1084#" "preamp_part1_0/w_n720_482#"
+merge "preamp_part1_0/w_n720_482#" "w_176_778#"
+merge "w_176_778#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0/a_n45_n45#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2/w_n183_n183#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1/a_n45_n45#" "li_1028_6060#"
+merge "li_1028_6060#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2/a_n45_n45#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1/w_n183_n183#" "li_1802_6060#"
+merge "li_1802_6060#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/w_n183_n183#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/w_n183_n183#" "li_96_6058#"
+merge "li_96_6058#" "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/a_n45_n45#"
+merge "sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3/a_n45_n45#" "inv_W1_0/VSUBS"
+merge "inv_W1_0/VSUBS" "inv_W1_0/GND"
+merge "inv_W1_0/GND" "SR_latch_0/VSUBS"
+merge "SR_latch_0/VSUBS" "SR_latch_0/GND"
+merge "SR_latch_0/GND" "latch_2_0/li_520_0#"
+merge "latch_2_0/li_520_0#" "latch_2_0/VSUBS"
+merge "latch_2_0/VSUBS" "latch_2_0/inv_W2_0/li_n100_n72#"
+merge "latch_2_0/inv_W2_0/li_n100_n72#" "preamp_part2_0/VSUBS"
+merge "preamp_part2_0/VSUBS" "preamp_part2_0/GND"
+merge "preamp_part2_0/GND" "preamp_part1_0/VSUBS"
+merge "preamp_part1_0/VSUBS" "preamp_part1_0/GND"
+merge "preamp_part1_0/GND" "a_86_n24#"
+merge "a_86_n24#" "GND"
+merge "preamp_part2_0/a_380_480#" "preamp_part1_0/a_864_270#" -194.626 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8640 -922 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_864_270#" "m1_1202_1938#"
+merge "preamp_part1_0/a_n434_n260#" "Vn" -117.896 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -18564 -788 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/a_518_392#" "Outp" -172.916 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -81264 -476 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/Vout" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" -371.231 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -35484 -496 0 0 -78108 -244 0 0 248060 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "a_760_3478#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/a_n656_268#" -44.7184 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1268 -292 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_n656_268#" "m1_n58_544#"
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "latch_2_0/inv_W2_1/li_202_260#" 87.79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 600 -92 0 0 -16472 -388 51704 -196 0 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/inv_W2_1/li_202_260#" "latch_2_0/inv_W2_0/a_84_352#"
+merge "latch_2_0/inv_W2_0/a_84_352#" "preamp_part1_0/li_n718_44#"
+merge "preamp_part1_0/li_n718_44#" "a_154_4842#"
+merge "inv_W1_0/Vin" "preamp_part2_0/a_1170_652#" -2388.24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -197352 -448 0 0 436424 -520 78372 -836 -851584 -3368 -430224 -2800 0 0 0 0 0 0
+merge "preamp_part2_0/a_1170_652#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part1_0/a_506_940#"
+merge "preamp_part1_0/a_506_940#" "preamp_part2_0/a_148_644#"
+merge "preamp_part2_0/a_148_644#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part1_0/a_n302_940#"
+merge "preamp_part1_0/a_n302_940#" "preamp_part1_0/a_80_n258#"
+merge "preamp_part1_0/a_80_n258#" "CLK"
+merge "preamp_part1_0/a_388_n260#" "Vp" -103.77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8820 -800 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "latch_2_0/inv_W2_1/a_84_352#" -799.693 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -202064 -60 0 0 -183096 -192 64024 -204 0 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/inv_W2_1/a_84_352#" "preamp_part1_0/li_954_42#"
+merge "preamp_part1_0/li_954_42#" "a_1048_4532#"
+merge "SR_latch_0/a_262_508#" "Outn" -57.31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13200 -220 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/comparator_v3.mag b/mag/comparator_v3.mag
new file mode 100644
index 0000000..d95ca03
--- /dev/null
+++ b/mag/comparator_v3.mag
@@ -0,0 +1,1046 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647011741
+<< nwell >>
+rect 782 5052 940 5336
+rect -348 3152 148 3568
+rect 178 2078 1624 2402
+rect 176 778 406 1044
+<< psubdiff >>
+rect 86 128 158 152
+rect 86 -24 158 0
+<< nsubdiff >>
+rect 810 5270 888 5294
+rect 810 5066 888 5090
+rect -42 3424 26 3448
+rect -42 3276 26 3300
+rect 332 2308 416 2332
+rect 332 2138 416 2162
+rect 194 1008 312 1032
+rect 194 784 312 808
+<< psubdiffcont >>
+rect 86 0 158 128
+<< nsubdiffcont >>
+rect 810 5090 888 5270
+rect -42 3300 26 3424
+rect 332 2162 416 2308
+rect 194 808 312 1008
+<< poly >>
+rect 154 4922 262 4948
+rect 154 4870 178 4922
+rect 228 4916 262 4922
+rect 228 4872 682 4916
+rect 228 4870 262 4872
+rect 154 4842 262 4870
+rect 652 4812 682 4872
+rect 1368 4580 1442 4600
+rect 1368 4578 1384 4580
+rect 1048 4532 1384 4578
+rect 1426 4532 1442 4580
+rect 1368 4518 1442 4532
+rect 2540 4450 2636 4468
+rect 2540 4406 2576 4450
+rect 2618 4406 2636 4450
+rect 2540 4382 2636 4406
+rect 760 3868 984 3890
+rect 760 3798 828 3868
+rect 928 3798 984 3868
+rect 760 3478 984 3798
+rect 510 2556 584 2576
+rect 510 2518 530 2556
+rect 566 2518 584 2556
+rect 510 2494 584 2518
+rect 1090 2556 1164 2576
+rect 1090 2518 1110 2556
+rect 1146 2518 1164 2556
+rect 1090 2494 1164 2518
+rect 530 2348 560 2494
+rect 1112 2350 1142 2494
+rect 818 1490 848 1606
+rect 816 1322 848 1490
+rect 814 1276 850 1322
+rect 802 1260 870 1276
+rect 802 1218 818 1260
+rect 858 1218 870 1260
+rect 802 1200 870 1218
+<< polycont >>
+rect 178 4870 228 4922
+rect 1384 4532 1426 4580
+rect 2576 4406 2618 4450
+rect 828 3798 928 3868
+rect 530 2518 566 2556
+rect 1110 2518 1146 2556
+rect 818 1218 858 1260
+<< locali >>
+rect 3694 6986 4172 7104
+rect 3694 6924 3812 6986
+rect 3692 6790 3812 6924
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+rect 2624 4400 2680 4456
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+rect -2262 2480 -2204 2826
+rect -2570 2414 -2204 2480
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+rect -1770 2480 -1712 2826
+rect -1462 2480 -1404 2826
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+rect 2278 2944 2684 3704
+rect 3356 3696 3714 3756
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+rect 3652 3456 3714 3696
+rect 3356 3390 3714 3456
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+rect 4156 3456 4228 3696
+rect 4452 3456 4514 3696
+rect 4156 3390 4514 3456
+rect -924 2278 -814 2540
+rect -588 2278 -510 2540
+rect -2570 1726 -2204 1776
+rect -2570 1380 -2512 1726
+rect -2262 1380 -2204 1726
+rect -2570 1314 -2204 1380
+rect -1770 1726 -1404 1776
+rect -1770 1380 -1712 1726
+rect -1462 1380 -1404 1726
+rect -1770 1314 -1404 1380
+rect -924 1358 -510 2278
+rect -924 1096 -814 1358
+rect -588 1096 -510 1358
+rect -2570 426 -2204 476
+rect -2570 80 -2512 426
+rect -2262 80 -2204 426
+rect -2570 14 -2204 80
+rect -1770 426 -1404 476
+rect -1770 80 -1712 426
+rect -1462 80 -1404 426
+rect -1770 14 -1404 80
+rect -924 -102 -510 1096
+rect -924 -364 -814 -102
+rect -588 -364 -510 -102
+rect -924 -556 -510 -364
+rect 2276 2848 2684 2944
+rect 2276 2586 2386 2848
+rect 2612 2586 2684 2848
+rect 2276 1550 2684 2586
+rect 3356 2536 3714 2596
+rect 3356 2296 3428 2536
+rect 3652 2296 3714 2536
+rect 3356 2230 3714 2296
+rect 4156 2536 4514 2596
+rect 4156 2296 4228 2536
+rect 4452 2296 4514 2536
+rect 4156 2230 4514 2296
+rect 2276 1288 2386 1550
+rect 2612 1318 2684 1550
+rect 2610 1288 2684 1318
+rect 2276 -110 2684 1288
+rect 3356 1236 3714 1298
+rect 3356 996 3428 1236
+rect 3652 996 3714 1236
+rect 3356 930 3714 996
+rect 4156 1236 4514 1298
+rect 4156 996 4228 1236
+rect 4452 996 4514 1236
+rect 4156 930 4514 996
+rect 2276 -356 2682 -110
+rect 2276 -556 2684 -356
+rect -924 -646 2684 -556
+rect -920 -824 2684 -646
+<< via3 >>
+rect -2174 6686 -1874 6952
+rect 3812 6736 4076 6986
+rect -2174 5960 -1874 6226
+rect 3812 5980 4076 6230
+rect 3428 5214 3652 5454
+rect 4228 5214 4452 5454
+rect -2512 4292 -2262 4638
+rect -1712 4292 -1462 4638
+rect -2512 2480 -2262 2826
+rect -1712 2480 -1462 2826
+rect 3428 3456 3652 3696
+rect 4228 3456 4452 3696
+rect -2512 1380 -2262 1726
+rect -1712 1380 -1462 1726
+rect -2512 80 -2262 426
+rect -1712 80 -1462 426
+rect 3428 2296 3652 2536
+rect 4228 2296 4452 2536
+rect 3428 996 3652 1236
+rect 4228 996 4452 1236
+<< metal4 >>
+rect 3322 7412 4536 7550
+rect 3322 7130 4538 7412
+rect -2282 6952 -1768 7064
+rect -2282 6686 -2174 6952
+rect -1874 6686 -1768 6952
+rect -2282 6560 -1768 6686
+rect 3324 6986 4538 7130
+rect 3324 6736 3812 6986
+rect 4076 6736 4538 6986
+rect -2282 6226 -1768 6338
+rect -2282 5960 -2174 6226
+rect -1874 5960 -1768 6226
+rect -2282 5834 -1768 5960
+rect 3324 6230 4538 6736
+rect 3324 5980 3812 6230
+rect 4076 5980 4538 6230
+rect 3324 5454 4538 5980
+rect 3324 5214 3428 5454
+rect 3652 5214 4228 5454
+rect 4452 5214 4538 5454
+rect 3324 4778 4538 5214
+rect -2570 4638 -2204 4684
+rect -2570 4292 -2512 4638
+rect -2262 4292 -2204 4638
+rect -2570 4226 -2204 4292
+rect -1770 4638 -1404 4684
+rect -1770 4292 -1712 4638
+rect -1462 4292 -1404 4638
+rect -1770 4226 -1404 4292
+rect 3336 3696 4532 4778
+rect 3336 3456 3428 3696
+rect 3652 3456 4228 3696
+rect 4452 3456 4532 3696
+rect -2570 2826 -2204 2876
+rect -2570 2480 -2512 2826
+rect -2262 2480 -2204 2826
+rect -2570 2414 -2204 2480
+rect -1770 2826 -1404 2876
+rect -1770 2480 -1712 2826
+rect -1462 2480 -1404 2826
+rect -1770 2414 -1404 2480
+rect 3336 2536 4532 3456
+rect 3336 2296 3428 2536
+rect 3652 2296 4228 2536
+rect 4452 2296 4532 2536
+rect -2570 1726 -2204 1776
+rect -2570 1380 -2512 1726
+rect -2262 1380 -2204 1726
+rect -2570 1314 -2204 1380
+rect -1770 1726 -1404 1776
+rect -1770 1380 -1712 1726
+rect -1462 1380 -1404 1726
+rect -1770 1314 -1404 1380
+rect 3336 1236 4532 2296
+rect 3336 996 3428 1236
+rect 3652 996 4228 1236
+rect 4452 996 4532 1236
+rect -2570 426 -2204 476
+rect -2570 80 -2512 426
+rect -2262 80 -2204 426
+rect -2570 14 -2204 80
+rect -1770 426 -1404 476
+rect -1770 80 -1712 426
+rect -1462 80 -1404 426
+rect -1770 14 -1404 80
+rect 3336 -788 4532 996
+<< via4 >>
+rect -2174 6686 -1874 6952
+rect -2174 5960 -1874 6226
+rect -2512 4292 -2262 4638
+rect -1712 4292 -1462 4638
+rect -2512 2480 -2262 2826
+rect -1712 2480 -1462 2826
+rect -2512 1380 -2262 1726
+rect -1712 1380 -1462 1726
+rect -2512 80 -2262 426
+rect -1712 80 -1462 426
+<< metal5 >>
+rect -2612 7202 -1346 7550
+rect -2612 7030 -1344 7202
+rect -2592 6952 -1344 7030
+rect -2592 6686 -2174 6952
+rect -1874 6686 -1344 6952
+rect -2592 6226 -1344 6686
+rect -2592 5960 -2174 6226
+rect -1874 5960 -1344 6226
+rect -2592 5374 -1344 5960
+rect -2592 4638 -1354 5374
+rect -2592 4292 -2512 4638
+rect -2262 4292 -1712 4638
+rect -1462 4292 -1354 4638
+rect -2592 2826 -1354 4292
+rect -2592 2480 -2512 2826
+rect -2262 2480 -1712 2826
+rect -1462 2480 -1354 2826
+rect -2592 1726 -1354 2480
+rect -2592 1380 -2512 1726
+rect -2262 1380 -1712 1726
+rect -1462 1380 -1354 1726
+rect -2592 426 -1354 1380
+rect -2592 80 -2512 426
+rect -2262 80 -1712 426
+rect -1462 80 -1354 426
+rect -2592 -824 -1354 80
+use SR_latch SR_latch_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646810677
+transform 1 0 394 0 1 4454
+box 0 0 872 948
+use inv_W1 inv_W1_0 ~/mycomparator_copy1/layout/myinv_layout2
+timestamp 1645263751
+transform -1 0 2630 0 1 4030
+box -100 -72 388 878
+use latch_2 latch_2_0 ~/mycomparator/layout/latch
+timestamp 1646831438
+transform 1 0 86 0 1 2636
+box 0 0 1602 1002
+use preamp_part1 preamp_part1_0 ~/mycomparator/layout/preamp
+timestamp 1646810354
+transform 1 0 720 0 1 260
+box -720 -260 1020 1016
+use preamp_part2 preamp_part2_0 ~/mycomparator/layout/preamp
+timestamp 1646810398
+transform 1 0 138 0 1 1376
+box 116 2 1282 1088
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0
+timestamp 1646995406
+transform 1 0 2400 0 1 6834
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1
+timestamp 1646995406
+transform 1 0 1758 0 1 6836
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2
+timestamp 1646995406
+transform 1 0 928 0 1 6830
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 sky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3
+timestamp 1646995406
+transform 1 0 -6 0 1 6840
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0
+timestamp 1646995406
+transform 1 0 2400 0 1 6112
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1
+timestamp 1646995406
+transform 1 0 1689 0 1 6111
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2
+timestamp 1646995406
+transform 1 0 915 0 1 6111
+box -183 -183 183 183
+use sky130_fd_pr__diode_pw2nd_05v5_KLAK3C sky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3
+timestamp 1646995406
+transform 1 0 -17 0 1 6109
+box -183 -183 183 183
+<< labels >>
+rlabel metal1 440 -116 440 -116 5 Vn
+rlabel metal1 1280 -116 1280 -116 5 Vp
+rlabel locali 514 4862 514 4862 7 Outp
+rlabel locali 1190 4896 1190 4896 3 Outn
+rlabel metal3 990 -824 990 -824 5 CLK
+rlabel metal5 -2092 -824 -2092 -824 5 GND
+rlabel metal4 3792 -788 3792 -788 5 VDD
+<< end >>
diff --git a/mag/comparator_v3.spice b/mag/comparator_v3.spice
new file mode 100644
index 0000000..38ac898
--- /dev/null
+++ b/mag/comparator_v3.spice
@@ -0,0 +1,186 @@
+* SPICE3 file created from comparator_v3.ext - technology: sky130A
+
+.subckt sky130_fd_pr__diode_pw2nd_05v5_KLAK3C a_n45_n45# w_n183_n183#
+D0 w_n183_n183# a_n45_n45# sky130_fd_pr__diode_pw2nd_05v5 pj=1.8e+06u area=2.025e+11p
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__diode_pw2nd_05v5_FT7GK8 a_n45_n45# w_n183_n183#
+D0 w_n183_n183# a_n45_n45# sky130_fd_pr__diode_pw2nd_05v5 pj=1.8e+06u area=2.025e+11p
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# li_202_260# li_n100_828#
++ li_n100_n72# a_84_352# VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 li_n100_828# li_202_260# a_84_352# li_n100_828#
++ li_n100_828# li_202_260# a_84_352# li_n100_n72# li_n100_828# sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ li_n100_828# li_n100_n72# VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_84_352# a_84_352# li_n100_n72# li_n100_n72# li_202_260#
++ VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/li_202_260# li_480_436# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ li_520_0# sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# VSUBS inv_W2_0/a_84_352#
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# li_480_436# li_502_900# li_520_0#
++ inv_W2_0/a_84_352# VSUBS inv_W2
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/li_202_260# li_502_900#
++ li_520_0# li_480_436# VSUBS inv_W2
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# li_502_900#
++ li_502_900# m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+C0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# VSUBS 2.01fF
+.ends
+
+
+* Top level circuit comparator_v3
+
+Xsky130_fd_pr__diode_pw2nd_05v5_KLAK3C_2 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_KLAK3C
+Xsky130_fd_pr__diode_pw2nd_05v5_KLAK3C_3 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_KLAK3C
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD VDD m1_n58_544# VDD
++ preamp_part2
+Xsky130_fd_pr__diode_pw2nd_05v5_FT7GK8_0 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_FT7GK8
+Xsky130_fd_pr__diode_pw2nd_05v5_FT7GK8_1 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_FT7GK8
+Xsky130_fd_pr__diode_pw2nd_05v5_FT7GK8_2 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_FT7GK8
+Xsky130_fd_pr__diode_pw2nd_05v5_FT7GK8_3 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_FT7GK8
+XSR_latch_0 Outp a_1048_4532# a_154_4842# Outn VDD VDD VDD VDD SR_latch
+Xpreamp_part1_0 a_1048_4532# a_154_4842# m1_n58_544# CLK CLK VDD Vn CLK m1_1202_1938#
++ VDD Vp VDD VDD preamp_part1
+Xinv_W1_0 inv_W1_0/Vout CLK VDD VDD inv_W1
+Xlatch_2_0 VDD a_154_4842# a_1048_4532# VDD VDD inv_W1_0/Vout VDD a_154_4842# latch_2
+Xsky130_fd_pr__diode_pw2nd_05v5_KLAK3C_0 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_KLAK3C
+Xsky130_fd_pr__diode_pw2nd_05v5_KLAK3C_1 VDD VDD sky130_fd_pr__diode_pw2nd_05v5_KLAK3C
+C0 a_1048_4532# VDD 3.13fF
+C1 a_154_4842# VDD 4.97fF
+C2 inv_W1_0/Vout VDD 2.30fF
+C3 CLK VDD 20.76fF
+C4 m1_n58_544# VDD 2.18fF
+.end
+
diff --git a/mag/comparator_v5.ext b/mag/comparator_v5.ext
new file mode 100644
index 0000000..bee67ab
--- /dev/null
+++ b/mag/comparator_v5.ext
@@ -0,0 +1,205 @@
+timestamp 1647352381
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use preamp_part2 preamp_part2_0 1 0 138 0 1 1376
+use preamp_part1 preamp_part1_0 1 0 720 0 1 260
+use latch_2 latch_2_0 1 0 86 0 1 2636
+use SR_latch SR_latch_0 1 0 394 0 1 4454
+node "Vp" 0 260.94 1116 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68400 1056 0 0 0 0 0 0 0 0 0 0
+node "Vn" 0 255.186 296 -116 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65856 1036 0 0 0 0 0 0 0 0 0 0
+node "m1_1202_1938#" 4 908.66 1202 1938 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 116940 4188 0 0 0 0 0 0 0 0 0 0
+node "m1_n58_544#" 4 796.655 -58 544 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 103856 3792 0 0 0 0 0 0 0 0 0 0
+node "li_n270_1084#" 81 171.975 -270 1084 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16600 764 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_80_2410#" 45 114.13 80 2410 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 508 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outn" 16 78.185 1090 4862 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7400 348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Outp" 47 151.78 514 4852 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17816 660 0 0 0 0 0 0 0 0 0 0 0 0
+node "GND" 275 15303.5 -2592 -884 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8321428 28096 1349808 13232 1349808 13232 1349808 13232 1349808 13232 7977560 15376 0 0
+node "CLK" 1734 16650.3 510 2494 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36516 2152 0 0 639860 8112 668136 8828 4400052 39184 3850892 21796 0 0 0 0 0 0
+node "CLKBAR" 106 660.252 760 3478 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92288 1272 0 0 17784 540 17784 540 0 0 0 0 0 0 0 0 0 0
+node "a_1048_4532#" 499 2915.6 1048 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20788 952 0 0 8368 504 409552 11360 0 0 0 0 0 0 0 0 0 0
+node "a_366_4532#" 479 3259.19 366 4532 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18592 828 0 0 15984 888 477728 14188 0 0 0 0 0 0 0 0 0 0
+node "a_652_4812#" 181 21.536 652 4812 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 240 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_176_778#" 2240 186.719 176 778 nw 0 0 0 0 61180 992 0 0 29264 732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49492 928 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_178_2078#" 7877 1405.51 178 2078 nw 0 0 0 0 468504 3540 0 0 16296 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36828 768 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 2644 17443.9 -348 3152 nw 0 0 0 0 206336 1824 0 0 11696 480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8050900 29500 1134468 14080 7917664 20416 1048924 11588 7700232 15292 0 0 0 0
+node "w_782_5052#" 3460 140.755 782 5052 nw 0 0 0 0 44872 884 0 0 17784 612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21640 756 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_86_n24#" 0 0 86 -24 ppd 0 0 0 0 0 0 0 0 0 0 12672 496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16760 636 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_782_5052#" "VDD" 88.3518
+cap "GND" "m1_n58_544#" 63.0768
+cap "w_178_2078#" "CLK" 179.767
+cap "a_366_4532#" "CLK" 383.156
+cap "li_n270_1084#" "m1_n58_544#" 57.08
+cap "a_1048_4532#" "a_366_4532#" 498.297
+cap "a_366_4532#" "a_652_4812#" 2.94872
+cap "li_80_2410#" "GND" 12.6718
+cap "a_1048_4532#" "CLK" 387.157
+cap "m1_1202_1938#" "VDD" 63.0768
+cap "a_366_4532#" "m1_n58_544#" 965.934
+cap "CLK" "m1_n58_544#" 69.5648
+cap "VDD" "CLKBAR" 408.264
+cap "Vn" "CLK" 17.8378
+cap "a_366_4532#" "VDD" 242.961
+cap "li_n270_1084#" "GND" 28.8316
+cap "VDD" "CLK" 722.286
+cap "a_1048_4532#" "VDD" 252.22
+cap "Vp" "CLK" 19.2233
+cap "Outn" "Outp" 6.09554
+cap "a_366_4532#" "GND" 272.129
+cap "CLK" "GND" 922.096
+cap "li_n270_1084#" "a_366_4532#" 68.9
+cap "m1_1202_1938#" "CLK" 70.9
+cap "m1_1202_1938#" "a_1048_4532#" 775.227
+cap "li_n270_1084#" "CLK" 6.34615
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 3.64525
+cap "preamp_part1_0/GND" "preamp_part1_0/a_n434_n260#" 12.0214
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/a_n656_268#" -1.84932
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/GND" 9.59016
+cap "preamp_part1_0/w_n720_482#" "preamp_part1_0/a_n656_268#" 1.51622
+cap "preamp_part1_0/li_n718_44#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 3.64525
+cap "preamp_part1_0/a_388_n260#" "preamp_part1_0/a_80_n258#" -17.0868
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/GND" 3.17114
+cap "preamp_part1_0/w_n720_482#" "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" 8.7473
+cap "preamp_part1_0/a_n434_n260#" "preamp_part1_0/GND" 12.0214
+cap "preamp_part1_0/a_n434_n260#" "preamp_part1_0/a_80_n258#" -16.9725
+cap "preamp_part1_0/GND" "preamp_part1_0/li_954_42#" 3.17114
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/a_864_270#" 5.45455
+cap "preamp_part1_0/w_n720_482#" "preamp_part2_0/GND" 12.1579
+cap "preamp_part1_0/w_n720_482#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 8.58247
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/li_n718_44#" 33.6017
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 9.51429
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 116.488
+cap "preamp_part1_0/sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "preamp_part1_0/VDD" 18.5052
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 23.1489
+cap "preamp_part1_0/VDD" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 22.8118
+cap "preamp_part1_0/a_506_940#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 14.3915
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 10.373
+cap "preamp_part2_0/GND" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 54.9816
+cap "preamp_part2_0/GND" "preamp_part1_0/VDD" 105.774
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 9.51429
+cap "preamp_part2_0/a_380_480#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 1.02273
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 0.849201
+cap "preamp_part1_0/VDD" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 34
+cap "preamp_part1_0/a_506_940#" "preamp_part2_0/GND" 9.42857
+cap "preamp_part1_0/li_n718_44#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 27.951
+cap "preamp_part2_0/a_148_644#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" -4.01786
+cap "preamp_part2_0/a_380_480#" "preamp_part1_0/li_954_42#" 2.46575
+cap "preamp_part2_0/a_380_480#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 3.43678
+cap "preamp_part1_0/li_954_42#" "preamp_part1_0/a_864_270#" 11.261
+cap "latch_2_0/inv_W2_0/GND" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 10.7442
+cap "latch_2_0/inv_W2_0/Vout" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 3.12657
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/Vout" 1.76966
+cap "latch_2_0/inv_W2_0/VDD" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 11.1654
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/VDD" 17.7837
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/Vout" 3.22414
+cap "latch_2_0/inv_W2_1/GND" "latch_2_0/inv_W2_1/Vout" 263.571
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 3.5283
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 1.13687e-13
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_380_480#" 9.71591
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 4.78585
+cap "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 5.62327
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 3.5283
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/VDD" 58.8309
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 26.2619
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/Vout" 251.915
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/VDD" 1.73684
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" 3.12657
+cap "preamp_part2_0/VDD" "preamp_part2_0/a_148_644#" 40.4353
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/VDD" 285.214
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" 41.9954
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" 68.9902
+cap "latch_2_0/inv_W2_1/GND" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 36.0938
+cap "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 71.7475
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part2_0/a_148_644#" 28.125
+cap "latch_2_0/inv_W2_1/GND" "latch_2_0/inv_W2_1/Vin" 34.2451
+cap "preamp_part2_0/a_1170_652#" "preamp_part2_0/VDD" 70.8502
+cap "latch_2_0/inv_W2_1/Vin" "preamp_part2_0/VDD" 3.22414
+cap "preamp_part2_0/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "preamp_part2_0/VDD" 0.849201
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/VDD" 17.4747
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/Vout" 18.9908
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/Vout" 6.62791
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 33.0927
+cap "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "latch_2_0/inv_W2_1/Vin" 15.3012
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 32.8186
+cap "w_178_2078#" "preamp_part2_0/a_1170_652#" -56.62
+cap "preamp_part2_0/VDD" "latch_2_0/inv_W2_1/sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" 16.5
+cap "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_1/Vin" -90.8303
+cap "latch_2_0/inv_W2_1/Vin" "preamp_part2_0/VDD" 1.42109e-14
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_0/VDD" 111.593
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_0/Vout" 9.83654
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/VDD" 20.7692
+cap "latch_2_0/inv_W2_0/Vin" "latch_2_0/inv_W2_0/Vout" 7.58427
+cap "latch_2_0/inv_W2_1/Vin" "SR_latch_0/GND" 8.2
+cap "SR_latch_0/a_262_508#" "SR_latch_0/GND" 2.96629
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/Vin" 30.5365
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 10.9802
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/Vout" 15.3429
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "latch_2_0/inv_W2_1/Vout" 0.0472214
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/VDD" 0.931034
+cap "SR_latch_0/GND" "latch_2_0/inv_W2_1/Vout" 26.4556
+cap "latch_2_0/inv_W2_1/VDD" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 193.292
+cap "SR_latch_0/a_518_392#" "SR_latch_0/GND" 4.38728
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/Vout" 3.94129e-14
+cap "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "latch_2_0/inv_W2_1/VDD" 15.9256
+cap "SR_latch_0/a_518_392#" "latch_2_0/inv_W2_1/Vout" 0.402439
+cap "latch_2_0/inv_W2_1/VDD" "latch_2_0/inv_W2_1/Vout" -1.95399e-14
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/Vout" 7.75862
+cap "latch_2_0/inv_W2_1/Vin" "latch_2_0/inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" 21.4286
+cap "SR_latch_0/VDD" "SR_latch_0/a_262_508#" 96.8724
+cap "SR_latch_0/GND" "SR_latch_0/a_518_392#" 4.38728
+cap "SR_latch_0/a_262_508#" "SR_latch_0/GND" 2.96629
+cap "SR_latch_0/a_262_508#" "SR_latch_0/a_518_392#" -6.09554
+cap "SR_latch_0/VDD" "SR_latch_0/a_518_392#" 58.2776
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "CLKBAR" -242.167 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -49044 -496 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/VSUBS" "SR_latch_0/GND" -531.134 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -85778 -2136 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/GND" "latch_2_0/inv_W2_1/GND"
+merge "latch_2_0/inv_W2_1/GND" "latch_2_0/VSUBS"
+merge "latch_2_0/VSUBS" "latch_2_0/inv_W2_0/GND"
+merge "latch_2_0/inv_W2_0/GND" "preamp_part2_0/VSUBS"
+merge "preamp_part2_0/VSUBS" "preamp_part2_0/GND"
+merge "preamp_part2_0/GND" "preamp_part1_0/VSUBS"
+merge "preamp_part1_0/VSUBS" "preamp_part1_0/GND"
+merge "preamp_part1_0/GND" "a_86_n24#"
+merge "a_86_n24#" "GND"
+merge "preamp_part2_0/a_380_480#" "preamp_part1_0/a_864_270#" -259.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40000 -1138 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_864_270#" "m1_1202_1938#"
+merge "preamp_part1_0/a_n434_n260#" "Vn" -118.824 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -19992 -788 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/a_518_392#" "Outp" -217.253 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -129376 -476 0 0 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/VDD" "SR_latch_0/w_0_524#" -2214.62 0 0 0 0 -460960 -5368 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -22780 -3720 58548 -552 131714 -1040 0 0 0 0 0 0 0 0
+merge "SR_latch_0/w_0_524#" "w_782_5052#"
+merge "w_782_5052#" "latch_2_0/m1_718_782#"
+merge "latch_2_0/m1_718_782#" "preamp_part2_0/VDD"
+merge "preamp_part2_0/VDD" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "li_80_2410#"
+merge "li_80_2410#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "w_178_2078#"
+merge "w_178_2078#" "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#"
+merge "latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "preamp_part1_0/VDD"
+merge "preamp_part1_0/VDD" "VDD"
+merge "VDD" "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#"
+merge "preamp_part1_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "li_n270_1084#"
+merge "li_n270_1084#" "preamp_part1_0/w_n720_482#"
+merge "preamp_part1_0/w_n720_482#" "w_176_778#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "preamp_part1_0/a_n656_268#" -47.3206 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1680 -292 0 0 0 0 0 0 0 0 0 0
+merge "preamp_part1_0/a_n656_268#" "m1_n58_544#"
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "a_652_4812#" 75.6763 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2580 -140 0 0 -11076 -388 41724 -196 0 0 0 0 0 0 0 0 0 0
+merge "a_652_4812#" "latch_2_0/inv_W2_1/Vout"
+merge "latch_2_0/inv_W2_1/Vout" "latch_2_0/inv_W2_0/Vin"
+merge "latch_2_0/inv_W2_0/Vin" "preamp_part1_0/li_n718_44#"
+merge "preamp_part1_0/li_n718_44#" "a_366_4532#"
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" -1966.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13884 -268 0 0 0 0 -53924 -836 -1223534 -4500 -375200 -2800 0 0 0 0 0 0
+merge "preamp_part2_0/sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "preamp_part1_0/a_506_940#"
+merge "preamp_part1_0/a_506_940#" "preamp_part2_0/a_1170_652#"
+merge "preamp_part2_0/a_1170_652#" "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#"
+merge "preamp_part2_0/sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "preamp_part1_0/a_n302_940#"
+merge "preamp_part1_0/a_n302_940#" "preamp_part2_0/a_148_644#"
+merge "preamp_part2_0/a_148_644#" "preamp_part1_0/a_80_n258#"
+merge "preamp_part1_0/a_80_n258#" "CLK"
+merge "preamp_part1_0/a_388_n260#" "Vp" -101.695 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12012 -800 0 0 0 0 0 0 0 0 0 0
+merge "SR_latch_0/sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "latch_2_0/inv_W2_1/Vin" -737.106 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -153428 -60 0 0 -140572 -192 -102904 -204 0 0 0 0 0 0 0 0 0 0
+merge "latch_2_0/inv_W2_1/Vin" "preamp_part1_0/li_954_42#"
+merge "preamp_part1_0/li_954_42#" "a_1048_4532#"
+merge "SR_latch_0/a_262_508#" "Outn" -54.8902 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10584 -220 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/comparator_v5.mag b/mag/comparator_v5.mag
new file mode 100644
index 0000000..8dde525
--- /dev/null
+++ b/mag/comparator_v5.mag
@@ -0,0 +1,803 @@
+magic
+tech sky130A
+timestamp 1647352381
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+rect -441 -182 -407 -51
+rect -294 -182 -265 -51
+rect 148 -58 295 54
+rect 558 -58 708 56
+rect -441 -208 -265 -182
+<< via1 >>
+rect 1714 2607 1826 2727
+rect 2114 2607 2226 2727
+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect 433 1811 485 1851
+rect -1256 1240 -1131 1413
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+rect 262 1278 288 1282
+rect 262 1259 265 1278
+rect 265 1259 283 1278
+rect 283 1259 288 1278
+rect 262 1256 288 1259
+rect 552 1278 578 1282
+rect 552 1259 555 1278
+rect 555 1259 573 1278
+rect 573 1259 578 1278
+rect 552 1256 578 1259
+rect 212 603 240 634
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+rect 409 609 429 630
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+rect 1193 644 1305 659
+rect 1714 498 1826 618
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+rect -407 -182 -294 -51
+rect 406 5 455 49
+<< metal2 >>
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+rect 1664 2607 1714 2727
+rect 1826 2607 2114 2727
+rect 2226 2607 2266 2727
+rect -1285 2319 -1102 2342
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+rect -460 -412 1341 -268
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+<< via2 >>
+rect 1714 2607 1826 2727
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+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect 1714 1728 1826 1848
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+rect -407 -182 -294 -51
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+rect 2114 498 2226 618
+<< metal3 >>
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+rect 2114 2607 2226 2727
+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect 1714 1728 1826 1848
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+rect 1714 1148 1826 1268
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+<< metal4 >>
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+rect 1662 2675 1714 2727
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+rect 2226 2607 2269 2727
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+rect -885 40 -856 213
+rect -731 40 -702 213
+rect -885 7 -702 40
+rect 1668 -403 2266 498
+rect 1668 -437 2251 -403
+<< via4 >>
+rect -1256 2146 -1131 2319
+rect -856 2146 -731 2319
+rect -1256 1240 -1131 1413
+rect -856 1240 -731 1413
+rect -1256 690 -1131 863
+rect -856 690 -731 863
+rect -1256 40 -1131 213
+rect -856 40 -731 213
+<< metal5 >>
+rect -1299 2536 -675 2778
+rect -1296 2319 -677 2536
+rect -1296 2146 -1256 2319
+rect -1131 2146 -856 2319
+rect -731 2146 -677 2319
+rect -1296 1413 -677 2146
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+rect -1131 1240 -856 1413
+rect -731 1240 -677 1413
+rect -1296 863 -677 1240
+rect -1296 690 -1256 863
+rect -1131 690 -856 863
+rect -731 690 -677 863
+rect -1296 213 -677 690
+rect -1296 40 -1256 213
+rect -1131 40 -856 213
+rect -731 40 -677 213
+rect -1296 -442 -677 40
+use SR_latch SR_latch_0 ~/mycomparator_copy1/layout/latch
+timestamp 1646810677
+transform 1 0 197 0 1 2227
+box 0 0 436 474
+use latch_2 latch_2_0 ~/mycomparator/layout/latch
+timestamp 1647337196
+transform 1 0 43 0 1 1318
+box 0 0 801 501
+use preamp_part1 preamp_part1_0 ~/mycomparator/layout/preamp
+timestamp 1646810354
+transform 1 0 360 0 1 130
+box -360 -130 510 508
+use preamp_part2 preamp_part2_0 ~/mycomparator/layout/preamp
+timestamp 1646810398
+transform 1 0 69 0 1 688
+box 58 1 641 544
+<< labels >>
+rlabel metal3 413 -412 413 -412 5 CLK
+rlabel metal1 220 -58 220 -58 5 Vn
+rlabel metal1 640 -58 640 -58 5 Vp
+rlabel locali 257 2431 257 2431 7 Outp
+rlabel locali 595 2448 595 2448 3 Outn
+rlabel metal5 -988 -442 -988 -442 5 GND
+rlabel metal4 2008 -437 2008 -437 5 VDD
+rlabel poly 483 1945 483 1945 1 CLKBAR
+<< end >>
diff --git a/mag/comparator_v5.spice b/mag/comparator_v5.spice
new file mode 100644
index 0000000..9c41927
--- /dev/null
+++ b/mag/comparator_v5.spice
@@ -0,0 +1,143 @@
+* SPICE3 file created from comparator_v5.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/Vin inv_W2_1/GND sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_0/Vin inv_W2_1/Vout VSUBS
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vin inv_W2_0/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vout inv_W2_1/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_1/VDD
++ inv_W2_1/VDD m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+
+.ends
+
+
+* Top level circuit comparator_v5
+
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin Outn VDD VDD GND GND
++ SR_latch
+Xpreamp_part1_0 latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin m1_n58_544# CLK CLK
++ VDD Vn CLK m1_1202_1938# VDD Vp GND GND preamp_part1
+Xlatch_2_0 VDD latch_2_0/inv_W2_1/Vin GND VDD CLKBAR latch_2_0/inv_W2_0/Vin latch_2_0/inv_W2_0/Vin
++ GND latch_2
+
+.end
+
diff --git "a/mag/inv_W2\0430.ext" "b/mag/inv_W2\0430.ext"
new file mode 100644
index 0000000..15af871
--- /dev/null
+++ "b/mag/inv_W2\0430.ext"
@@ -0,0 +1,51 @@
+timestamp 1647355571
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5Z8B#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0 1 0 141 0 1 654
+use sky130_fd_pr__nfet_01v8_XJTKXQ#1 sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 219 0 1 182
+node "GND" 207 364.064 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34556 1620 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 91 169.775 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 760 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 120 244.033 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24468 1080 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_156_12#" 127 111.727 156 12 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6048 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_252_300#" 56 32.867 252 300 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 251 302.04 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 516 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "VDD" "Vin" 7.08611
+cap "Vin" "Vout" 81.5294
+cap "a_156_12#" "a_252_300#" 2.875
+cap "GND" "Vout" 18.672
+cap "Vin" "a_156_12#" 2.89916
+cap "Vin" "a_252_300#" 9.06061
+cap "VDD" "Vout" 3
+cap "Vin" "GND" 24.9623
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 42.0143
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 11.1195
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" 30.4523
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" 67.2375
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" 6.10637
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" -7.15
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 14.0899
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" 12.3374
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" -104.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2828 -468 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "GND"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_33_n122#" "a_252_300#" -117.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -540 -336 0 0 -896 -144 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_252_300#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#" "a_156_12#"
+merge "a_156_12#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "Vin"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_229_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" -147.998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2968 -560 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "VDD"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" -76.2649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2360 -348 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "Vout"
diff --git "a/mag/inv_W2\0430.mag" "b/mag/inv_W2\0430.mag"
new file mode 100755
index 0000000..61116f5
--- /dev/null
+++ "b/mag/inv_W2\0430.mag"
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1647355571
+<< poly >>
+rect 156 436 186 454
+rect 84 416 186 436
+rect 84 370 100 416
+rect 150 370 186 416
+rect 84 352 186 370
+rect 156 298 186 352
+rect 252 300 282 326
+rect 156 12 282 60
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 826 140 828
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 454
+rect 202 364 388 420
+rect 202 260 236 364
+rect 106 -20 140 114
+rect 298 -20 332 116
+rect -100 -72 388 -20
+use sky130_fd_pr__nfet_01v8_XJTKXQ#1 sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646324451
+transform 1 0 219 0 1 182
+box -125 -126 125 126
+use sky130_fd_pr__pfet_01v8_AC5Z8B#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0
+timestamp 1646324451
+transform 1 0 141 0 1 654
+box -261 -726 263 224
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 -46 -100 -46 7 GND
+rlabel locali -100 854 -100 854 7 VDD
+<< end >>
diff --git a/mag/inv_W2.ext b/mag/inv_W2.ext
new file mode 100755
index 0000000..2d1cdde
--- /dev/null
+++ b/mag/inv_W2.ext
@@ -0,0 +1,51 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0 1 0 141 0 1 654
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 219 0 1 182
+node "GND" 217 364.064 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34556 1620 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 95 169.775 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 760 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 126 244.033 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24468 1080 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_156_12#" 127 111.727 156 12 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6048 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_252_300#" 56 32.867 252 300 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 254 302.04 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 516 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "GND" 24.9623
+cap "Vin" "VDD" 7.08611
+cap "Vin" "a_252_300#" 9.06061
+cap "Vout" "GND" 18.672
+cap "VDD" "Vout" 3
+cap "a_252_300#" "a_156_12#" 2.875
+cap "Vin" "Vout" 81.5294
+cap "Vin" "a_156_12#" 2.89916
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 11.1195
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 14.0899
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 6.10637
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 42.0143
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 30.4523
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 12.3374
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 67.2375
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" -7.15
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" -104.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2828 -468 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "GND"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_33_n122#" "a_252_300#" -117.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -540 -336 0 0 -896 -144 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_252_300#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#" "a_156_12#"
+merge "a_156_12#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "Vin"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_229_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" -147.998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2968 -560 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "VDD"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" -76.2649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2360 -348 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "Vout"
diff --git a/mag/inv_W2.mag b/mag/inv_W2.mag
new file mode 100755
index 0000000..66c19e1
--- /dev/null
+++ b/mag/inv_W2.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< poly >>
+rect 156 436 186 454
+rect 84 416 186 436
+rect 84 370 100 416
+rect 150 370 186 416
+rect 84 352 186 370
+rect 156 298 186 352
+rect 252 300 282 326
+rect 156 12 282 60
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 826 140 828
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 454
+rect 202 364 388 420
+rect 202 260 236 364
+rect 106 -20 140 114
+rect 298 -20 332 116
+rect -100 -72 388 -20
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646324451
+transform 1 0 219 0 1 182
+box -125 -126 125 126
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0
+timestamp 1646324451
+transform 1 0 141 0 1 654
+box -261 -726 263 224
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 -46 -100 -46 7 GND
+rlabel locali -100 854 -100 854 7 VDD
+<< end >>
diff --git a/mag/latch/SR_latch.ext b/mag/latch/SR_latch.ext
new file mode 100644
index 0000000..535dc50
--- /dev/null
+++ b/mag/latch/SR_latch.ext
@@ -0,0 +1,67 @@
+timestamp 1646810677
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_1 1 0 711 0 1 726
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_0 1 0 229 0 1 724
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_1 1 0 669 0 1 250
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_0 1 0 273 0 1 248
+node "GND" 289 542.754 0 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55756 2396 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 364 159.564 2 896 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63484 2844 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_518_392#" 532 438.835 518 392 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13888 748 0 0 40980 1532 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_262_508#" 297 224.078 262 508 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9044 440 0 0 44880 1612 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_648_848#" 112 18.0306 648 848 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6804 360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_166_848#" 112 18.0306 166 848 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6804 360 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_0_524#" 3688 1051.63 0 524 nw 0 0 0 0 350544 2548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_648_848#" "a_518_392#" 2.85124
+cap "a_648_848#" "VDD" 51.7866
+cap "a_262_508#" "a_518_392#" 404.208
+cap "VDD" "a_262_508#" 52.2896
+cap "VDD" "a_518_392#" 8.97418
+cap "a_648_848#" "w_0_524#" 99
+cap "a_262_508#" "w_0_524#" 259.748
+cap "a_648_848#" "a_166_848#" 3.48876
+cap "w_0_524#" "a_518_392#" 117.472
+cap "a_166_848#" "a_262_508#" 2.89916
+cap "VDD" "w_0_524#" 429.12
+cap "a_166_848#" "VDD" 51.7866
+cap "a_166_848#" "w_0_524#" 99
+cap "GND" "a_262_508#" 11.6389
+cap "GND" "a_518_392#" 41.7112
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 3.01639
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 4.46269
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 50.8278
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" 43.4924
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" 9.51724
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" -78.9324
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" -95.631
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" 15.3087
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" 2.58427
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" -115.525
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" 44.4318
+cap "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" 66.447
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" "sky130_fd_pr__pfet_01v8_AC5E9B_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5E9B_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" -52.832 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1224 -208 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "GND"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n33_n100#" -46.0998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -660 -224 0 0 -2040 -256 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_33_n126#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_33_n126#" "a_518_392#"
+merge "a_518_392#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n63_n130#" "a_648_848#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_63_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n125_n74#" -12.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4352 -528 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_63_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_63_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n125_n74#" "VDD"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/w_n161_n200#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" -729.024 0 0 0 0 -243008 -2888 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/w_n161_n200#" "w_0_524#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_33_n126#" -28.5522 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -600 -220 0 0 -1944 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_33_n126#" "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_1/a_n33_n100#" "a_262_508#"
+merge "a_262_508#" "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n63_n130#"
+merge "sky130_fd_pr__pfet_01v8_AC5E9B_0/a_n63_n130#" "a_166_848#"
diff --git a/mag/latch/SR_latch.mag b/mag/latch/SR_latch.mag
new file mode 100755
index 0000000..3aa0bc6
--- /dev/null
+++ b/mag/latch/SR_latch.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646810677
+<< nwell >>
+rect 0 524 872 926
+<< poly >>
+rect 166 848 292 902
+rect 648 848 774 902
+rect 262 576 292 610
+rect 262 566 380 576
+rect 262 520 318 566
+rect 364 520 380 566
+rect 262 508 380 520
+rect 648 474 678 606
+rect 518 450 678 474
+rect 518 410 540 450
+rect 582 434 678 450
+rect 582 410 602 434
+rect 518 392 602 410
+<< polycont >>
+rect 318 520 364 566
+rect 540 410 582 450
+<< locali >>
+rect 2 896 872 948
+rect 114 774 152 896
+rect 308 776 344 896
+rect 596 766 632 896
+rect 790 768 826 896
+rect 212 470 248 652
+rect 696 584 732 696
+rect 306 566 732 584
+rect 306 520 318 566
+rect 364 520 732 566
+rect 306 504 732 520
+rect 212 450 598 470
+rect 212 410 540 450
+rect 582 410 598 450
+rect 212 392 598 410
+rect 212 272 248 392
+rect 696 316 732 504
+rect 298 52 336 184
+rect 606 52 644 194
+rect 0 0 872 52
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_0
+timestamp 1646507701
+transform 1 0 273 0 1 248
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_F5U58G sky130_fd_pr__nfet_01v8_F5U58G_1
+timestamp 1646507701
+transform 1 0 669 0 1 250
+box -73 -126 73 126
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_0
+timestamp 1646507701
+transform 1 0 229 0 1 724
+box -161 -200 161 200
+use sky130_fd_pr__pfet_01v8_AC5E9B sky130_fd_pr__pfet_01v8_AC5E9B_1
+timestamp 1646507701
+transform 1 0 711 0 1 726
+box -161 -200 161 200
+<< labels >>
+rlabel locali 872 934 872 934 3 VDD
+rlabel locali 870 26 870 26 3 GND
+<< end >>
diff --git a/mag/latch/latch.mag b/mag/latch/latch.mag
new file mode 100755
index 0000000..7e24a0d
--- /dev/null
+++ b/mag/latch/latch.mag
@@ -0,0 +1,36 @@
+magic
+tech sky130A
+timestamp 1646333448
+<< locali >>
+rect -6 450 11 475
+rect 0 286 6 305
+rect 34 286 91 305
+rect -6 0 6 26
+<< viali >>
+rect 6 286 34 305
+rect 1 218 41 246
+rect 517 218 557 246
+<< metal1 >>
+rect -6 305 40 312
+rect -6 286 6 305
+rect 34 286 40 305
+rect -6 282 40 286
+rect -6 246 567 253
+rect -6 218 1 246
+rect 41 218 517 246
+rect 557 218 567 246
+rect -6 211 567 218
+use inv_W2 inv_W2_0 ~/mycomparator/layout/myinv_layout2
+timestamp 1646324451
+transform 1 0 60 0 1 36
+box -60 -36 202 439
+use inv_W2 inv_W2_1
+timestamp 1646324451
+transform 1 0 322 0 1 36
+box -60 -36 202 439
+<< labels >>
+rlabel metal1 -6 297 -6 297 7 outn
+rlabel metal1 -6 232 -6 232 7 outp
+rlabel locali -6 463 -6 463 7 VDD
+rlabel locali -6 14 -6 14 7 GND
+<< end >>
diff --git a/mag/latch/latch_2.ext b/mag/latch/latch_2.ext
new file mode 100644
index 0000000..40bf2ab
--- /dev/null
+++ b/mag/latch/latch_2.ext
@@ -0,0 +1,46 @@
+timestamp 1646818746
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W2 inv_W2_0 1 0 120 0 1 72
+use inv_W2 inv_W2_1 1 0 1198 0 1 72
+use sky130_fd_pr__pfet_01v8_5SVZDE sky130_fd_pr__pfet_01v8_5SVZDE_0 1 0 789 0 1 712
+node "m1_718_782#" 2 233.662 718 782 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25988 1272 0 0 0 0 0 0 0 0 0 0
+node "li_520_0#" 134 283.353 520 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29744 1248 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_480_436#" 139 318.512 480 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35840 1392 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_502_900#" 224 400.76 502 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38768 1780 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_718_782#" "li_502_900#" 104.31
+cap "li_480_436#" "li_502_900#" 7.31014
+cap "li_520_0#" "li_480_436#" 49.1562
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "inv_W2_0/li_n100_828#" 182.468
+cap "inv_W2_0/li_n100_828#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 227.111
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" 13.1085
+cap "inv_W2_0/li_202_260#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 57.529
+cap "inv_W2_0/li_n100_828#" "inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 35.9111
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 85.249
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "inv_W2_0/li_n100_828#" 28.8966
+cap "inv_W2_0/li_n100_828#" "inv_W2_0/li_n100_n72#" -1.77636e-15
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "inv_W2_0/li_202_260#" 11.0141
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 48.7057
+cap "inv_W2_0/li_202_260#" "inv_W2_0/li_n100_n72#" -1.54688
+cap "inv_W2_0/li_n100_828#" "inv_W2_0/li_202_260#" 65.0199
+cap "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 25.5595
+cap "inv_W2_1/li_n100_828#" "inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" -96.9644
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" -210.702 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7644 -572 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n173_n100#" "inv_W2_1/li_n100_828#"
+merge "inv_W2_1/li_n100_828#" "inv_W2_0/li_n100_828#"
+merge "inv_W2_0/li_n100_828#" "li_502_900#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/VSUBS" "inv_W2_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_1/VSUBS" "inv_W2_0/VSUBS"
+merge "inv_W2_0/VSUBS" "VSUBS"
+merge "inv_W2_1/a_84_352#" "inv_W2_0/li_202_260#" -71.1308 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10864 -396 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/li_202_260#" "li_480_436#"
+merge "inv_W2_1/li_n100_n72#" "inv_W2_0/li_n100_n72#" -36.071 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15080 -244 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/li_n100_n72#" "li_520_0#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#" "inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" -1279.2 0 0 0 0 -426400 -3720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_1/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#"
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_111_n100#" "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" -149.677 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2668 -300 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "m1_718_782#"
diff --git a/mag/latch/latch_2.mag b/mag/latch/latch_2.mag
new file mode 100755
index 0000000..d8300aa
--- /dev/null
+++ b/mag/latch/latch_2.mag
@@ -0,0 +1,30 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646810591
+<< locali >>
+rect 502 900 1140 950
+rect 628 796 662 900
+rect 820 802 854 900
+rect 480 436 1120 492
+rect 520 0 1092 52
+<< metal1 >>
+rect 718 962 956 1002
+rect 718 782 764 962
+rect 910 784 956 962
+use inv_W2 inv_W2_0 ~/mycomparator/layout/myinv_layout2
+timestamp 1646730554
+transform 1 0 120 0 1 72
+box -120 -72 404 878
+use inv_W2 inv_W2_1
+timestamp 1646730554
+transform 1 0 1198 0 1 72
+box -120 -72 404 878
+use sky130_fd_pr__pfet_01v8_5SVZDE sky130_fd_pr__pfet_01v8_5SVZDE_0
+timestamp 1646503715
+transform 1 0 789 0 1 712
+box -789 -196 805 222
+<< labels >>
+rlabel space 1602 26 1602 26 3 GND
+rlabel space 1602 936 1602 936 3 VDD
+<< end >>
diff --git a/mag/latch/sky130A.magicrc b/mag/latch/sky130A.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/latch/sky130A.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
new file mode 100644
index 0000000..431a549
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
@@ -0,0 +1,13 @@
+timestamp 1646507701
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 470 -13.94 15 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 470 -13.94 -73 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 49.234 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n100#" "a_n73_n100#" 253.905
+device msubckt sky130_fd_pr__nfet_01v8 -15 -100 -14 -99 l=30 w=200 "VSUBS" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.mag b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.mag
new file mode 100755
index 0000000..88fc7a8
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646507701
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
new file mode 100644
index 0000000..46fa16d
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
@@ -0,0 +1,28 @@
+timestamp 1646503715
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_111_n100#" 711 -177.94 111 -100 pdif 0 0 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_15_n100#" 672 -177.94 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n81_n100#" 672 -177.94 -81 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n173_n100#" 711 -177.94 -173 -100 pdif 0 0 0 0 0 0 0 0 0 0 12400 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n111_n158#" 1654 51.4524 -111 -158 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37416 2332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n789_n196#" 6483 1998.88 -789 -196 nw 0 0 0 0 666292 4024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n173_n100#" "a_15_n100#" 105.087
+cap "a_15_n100#" "a_n81_n100#" 290.71
+cap "w_n789_n196#" "a_111_n100#" 200.332
+cap "a_n173_n100#" "w_n789_n196#" 200.332
+cap "w_n789_n196#" "a_n81_n100#" 200.332
+cap "w_n789_n196#" "a_15_n100#" 200.332
+cap "a_n173_n100#" "a_111_n100#" 64.2137
+cap "a_111_n100#" "a_n81_n100#" 105.087
+cap "a_n173_n100#" "a_n81_n100#" 290.71
+cap "a_111_n100#" "a_15_n100#" 290.71
+cap "w_n789_n196#" "a_n111_n158#" 311.3
+device msubckt sky130_fd_pr__pfet_01v8 81 -100 82 -99 l=30 w=200 "w_n789_n196#" "a_n111_n158#" 60 0 "a_15_n100#" 200 0 "a_111_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -15 -100 -14 -99 l=30 w=200 "w_n789_n196#" "a_n111_n158#" 60 0 "a_n81_n100#" 200 0 "a_15_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -111 -100 -110 -99 l=30 w=200 "w_n789_n196#" "a_n111_n158#" 60 0 "a_n173_n100#" 200 0 "a_n81_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.mag b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.mag
new file mode 100755
index 0000000..f6c91f5
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.mag
@@ -0,0 +1,77 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646503715
+<< nwell >>
+rect -789 -196 805 222
+<< pmos >>
+rect -111 -100 -81 100
+rect -15 -100 15 100
+rect 81 -100 111 100
+<< pdiff >>
+rect -173 88 -111 100
+rect -173 -88 -161 88
+rect -127 -88 -111 88
+rect -173 -100 -111 -88
+rect -81 88 -15 100
+rect -81 -88 -65 88
+rect -31 -88 -15 88
+rect -81 -100 -15 -88
+rect 15 88 81 100
+rect 15 -88 31 88
+rect 65 -88 81 88
+rect 15 -100 81 -88
+rect 111 88 173 100
+rect 111 -88 127 88
+rect 161 -88 173 88
+rect 111 -100 173 -88
+<< pdiffc >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< poly >>
+rect -111 124 111 158
+rect -111 100 -81 124
+rect -15 100 15 124
+rect 81 100 111 124
+rect -111 -124 -81 -100
+rect -15 -124 15 -100
+rect 81 -124 111 -100
+rect -111 -158 111 -124
+<< locali >>
+rect -161 88 -127 104
+rect -161 -104 -127 -88
+rect -65 88 -31 104
+rect -65 -104 -31 -88
+rect 31 88 65 104
+rect 31 -104 65 -88
+rect 127 88 161 104
+rect 127 -104 161 -88
+<< viali >>
+rect -161 -88 -127 88
+rect -65 -88 -31 88
+rect 31 -88 65 88
+rect 127 -88 161 88
+<< metal1 >>
+rect -167 88 -121 100
+rect -167 -88 -161 88
+rect -127 -88 -121 88
+rect -167 -100 -121 -88
+rect -71 88 -25 100
+rect -71 -88 -65 88
+rect -31 -88 -25 88
+rect -71 -100 -25 -88
+rect 25 88 71 100
+rect 25 -88 31 88
+rect 65 -88 71 88
+rect 25 -100 71 -88
+rect 121 88 167 100
+rect 121 -88 127 88
+rect 161 -88 167 88
+rect 121 -100 167 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 3 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
new file mode 100644
index 0000000..66ae58c
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
@@ -0,0 +1,25 @@
+timestamp 1646507701
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 712 -171.38 63 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 653 -171.38 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 712 -171.38 -125 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n126#" 411 4.452 33 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n130#" 411 4.452 -63 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n161_n200#" 2895 364.512 -161 -200 nw 0 0 0 0 121504 1444 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_63_n100#" "a_n125_n74#" 78.1987
+cap "a_63_n100#" "a_n33_n100#" 216.232
+cap "a_33_n126#" "w_n161_n200#" 47.3
+cap "a_n125_n74#" "w_n161_n200#" 157.44
+cap "a_33_n126#" "a_n63_n130#" 18.1212
+cap "w_n161_n200#" "a_n33_n100#" 157.44
+cap "a_63_n100#" "w_n161_n200#" 157.44
+cap "a_n63_n130#" "w_n161_n200#" 47.3
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n161_n200#" "a_33_n126#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n161_n200#" "a_n63_n130#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.mag b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.mag
new file mode 100755
index 0000000..99c3b1d
--- /dev/null
+++ b/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646507701
+<< nwell >>
+rect -65 162 161 200
+rect -161 -162 161 162
+rect -161 -200 65 -162
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< pdiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 126
+rect 33 100 63 130
+rect -63 -130 -33 -100
+rect 33 -126 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/.spiceinit b/mag/myinv_layout2/.spiceinit
new file mode 100755
index 0000000..6bc157f
--- /dev/null
+++ b/mag/myinv_layout2/.spiceinit
@@ -0,0 +1 @@
+set ngbehavior=hs
diff --git a/mag/myinv_layout2/PLS_INV1.raw b/mag/myinv_layout2/PLS_INV1.raw
new file mode 100755
index 0000000..accab2f
--- /dev/null
+++ b/mag/myinv_layout2/PLS_INV1.raw
Binary files differ
diff --git a/mag/myinv_layout2/buffer_1.ext b/mag/myinv_layout2/buffer_1.ext
new file mode 100755
index 0000000..8808168
--- /dev/null
+++ b/mag/myinv_layout2/buffer_1.ext
@@ -0,0 +1,22 @@
+timestamp 1646324508
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W2 inv_W2_0 1 0 588 0 1 72
+use inv_W1 inv_W1_0 1 0 100 0 1 72
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W1_0/Vin" "inv_W2_0/Vin" 11.0875
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "inv_W2_0/Vin" 23.6443
+cap "inv_W1_0/Vin" "inv_W2_0/GND" 2.90674
+cap "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "inv_W2_0/VDD" 116.829
+cap "inv_W2_0/GND" "inv_W2_0/Vin" 32.2784
+cap "inv_W2_0/Vin" "inv_W2_0/VDD" 33.1221
+cap "inv_W2_0/GND" "inv_W2_0/VDD" -1.77636e-15
+merge "inv_W1_0/VSUBS" "inv_W2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VSUBS" "VSUBS"
+merge "inv_W1_0/Vout" "inv_W2_0/Vin" -32.196 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1120 -152 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/w_156_432#" "inv_W2_0/VDD" -52.545 0 0 0 0 -7640 -804 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1000 -140 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W2_0/VDD" "inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#"
+merge "inv_W1_0/GND" "inv_W2_0/GND" -30.482 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1040 -144 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_1.mag b/mag/myinv_layout2/buffer_1.mag
new file mode 100755
index 0000000..9a3422f
--- /dev/null
+++ b/mag/myinv_layout2/buffer_1.mag
@@ -0,0 +1,12 @@
+magic
+tech sky130A
+timestamp 1646324508
+use inv_W1 inv_W1_0
+timestamp 1645263751
+transform 1 0 50 0 1 36
+box -50 -36 194 439
+use inv_W2 inv_W2_0
+timestamp 1646324451
+transform 1 0 294 0 1 36
+box -60 -36 202 439
+<< end >>
diff --git a/mag/myinv_layout2/buffer_1.spice b/mag/myinv_layout2/buffer_1.spice
new file mode 100755
index 0000000..8dd610a
--- /dev/null
+++ b/mag/myinv_layout2/buffer_1.spice
@@ -0,0 +1,48 @@
+* SPICE3 file created from buffer_1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n63_n126# a_n159_n130# a_33_n130# w_n257_n200# a_n33_n100# a_129_n126# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_159_n100# a_129_n126# a_63_n100# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n130# a_n221_n74# w_n257_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n142# a_63_n100# a_n63_n142# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n142# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n142# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 Vin VDD GND w_n106_454# VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD VDD VDD VDD Vin Vin Vin w_n106_454# VDD Vin
++ VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin GND Vin GND VDD VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1
+Xinv_W2_0 inv_W2_0/Vin inv_W2_0/VDD VSUBS inv_W2_0/VDD VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/Vin inv_W2_0/VDD VSUBS inv_W1
+.ends
+
diff --git a/mag/myinv_layout2/buffer_12.ext b/mag/myinv_layout2/buffer_12.ext
new file mode 100755
index 0000000..efa80fe
--- /dev/null
+++ b/mag/myinv_layout2/buffer_12.ext
@@ -0,0 +1,30 @@
+timestamp 1646326465
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use buffer_2 buffer_2_0 1 0 990 0 1 0
+use buffer_1 buffer_1_0 1 0 0 0 1 0
+node "GND" 18 37.8116 0 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1872 176 0 0 0 0 0 0 0 0 0 0 0 0
+node "buf_out" 13 49.7444 5828 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3248 228 0 0 0 0 0 0 0 0 0 0 0 0
+node "buf_in" 13 46.9736 0 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2912 216 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 14 40.575 0 900 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2200 188 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "buf_in" 3.09375
+cap "buffer_2_0/inv_W8_0/w_354_500#" "buffer_2_0/inv_W8_0/a_804_430#" 83.8408
+cap "buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_2_0/inv_W8_0/a_804_430#" 43.2725
+cap "buffer_1_0/inv_W2_0/Vin" "buffer_2_0/inv_W8_0/a_466_816#" 11.4029
+cap "buffer_2_0/inv_W8_0/a_804_430#" "buffer_2_0/inv_W8_0/li_354_0#" -0.171875
+cap "buffer_2_0/inv_W8_0/w_354_500#" "buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 75.6961
+cap "buffer_1_0/inv_W1_0/Vin" "buffer_2_0/inv_W8_0/li_354_0#" -3.09375
+merge "buffer_1_0/VSUBS" "buffer_2_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_2_0/VSUBS" "VSUBS"
+merge "buffer_1_0/inv_W2_0/GND" "buffer_2_0/inv_W8_0/li_354_0#" -60.0478 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1976 -284 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_2_0/inv_W8_0/li_354_0#" "GND"
+merge "buffer_2_0/Vout" "buf_out" -37.934 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9520 -228 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_1_0/inv_W2_0/VDD" "buffer_2_0/inv_W8_0/li_354_902#" -63.5794 0 0 0 0 -820 -824 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2296 -288 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_2_0/inv_W8_0/li_354_902#" "VDD"
+merge "VDD" "buffer_2_0/inv_W8_0/w_354_500#"
+merge "buffer_1_0/inv_W2_0/Vout" "buffer_2_0/inv_W8_0/a_804_430#" -23.0599 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -108 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "buffer_1_0/inv_W1_0/Vin" "buf_in" -46.9736 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2912 -216 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_12.mag b/mag/myinv_layout2/buffer_12.mag
new file mode 100755
index 0000000..ea42762
--- /dev/null
+++ b/mag/myinv_layout2/buffer_12.mag
@@ -0,0 +1,22 @@
+magic
+tech sky130A
+timestamp 1646326465
+<< locali >>
+rect 0 450 22 475
+rect 0 218 26 246
+rect 2914 218 2943 246
+rect 0 0 18 26
+use buffer_1 buffer_1_0
+timestamp 1646324508
+transform 1 0 0 0 1 0
+box 0 0 496 475
+use buffer_2 buffer_2_0
+timestamp 1646326308
+transform 1 0 495 0 1 0
+box 0 0 2448 477
+<< labels >>
+rlabel locali 0 20 0 20 7 GND
+rlabel locali 2943 238 2943 238 3 buf_out
+rlabel locali 0 238 0 238 7 buf_in
+rlabel locali 0 469 0 469 7 VDD
+<< end >>
diff --git a/mag/myinv_layout2/buffer_12.spice b/mag/myinv_layout2/buffer_12.spice
new file mode 100755
index 0000000..ef46354
--- /dev/null
+++ b/mag/myinv_layout2/buffer_12.spice
@@ -0,0 +1,201 @@
+* SPICE3 file created from buffer_12.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout VDD Vin GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 w_n1601_n200# VSUBS 3.82fF
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+C0 a_82_816# VSUBS 3.17fF
+C1 w_82_814# VSUBS 3.92fF
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W16_0/a_82_816# VSUBS 3.68fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.31fF
+.ends
+
+.subckt buffer_12
+Xbuffer_1_0 VDD buffer_1_0/inv_W2_0/Vout buf_in GND buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+C0 VDD 0 9.85fF
+C1 buffer_2_0/inv_W16_0/a_82_816# 0 3.68fF
+C2 GND 0 2.85fF
+.ends
+
diff --git a/mag/myinv_layout2/buffer_2.ext b/mag/myinv_layout2/buffer_2.ext
new file mode 100755
index 0000000..6a8155a
--- /dev/null
+++ b/mag/myinv_layout2/buffer_2.ext
@@ -0,0 +1,27 @@
+timestamp 1646326308
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W16 inv_W16_0 1 0 1708 0 1 0
+use inv_W8 inv_W8_0 1 0 -354 0 1 0
+node "Vout" 15 44.2028 4850 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_1666_500#" 1943 420 1666 500 nw 0 0 0 0 140000 1500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 15.1736
+cap "inv_W8_0/a_466_816#" "inv_W16_0/a_82_816#" 1.35641
+cap "inv_W16_0/a_468_358#" "inv_W8_0/a_466_816#" 16.3371
+cap "inv_W16_0/a_468_358#" "inv_W16_0/li_n14_0#" -0.171875
+cap "inv_W16_0/a_468_358#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 48.7475
+cap "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "inv_W16_0/li_n14_902#" 16.9157
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/a_468_358#" 105.456
+cap "inv_W16_0/li_n14_902#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 120.656
+merge "inv_W8_0/VSUBS" "inv_W16_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/VSUBS" "VSUBS"
+merge "inv_W8_0/li_512_546#" "inv_W16_0/a_468_358#" -8.3746 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15768 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/li_354_0#" "inv_W16_0/li_n14_0#" -8.0948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W8_0/w_354_500#" "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 271.488 0 0 0 0 90496 -2304 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_1666_500#"
+merge "inv_W8_0/li_354_902#" "inv_W16_0/li_n14_902#" -25.0105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 -108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W16_0/li_128_546#" "Vout" -44.2028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2576 -204 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_2.mag b/mag/myinv_layout2/buffer_2.mag
new file mode 100755
index 0000000..12f4f9a
--- /dev/null
+++ b/mag/myinv_layout2/buffer_2.mag
@@ -0,0 +1,18 @@
+magic
+tech sky130A
+timestamp 1646326308
+<< nwell >>
+rect 833 250 1008 450
+<< locali >>
+rect 2425 218 2448 246
+use inv_W8 inv_W8_0
+timestamp 1646325197
+transform 1 0 -177 0 1 0
+box 177 0 1025 477
+use inv_W16 inv_W16_0
+timestamp 1646325283
+transform 1 0 854 0 1 0
+box -7 0 1594 477
+<< labels >>
+rlabel locali 2448 232 2448 232 3 Vout
+<< end >>
diff --git a/mag/myinv_layout2/buffer_sample_lay.ext b/mag/myinv_layout2/buffer_sample_lay.ext
new file mode 100755
index 0000000..3c5ab2f
--- /dev/null
+++ b/mag/myinv_layout2/buffer_sample_lay.ext
@@ -0,0 +1,29 @@
+timestamp 1645264122
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use inv_W1 inv_W1_1 1 0 588 0 1 72
+use inv_W1 inv_W1_0 1 0 100 0 1 72
+node "GND" 14 41.4764 0 2 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2288 192 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 26 34.9668 950 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1456 164 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 16 42.3556 0 436 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2352 196 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 16 36.0384 -2 902 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1728 168 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "Vin" 3.62827
+cap "inv_W1_1/Vin" "inv_W1_1/GND" 47.9354
+cap "inv_W1_1/GND" "inv_W1_0/Vin" 0.314602
+cap "inv_W1_1/VDD" "inv_W1_1/Vout" 14.3882
+cap "inv_W1_1/Vin" "inv_W1_0/Vin" 15.2675
+cap "inv_W1_1/VDD" "inv_W1_1/GND" -1.42109e-14
+cap "inv_W1_1/Vin" "inv_W1_1/VDD" 31.3824
+merge "inv_W1_0/VDD" "VDD" -55.6296 0 0 0 0 0 -812 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1632 -264 0 0 0 0 0 0 0 0 0 0 0 0
+merge "VDD" "inv_W1_1/VDD"
+merge "inv_W1_0/VSUBS" "inv_W1_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_1/VSUBS" "VSUBS"
+merge "inv_W1_0/GND" "inv_W1_1/GND" -61.895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2200 -292 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_1/GND" "GND"
+merge "inv_W1_0/Vin" "Vin" -42.3556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2352 -196 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_0/Vout" "inv_W1_1/Vin" -22.96 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -112 0 0 0 0 0 0 0 0 0 0 0 0
+merge "inv_W1_1/Vout" "Vout" -34.9668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1456 -164 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/buffer_sample_lay.mag b/mag/myinv_layout2/buffer_sample_lay.mag
new file mode 100755
index 0000000..28edf44
--- /dev/null
+++ b/mag/myinv_layout2/buffer_sample_lay.mag
@@ -0,0 +1,22 @@
+magic
+tech sky130A
+timestamp 1645264122
+<< locali >>
+rect -1 451 17 475
+rect 0 218 21 246
+rect 475 218 488 246
+rect 0 1 22 27
+use inv_W1 inv_W1_0
+timestamp 1645263751
+transform 1 0 50 0 1 36
+box -50 -36 194 439
+use inv_W1 inv_W1_1
+timestamp 1645263751
+transform 1 0 294 0 1 36
+box -50 -36 194 439
+<< labels >>
+rlabel locali 0 6 0 6 7 GND
+rlabel locali 0 227 0 227 7 Vin
+rlabel locali -1 456 -1 456 7 VDD
+rlabel locali 488 227 488 227 3 Vout
+<< end >>
diff --git a/mag/myinv_layout2/buffer_sample_lay.spice b/mag/myinv_layout2/buffer_sample_lay.spice
new file mode 100755
index 0000000..ac80db0
--- /dev/null
+++ b/mag/myinv_layout2/buffer_sample_lay.spice
@@ -0,0 +1,32 @@
+* SPICE3 file created from buffer_sample_lay.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout Vin VDD GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+
+* Top level circuit buffer_sample_lay
+
+Xinv_W1_0 inv_W1_1/Vin Vin VDD GND inv_W1
+Xinv_W1_1 Vout inv_W1_1/Vin VDD GND inv_W1
+.global VDD
+.global GND
+.end
+
diff --git a/mag/myinv_layout2/inv.ext b/mag/myinv_layout2/inv.ext
new file mode 100755
index 0000000..4754063
--- /dev/null
+++ b/mag/myinv_layout2/inv.ext
@@ -0,0 +1,41 @@
+timestamp 1644846380
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_5YYKDE sky130_fd_pr__pfet_01v8_5YYKDE_0 1 0 21 0 1 730
+use sky130_fd_pr__nfet_01v8_QQ4XG9 sky130_fd_pr__nfet_01v8_QQ4XG9_0 1 0 71 0 1 141
+node "m1_18_0#" 0 51.1006 18 0 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 0 0 0 0 0 0 0 0 0 0
+node "m1_n100_448#" 0 -7.38 -100 448 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3816 284 0 0 0 0 0 0 0 0 0 0
+node "m1_36_976#" 0 0 36 976 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3816 284 0 0 0 0 0 0 0 0 0 0
+node "a_n46_72#" 545 8.14 -46 72 ndif 0 0 0 0 0 0 0 0 8800 488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_6_442#" 385 94.535 6 442 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8900 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n254_408#" 2764 923.34 -254 408 nw 0 0 0 0 304964 2232 0 0 42400 1012 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48144 1052 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_n160_72#" 0 0 -160 72 ppd 0 0 0 0 0 0 0 0 0 0 22800 628 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34528 748 0 0 0 0 0 0 0 0 0 0 0 0
+cap "m1_n100_448#" "a_6_442#" 11.52
+cap "m1_n100_448#" "w_n254_408#" 60.7004
+cap "w_n254_408#" "m1_36_976#" 60.7004
+cap "a_6_442#" "w_n254_408#" 94.05
+cap "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" 4.488
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_63_n200#" 41.087
+cap "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" 41.522
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_15_n69#" 4.73684
+cap "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n33_n200#" 11.4647
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" -86.3818
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n33_n200#" -5.68434e-14
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_63_n200#" "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_15_n69#" 11.8984
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n33_n200#" 7.82609
+cap "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_63_n200#" -1.13687e-13
+merge "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n33_n157#" "m1_18_0#" 9.4784 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -420 -240 0 0 0 0 -6148 -560 0 0 0 0 0 0 0 0 0 0
+merge "m1_18_0#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n81_n297#"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n81_n297#" "m1_n100_448#"
+merge "m1_n100_448#" "m1_36_976#"
+merge "m1_36_976#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_15_231#" "a_6_442#"
+merge "sky130_fd_pr__nfet_01v8_QQ4XG9_0/VSUBS" "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" -89.96 0 0 0 0 0 0 0 0 0 -400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -416 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_QQ4XG9_0/a_n73_n69#" "a_n46_72#"
+merge "a_n46_72#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS" "a_n160_72#"
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/a_n125_n200#" "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" -560.172 0 0 0 0 -185904 -1844 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -816 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_5YYKDE_0/w_n161_n300#" "w_n254_408#"
diff --git a/mag/myinv_layout2/inv.mag b/mag/myinv_layout2/inv.mag
new file mode 100755
index 0000000..88cc41a
--- /dev/null
+++ b/mag/myinv_layout2/inv.mag
@@ -0,0 +1,48 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644851365
+<< nwell >>
+rect -254 408 224 1046
+<< ndiff >>
+rect -46 72 -2 272
+<< psubdiff >>
+rect -160 248 -46 272
+rect -160 92 -126 248
+rect -76 92 -46 248
+rect -160 72 -46 92
+<< nsubdiff >>
+rect -210 896 -104 930
+rect -210 556 -180 896
+rect -138 556 -104 896
+rect -210 530 -104 556
+<< psubdiffcont >>
+rect -126 92 -76 248
+<< nsubdiffcont >>
+rect -180 556 -138 896
+<< poly >>
+rect 54 488 84 514
+rect 6 442 86 488
+rect 56 294 86 442
+<< locali >>
+rect -210 896 -92 934
+rect -210 556 -180 896
+rect -138 556 -92 896
+rect -210 526 -92 556
+rect -156 248 10 276
+rect -156 92 -126 248
+rect -76 92 10 248
+rect -156 68 10 92
+<< metal1 >>
+rect 36 976 142 1012
+rect -100 448 6 484
+rect 18 0 104 34
+use sky130_fd_pr__nfet_01v8_QQ4XG9 sky130_fd_pr__nfet_01v8_QQ4XG9_0
+timestamp 1644851365
+transform 1 0 71 0 1 141
+box -73 -157 73 157
+use sky130_fd_pr__pfet_01v8_5YYKDE sky130_fd_pr__pfet_01v8_5YYKDE_0
+timestamp 1644851365
+transform 1 0 21 0 1 730
+box -161 -300 161 300
+<< end >>
diff --git a/mag/myinv_layout2/inv.spice b/mag/myinv_layout2/inv.spice
new file mode 100755
index 0000000..4c427c4
--- /dev/null
+++ b/mag/myinv_layout2/inv.spice
@@ -0,0 +1,21 @@
+* SPICE3 file created from inv.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_5YYKDE a_15_231# a_n81_n297# w_n161_n300# a_n125_n200#
++ VSUBS
+X0 a_63_n200# a_15_231# a_n33_n200# w_n161_n300# sky130_fd_pr__pfet_01v8 ad=6.2e+11p pd=4.62e+06u as=6.6e+11p ps=4.66e+06u w=2e+06u l=150000u
+X1 a_n33_n200# a_n81_n297# a_n125_n200# w_n161_n300# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=6.2e+11p ps=4.62e+06u w=2e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_QQ4XG9 a_n73_n69# a_n33_n157# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+
+* Top level circuit inv
+
+Xsky130_fd_pr__pfet_01v8_5YYKDE_0 m1_18_0# m1_18_0# w_n254_408# w_n254_408# sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS
++ sky130_fd_pr__pfet_01v8_5YYKDE
+Xsky130_fd_pr__nfet_01v8_QQ4XG9_0 sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS m1_18_0#
++ sky130_fd_pr__pfet_01v8_5YYKDE_0/VSUBS sky130_fd_pr__nfet_01v8_QQ4XG9
+.end
+
diff --git a/mag/myinv_layout2/inv_W1.ext b/mag/myinv_layout2/inv_W1.ext
new file mode 100755
index 0000000..4752a17
--- /dev/null
+++ b/mag/myinv_layout2/inv_W1.ext
@@ -0,0 +1,43 @@
+timestamp 1645263751
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use pmos_2uf2 pmos_2uf2_0 1 0 219 0 1 622
+use nmos_1u nmos_1u_0 1 0 112 0 1 14
+node "GND" 130 309.233 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35560 1348 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 127 170.655 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18576 964 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 295 464.724 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42548 2112 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 437 361.439 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16584 812 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_156_432#" 3455 23.436 156 432 nw 0 0 0 0 7812 376 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_106_758#" 10767 24.624 106 758 nw 0 0 0 0 8208 528 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n100_420#" 345100 2.436 -100 420 nw 0 0 0 0 812 816 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "GND" "Vin" 26.7649
+cap "w_156_432#" "Vin" 37.93
+cap "GND" "Vout" 17.0696
+cap "VDD" "Vin" 14.9802
+cap "w_156_432#" "Vout" 26.4893
+cap "Vout" "Vin" 114.025
+cap "w_n100_420#" "Vin" 0.41
+cap "VDD" "Vout" 20.2327
+cap "VDD" "w_106_758#" 7.5924
+cap "pmos_2uf2_0/a_n33_n100#" "nmos_1u_0/a_n112_74#" 5.34286
+cap "pmos_2uf2_0/a_n63_n130#" "nmos_1u_0/a_n112_74#" 180.654
+cap "pmos_2uf2_0/w_n317_n202#" "nmos_1u_0/a_n112_74#" 23.3428
+cap "pmos_2uf2_0/w_n317_n202#" "pmos_2uf2_0/a_n33_n100#" 81.4607
+cap "pmos_2uf2_0/w_n317_n202#" "pmos_2uf2_0/a_n63_n130#" 156.497
+merge "nmos_1u_0/a_n112_74#" "GND" -28.0678 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1064 -180 0 0 0 0 0 0 0 0 0 0 0 0
+merge "GND" "pmos_2uf2_0/VSUBS"
+merge "pmos_2uf2_0/VSUBS" "VSUBS"
+merge "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" "pmos_2uf2_0/a_n33_n100#" -98.7705 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -952 -192 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/a_n33_n100#" "Vout"
+merge "pmos_2uf2_0/a_63_n100#" "pmos_2uf2_0/w_n317_n202#" -280.232 0 0 0 0 -16020 -1716 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4692 -412 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/w_n317_n202#" "VDD"
+merge "VDD" "w_156_432#"
+merge "w_156_432#" "w_106_758#"
+merge "w_106_758#" "w_n100_420#"
+merge "nmos_1u_0/sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n33_n157#" "pmos_2uf2_0/a_33_n130#" -210.176 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1320 -268 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "pmos_2uf2_0/a_33_n130#" "pmos_2uf2_0/a_n63_n130#"
+merge "pmos_2uf2_0/a_n63_n130#" "Vin"
diff --git a/mag/myinv_layout2/inv_W1.mag b/mag/myinv_layout2/inv_W1.mag
new file mode 100755
index 0000000..0fa9a17
--- /dev/null
+++ b/mag/myinv_layout2/inv_W1.mag
@@ -0,0 +1,49 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645263751
+<< nwell >>
+rect -100 420 -98 826
+rect 106 758 334 794
+rect 156 432 282 494
+<< poly >>
+rect 156 466 282 506
+rect 156 436 190 466
+rect 84 416 190 436
+rect 84 370 100 416
+rect 150 370 190 416
+rect 84 352 190 370
+rect 160 298 190 352
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 794 140 828
+rect 106 758 334 794
+rect 106 578 140 758
+rect 298 684 334 758
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 556
+rect 202 364 388 420
+rect 202 260 236 364
+rect 6 -20 82 114
+rect -100 -72 388 -20
+use nmos_1u nmos_1u_0
+timestamp 1644925353
+transform 1 0 112 0 1 14
+box -112 -14 136 300
+use pmos_2uf2 pmos_2uf2_0
+timestamp 1645079724
+transform 1 0 219 0 1 622
+box -317 -202 169 204
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 854 -100 854 7 VDD
+rlabel locali -100 -46 -100 -46 7 GND
+<< end >>
diff --git a/mag/myinv_layout2/inv_W1.spice b/mag/myinv_layout2/inv_W1.spice
new file mode 100755
index 0000000..2a48770
--- /dev/null
+++ b/mag/myinv_layout2/inv_W1.spice
@@ -0,0 +1,40 @@
+* SPICE3 file created from inv_W1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+Vdd Vdd gnd 1.8
+Vin Vin gnd 0
+
+.control
+dc Vin 0 1.8 0.01
+plot Vin Vout
+save all
+write PLS_INV1.raw
+.endc
+
+**** end user architecture code
+* Top level circuit inv_W1
+
+Xnmos_1u_0 gnd Vout Vin nmos_1u
+Xpmos_2uf2_0 Vdd Vin Vdd Vout Vin gnd pmos_2uf2
+.end
+
diff --git a/mag/myinv_layout2/inv_W16.ext b/mag/myinv_layout2/inv_W16.ext
new file mode 100755
index 0000000..f7c7033
--- /dev/null
+++ b/mag/myinv_layout2/inv_W16.ext
@@ -0,0 +1,141 @@
+timestamp 1646325283
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_3M44SC sky130_fd_pr__pfet_01v8_3M44SC_0 1 0 1587 0 1 700
+use sky130_fd_pr__nfet_01v8_VJWT33 sky130_fd_pr__nfet_01v8_VJWT33_0 1 0 1205 0 1 242
+node "li_n14_0#" 751 1488.16 -14 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 166504 6508 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_128_546#" 1950 2770.04 128 546 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255720 12868 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n14_902#" 1454 1915.55 -14 902 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 253448 11084 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_468_358#" 214 496.36 468 358 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27648 688 0 0 32192 1292 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_82_816#" 3150 1218.38 82 816 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 138276 6104 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_598_546#" 77300 157.692 598 546 nw 0 0 0 0 52564 3160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_82_814#" 111091 414.828 82 814 nw 0 0 0 0 138276 6104 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_128_546#" "w_598_546#" 48.6217
+cap "li_n14_902#" "a_468_358#" 13.4357
+cap "li_n14_902#" "w_82_814#" 283.954
+cap "li_n14_902#" "li_128_546#" 310.984
+cap "a_468_358#" "li_n14_0#" 50.7778
+cap "li_n14_902#" "a_82_816#" 562.917
+cap "li_128_546#" "li_n14_0#" 272.424
+cap "li_128_546#" "a_468_358#" 425.592
+cap "a_468_358#" "a_82_816#" 12.1653
+cap "w_82_814#" "a_82_816#" 826.65
+cap "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 155.797
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 29.6436
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" 31.9355
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 7.08629
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" 7.90745
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" 51.8165
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 166.618
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" 151.576
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" 163.354
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" 13.4786
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 553.099
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" 89.65
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 194.847
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#" 154.243
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#" 37.1376
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 143.63
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 463.472
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" 110.965
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" 96.875
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 197.821
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" 19.5829
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" -52.725
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" -225.775
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_801_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" -95.425
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 19.6471
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" 92.39
+cap "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 74.2228
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_639_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1407_n100#" -1832.37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12172 -2084 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1407_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1215_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1215_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1023_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1023_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_831_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_639_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_639_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_447_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_447_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_255_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_255_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_447_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_447_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_63_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_255_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_255_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n129_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n321_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n321_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_63_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_63_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n321_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n321_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n705_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n897_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n897_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1089_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1089_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1281_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1281_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "li_128_546#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/VSUBS" "sky130_fd_pr__pfet_01v8_3M44SC_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1503_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1311_n100#" -821.67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13020 -1516 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1311_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1119_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1119_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_735_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_735_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_543_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_543_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_351_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_351_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_159_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n225_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n225_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n609_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n609_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n801_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n801_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n993_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n993_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1185_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1185_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1377_n100#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1377_n100#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1565_n74#" "li_n14_902#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1473_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1377_n128#" -530.201 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21792 -2980 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1377_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1281_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1281_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1185_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1185_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1089_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_1089_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_993_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_993_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_897_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_897_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_801_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_801_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_705_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_705_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_609_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_609_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_513_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_513_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_417_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_417_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_321_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_321_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_225_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_225_n128#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_129_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_129_n126#" "a_468_358#"
+merge "a_468_358#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_33_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_33_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n63_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n63_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n159_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n159_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n255_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n255_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n351_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n351_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n447_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n447_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n639_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n639_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n735_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n735_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n831_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n831_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n927_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n927_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1023_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1023_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1119_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1119_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1215_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1215_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1311_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1311_n128#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1407_n126#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1407_n126#" "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1503_n128#" "a_82_816#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_735_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_543_n100#" -410.172 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13040 -1948 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_543_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_351_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_351_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_159_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_159_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n225_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n417_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n417_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n609_n100#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n609_n100#" "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#"
+merge "sky130_fd_pr__nfet_01v8_VJWT33_0/a_n797_n74#" "li_n14_0#"
+merge "sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "w_598_546#" -472.248 0 0 0 0 -157416 -9264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "w_598_546#" "w_82_814#"
diff --git a/mag/myinv_layout2/inv_W16.mag b/mag/myinv_layout2/inv_W16.mag
new file mode 100755
index 0000000..2bc4e67
--- /dev/null
+++ b/mag/myinv_layout2/inv_W16.mag
@@ -0,0 +1,83 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646325283
+<< nwell >>
+rect 82 814 3088 860
+rect 706 580 740 630
+rect 898 580 932 626
+rect 1090 580 1124 630
+rect 1282 580 1316 626
+rect 1474 580 1508 628
+rect 1666 580 1700 626
+rect 598 546 1858 580
+<< poly >>
+rect 82 816 3088 862
+rect 468 490 596 574
+rect 468 436 498 490
+rect 560 436 596 490
+rect 468 358 596 436
+<< polycont >>
+rect 498 436 560 490
+<< locali >>
+rect -14 902 3188 954
+rect 32 770 70 902
+rect 224 770 262 902
+rect 416 770 454 902
+rect 608 768 646 902
+rect 800 766 838 902
+rect 992 768 1030 902
+rect 1186 770 1224 902
+rect 1376 766 1414 902
+rect 1568 768 1606 902
+rect 1760 766 1798 902
+rect 1954 768 1992 902
+rect 2146 768 2184 902
+rect 2336 766 2374 902
+rect 2528 760 2566 902
+rect 2720 766 2758 902
+rect 2912 768 2950 902
+rect 3104 768 3142 902
+rect 130 580 164 628
+rect 322 580 356 630
+rect 514 580 548 626
+rect 706 580 740 630
+rect 898 580 932 626
+rect 1090 580 1124 630
+rect 1282 580 1316 626
+rect 1474 580 1508 628
+rect 1666 580 1700 626
+rect 1858 580 1892 628
+rect 2050 580 2084 632
+rect 128 546 2084 580
+rect 2050 494 2084 546
+rect 1944 492 2084 494
+rect 2242 492 2276 634
+rect 2434 492 2468 632
+rect 2626 492 2660 630
+rect 2818 492 2852 628
+rect 3010 492 3044 632
+rect -14 436 498 490
+rect 560 436 576 490
+rect 1944 436 3188 492
+rect -14 434 152 436
+rect 1944 390 2062 436
+rect 512 354 2062 390
+rect 514 314 552 354
+rect 706 300 744 354
+rect 900 304 938 354
+rect 1090 302 1128 354
+rect 1282 308 1320 354
+rect 1476 304 1514 354
+rect 1666 308 1704 354
+rect 1858 308 1896 354
+rect -14 0 3188 52
+use sky130_fd_pr__nfet_01v8_VJWT33 sky130_fd_pr__nfet_01v8_VJWT33_0
+timestamp 1646295505
+transform 1 0 1205 0 1 242
+box -797 -218 797 138
+use sky130_fd_pr__pfet_01v8_3M44SC sky130_fd_pr__pfet_01v8_3M44SC_0
+timestamp 1646261959
+transform 1 0 1587 0 1 700
+box -1601 -200 1601 200
+<< end >>
diff --git a/mag/myinv_layout2/inv_W2.ext b/mag/myinv_layout2/inv_W2.ext
new file mode 100755
index 0000000..8ce7a59
--- /dev/null
+++ b/mag/myinv_layout2/inv_W2.ext
@@ -0,0 +1,51 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0 1 0 141 0 1 654
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 219 0 1 182
+node "GND" 207 364.064 -100 -72 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34556 1620 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vout" 91 169.775 202 260 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15108 760 0 0 0 0 0 0 0 0 0 0 0 0
+node "VDD" 120 244.033 -100 828 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24468 1080 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_156_12#" 127 111.727 156 12 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6048 348 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_252_300#" 56 32.867 252 300 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "Vin" 251 302.04 84 352 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10728 516 0 0 17360 704 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "Vin" "a_252_300#" 9.06061
+cap "a_156_12#" "a_252_300#" 2.875
+cap "a_156_12#" "Vin" 2.89916
+cap "Vout" "Vin" 81.5294
+cap "Vin" "VDD" 7.08611
+cap "Vin" "GND" 24.9623
+cap "Vout" "VDD" 3
+cap "Vout" "GND" 18.672
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 6.10637
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 11.1195
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 12.3374
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 42.0143
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" 30.4523
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 67.2375
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" -7.15
+cap "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" 14.0899
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" -104.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2828 -468 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_225_n726#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n726#" "GND"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_33_n122#" "a_252_300#" -117.03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -540 -336 0 0 -896 -144 0 0 0 0 0 0 0 0 0 0 0 0
+merge "a_252_300#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n122#" "a_156_12#"
+merge "a_156_12#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n159_n152#" "Vin"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_229_174#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" -147.998 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2968 -560 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n221_n74#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_n261_174#" "VDD"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" -76.2649 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2360 -348 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/li_217_n290#" "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" "Vout"
diff --git a/mag/myinv_layout2/inv_W2.mag b/mag/myinv_layout2/inv_W2.mag
new file mode 100755
index 0000000..66c19e1
--- /dev/null
+++ b/mag/myinv_layout2/inv_W2.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< poly >>
+rect 156 436 186 454
+rect 84 416 186 436
+rect 84 370 100 416
+rect 150 370 186 416
+rect 84 352 186 370
+rect 156 298 186 352
+rect 252 300 282 326
+rect 156 12 282 60
+<< polycont >>
+rect 100 370 150 416
+<< locali >>
+rect -100 828 388 878
+rect 106 826 140 828
+rect 84 420 168 436
+rect -100 416 168 420
+rect -100 370 100 416
+rect 150 370 168 416
+rect -100 364 168 370
+rect 84 352 168 364
+rect 202 420 236 454
+rect 202 364 388 420
+rect 202 260 236 364
+rect 106 -20 140 114
+rect 298 -20 332 116
+rect -100 -72 388 -20
+use sky130_fd_pr__nfet_01v8_XJTKXQ sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646324451
+transform 1 0 219 0 1 182
+box -125 -126 125 126
+use sky130_fd_pr__pfet_01v8_AC5Z8B sky130_fd_pr__pfet_01v8_AC5Z8B_0
+timestamp 1646324451
+transform 1 0 141 0 1 654
+box -261 -726 263 224
+<< labels >>
+rlabel locali -100 390 -100 390 7 Vin
+rlabel locali 388 392 388 392 3 Vout
+rlabel locali -100 -46 -100 -46 7 GND
+rlabel locali -100 854 -100 854 7 VDD
+<< end >>
diff --git a/mag/myinv_layout2/inv_W8.ext b/mag/myinv_layout2/inv_W8.ext
new file mode 100755
index 0000000..d9d0f4c
--- /dev/null
+++ b/mag/myinv_layout2/inv_W8.ext
@@ -0,0 +1,88 @@
+timestamp 1646325197
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RL4NCG sky130_fd_pr__pfet_01v8_RL4NCG_0 1 0 1203 0 1 700
+use sky130_fd_pr__nfet_01v8_KZU588 sky130_fd_pr__nfet_01v8_KZU588_0 1 0 1207 0 1 240
+node "li_354_0#" 593 1060.48 354 0 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108388 4684 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_512_546#" 863 631.918 512 546 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 140104 6384 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_354_902#" 770 236.98 354 902 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134096 5912 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_804_430#" 376 362.728 804 430 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12672 616 0 0 28836 1176 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_466_816#" 1544 179.681 466 816 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67804 3040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_354_500#" 6351 2309.95 354 500 nw 0 0 0 0 769984 4300 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_804_430#" "w_354_500#" 58.3
+cap "w_354_500#" "a_466_816#" 836
+cap "a_804_430#" "a_466_816#" 7.54446
+cap "w_354_500#" "li_354_902#" 955.68
+cap "a_466_816#" "li_354_902#" 262.695
+cap "a_804_430#" "li_354_902#" 13.5328
+cap "w_354_500#" "li_512_546#" 786.974
+cap "a_804_430#" "li_512_546#" 256.467
+cap "a_804_430#" "li_354_0#" 47.1553
+cap "li_512_546#" "li_354_902#" 185.517
+cap "li_354_0#" "li_512_546#" 141.711
+cap "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 132.841
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" -346.5
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" 13.3917
+cap "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" 106.409
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" 282.814
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" -134.154
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" -121.474
+cap "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" 46.5714
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" 167.333
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "w_354_500#" -17.5026
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#" 14.114
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#" "w_354_500#" -46.2
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#" 35.0677
+cap "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#" "w_354_500#" -39.2199
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_351_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_159_n100#" -153.624 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 -428 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_159_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n33_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n225_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n225_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n413_n74#" "li_354_0#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/VSUBS" "sky130_fd_pr__pfet_01v8_RL4NCG_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n353_n162#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_705_n126#" -0.161601 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8656 -1512 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_705_n126#" "a_804_430#"
+merge "a_804_430#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_609_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_609_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_513_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_513_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_417_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_417_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_321_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_321_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_225_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_129_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_129_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_33_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_33_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n63_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n63_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n159_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n159_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n255_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n255_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n351_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n351_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n447_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n447_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n543_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n543_n128#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n639_n126#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n639_n126#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n735_n128#" "a_466_816#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_255_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_63_n100#" -246.038 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5360 -1108 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n321_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n321_n100#" "sky130_fd_pr__nfet_01v8_KZU588_0/li_321_116#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/li_321_116#" "sky130_fd_pr__nfet_01v8_KZU588_0/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_KZU588_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_639_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_639_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_447_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_447_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_255_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_63_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_63_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n129_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n321_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n321_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n513_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n513_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "li_512_546#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_735_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_543_n100#" -26.0875 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4572 -796 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_543_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_351_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_351_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_159_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n33_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n225_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n225_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n417_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n417_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n609_n100#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n609_n100#" "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n797_n74#" "li_354_902#"
+merge "sky130_fd_pr__pfet_01v8_RL4NCG_0/w_n833_n200#" "w_354_500#" -2380.46 0 0 0 0 -793488 -5178 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/myinv_layout2/inv_W8.mag b/mag/myinv_layout2/inv_W8.mag
new file mode 100755
index 0000000..e2886a7
--- /dev/null
+++ b/mag/myinv_layout2/inv_W8.mag
@@ -0,0 +1,63 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646325197
+<< nwell >>
+rect 354 500 2050 954
+<< poly >>
+rect 466 816 1940 862
+rect 848 498 892 584
+rect 804 482 892 498
+rect 804 446 820 482
+rect 856 446 892 482
+rect 804 430 892 446
+rect 848 364 892 430
+<< polycont >>
+rect 820 446 856 482
+<< locali >>
+rect 354 902 2050 954
+rect 416 770 454 902
+rect 608 768 646 902
+rect 800 766 838 902
+rect 992 768 1030 902
+rect 1186 770 1224 902
+rect 1376 766 1414 902
+rect 1568 768 1606 902
+rect 1760 766 1798 902
+rect 1954 768 1992 902
+rect 514 580 548 626
+rect 706 580 740 630
+rect 898 580 932 626
+rect 1090 580 1124 630
+rect 1282 580 1316 626
+rect 1474 580 1508 628
+rect 1666 580 1700 626
+rect 1858 580 1892 628
+rect 512 546 1898 580
+rect 1516 492 1664 546
+rect 354 482 888 490
+rect 354 446 820 482
+rect 856 446 888 482
+rect 354 436 888 446
+rect 1516 436 2050 492
+rect 1516 390 1668 436
+rect 900 354 1668 390
+rect 900 304 938 354
+rect 1090 302 1128 354
+rect 1282 308 1320 354
+rect 1476 304 1514 354
+rect 806 52 840 168
+rect 998 52 1032 174
+rect 1190 52 1224 168
+rect 1382 52 1416 174
+rect 1574 52 1608 170
+rect 354 0 2050 52
+use sky130_fd_pr__nfet_01v8_KZU588 sky130_fd_pr__nfet_01v8_KZU588_0
+timestamp 1646318752
+transform 1 0 1207 0 1 240
+box -413 -162 413 150
+use sky130_fd_pr__pfet_01v8_RL4NCG sky130_fd_pr__pfet_01v8_RL4NCG_0
+timestamp 1646319668
+transform 1 0 1203 0 1 700
+box -833 -200 833 200
+<< end >>
diff --git a/mag/myinv_layout2/nmos_1u.ext b/mag/myinv_layout2/nmos_1u.ext
new file mode 100755
index 0000000..3f1ba5f
--- /dev/null
+++ b/mag/myinv_layout2/nmos_1u.ext
@@ -0,0 +1,16 @@
+timestamp 1644925353
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__nfet_01v8_7RYEVP sky130_fd_pr__nfet_01v8_7RYEVP_0 1 0 63 0 1 143
+node "m1_n86_2#" 1 92.5822 -86 2 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6188 432 0 0 0 0 0 0 0 0 0 0
+node "a_n12_74#" 12000 1.1456 -12 74 ndif 0 0 0 0 0 0 0 0 400 404 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "a_n112_74#" 0 0 -112 74 ppd 0 0 0 0 0 0 0 0 0 0 20000 600 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19008 568 0 0 0 0 0 0 0 0 0 0 0 0
+cap "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n33_n157#" "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" 45
+cap "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n33_n157#" "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#" 4.73684
+merge "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n33_n157#" "m1_n86_2#" -14.5786 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1972 -184 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS" "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" -79.0336 0 0 0 0 0 0 0 0 0 -400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -352 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_7RYEVP_0/a_n73_n69#" "a_n112_74#"
+merge "a_n112_74#" "a_n12_74#"
diff --git a/mag/myinv_layout2/nmos_1u.mag b/mag/myinv_layout2/nmos_1u.mag
new file mode 100755
index 0000000..8c56f86
--- /dev/null
+++ b/mag/myinv_layout2/nmos_1u.mag
@@ -0,0 +1,25 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644925353
+<< ndiff >>
+rect -12 74 -10 274
+<< psubdiff >>
+rect -112 236 -12 274
+rect -112 112 -90 236
+rect -56 112 -12 236
+rect -112 74 -12 112
+<< psubdiffcont >>
+rect -90 112 -56 236
+<< locali >>
+rect -106 236 2 262
+rect -106 112 -90 236
+rect -56 112 2 236
+rect -106 86 2 112
+<< metal1 >>
+rect -86 2 96 36
+use sky130_fd_pr__nfet_01v8_7RYEVP sky130_fd_pr__nfet_01v8_7RYEVP_0 ~/my_sky130_project/mag/myinv_layout2
+timestamp 1644925353
+transform 1 0 63 0 1 143
+box -73 -157 73 157
+<< end >>
diff --git a/mag/myinv_layout2/pmos_2u.mag b/mag/myinv_layout2/pmos_2u.mag
new file mode 100755
index 0000000..28c9b08
--- /dev/null
+++ b/mag/myinv_layout2/pmos_2u.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645075726
+<< error_s >>
+rect 890 113 948 119
+rect 890 79 902 113
+rect 890 73 948 79
+<< nwell >>
+rect -156 418 314 800
+<< pmos >>
+rect 46 480 76 680
+rect 134 480 164 680
+<< pdiff >>
+rect -20 644 46 680
+rect -20 520 0 644
+rect 34 520 46 644
+rect -20 480 46 520
+rect 76 644 134 680
+rect 76 520 88 644
+rect 122 520 134 644
+rect 76 480 134 520
+rect 164 644 222 680
+rect 164 520 176 644
+rect 210 520 222 644
+rect 164 480 222 520
+<< pdiffc >>
+rect 0 520 34 644
+rect 88 520 122 644
+rect 176 520 210 644
+<< nsubdiff >>
+rect -114 644 -20 680
+rect -114 520 -78 644
+rect -44 520 -20 644
+rect -114 480 -20 520
+<< nsubdiffcont >>
+rect -78 520 -44 644
+<< poly >>
+rect 46 680 76 730
+rect 134 680 164 730
+rect 46 428 76 480
+rect 134 428 164 480
+<< locali >>
+rect -106 644 40 680
+rect -106 520 -78 644
+rect -44 520 0 644
+rect 34 520 40 644
+rect -106 482 40 520
+rect -6 480 40 482
+rect 82 644 128 680
+rect 82 520 88 644
+rect 122 520 128 644
+rect 82 480 128 520
+rect 170 644 216 680
+rect 170 520 176 644
+rect 210 520 216 644
+rect 170 480 216 520
+use pmos_2uf2 sky130_fd_pr__pfet_01v8_SBMASV_0
+timestamp 1645025748
+transform 1 0 871 0 1 -68
+box -317 -202 169 204
+use sky130_fd_pr__pfet_01v8_U9MAPM sky130_fd_pr__pfet_01v8_U9MAPM_0
+timestamp 1645025748
+transform 1 0 1355 0 1 -78
+box 0 0 1 1
+<< end >>
diff --git a/mag/myinv_layout2/pmos_2uf2.ext b/mag/myinv_layout2/pmos_2uf2.ext
new file mode 100755
index 0000000..2207d63
--- /dev/null
+++ b/mag/myinv_layout2/pmos_2uf2.ext
@@ -0,0 +1,21 @@
+timestamp 1645079724
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 712 -156.62 63 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 5152 316 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 653 -77.9 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_33_n130#" 411 4.452 33 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n130#" 411 4.452 -63 -130 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n317_n202#" 2861 369.728 -317 -202 nw 0 0 0 0 197316 1784 0 0 29824 752 15200 552 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36016 840 5152 316 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_63_n100#" "a_n33_n100#" 83.0323
+cap "a_33_n130#" "a_n63_n130#" 19.5152
+cap "w_n317_n202#" "a_33_n130#" 47.3
+cap "w_n317_n202#" "a_n33_n100#" 160.932
+cap "w_n317_n202#" "a_63_n100#" 209.783
+cap "w_n317_n202#" "a_n63_n130#" 47.3
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n317_n202#" "a_33_n130#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n317_n202#" "a_n63_n130#" 60 0 "w_n317_n202#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/myinv_layout2/pmos_2uf2.mag b/mag/myinv_layout2/pmos_2uf2.mag
new file mode 100755
index 0000000..2b1d032
--- /dev/null
+++ b/mag/myinv_layout2/pmos_2uf2.mag
@@ -0,0 +1,66 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645079724
+<< nwell >>
+rect -317 -202 169 204
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -139 62 -63 100
+rect -139 -62 -113 62
+rect -79 -62 -63 62
+rect -139 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< pdiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< nsubdiff >>
+rect -267 100 -179 124
+rect -179 -100 -139 100
+rect -267 -124 -179 -100
+<< nsubdiffcont >>
+rect -267 -100 -179 100
+<< poly >>
+rect -63 100 -33 126
+rect 33 100 63 126
+rect -63 -130 -33 -100
+rect 33 -130 63 -100
+<< locali >>
+rect -267 100 -179 116
+rect -179 62 -79 78
+rect -179 -62 -113 62
+rect -179 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect -267 -116 -179 -100
+<< viali >>
+rect -113 -44 -79 44
+rect 79 -44 113 44
+<< metal1 >>
+rect -119 44 -73 56
+rect -119 -44 -113 44
+rect -79 -44 -73 44
+rect -119 -56 -73 -44
+rect 73 44 119 56
+rect 73 -44 79 44
+rect 113 -44 119 44
+rect 73 -56 119 -44
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 50 viadrn 50 viagate 50 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130A.magicrc b/mag/myinv_layout2/sky130A.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/myinv_layout2/sky130A.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
new file mode 100755
index 0000000..24a493e
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
@@ -0,0 +1,15 @@
+timestamp 1644925353
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n69#" 481 18.86 15 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n69#" 481 18.86 -73 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5984 420 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n157#" 514 144.799 -33 -157 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n69#" "a_15_n69#" 321.841
+cap "a_n73_n69#" "a_n33_n157#" 15.21
+cap "a_n33_n157#" "a_15_n69#" 15.21
+device msubckt sky130_fd_pr__nfet_01v8 -15 -69 -14 -68 l=30 w=200 "VSUBS" "a_n33_n157#" 60 0 "a_n73_n69#" 200 0 "a_15_n69#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.mag
new file mode 100755
index 0000000..c8b66a6
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644925353
+<< error_p >>
+rect -73 -69 -15 131
+rect 15 -69 73 131
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect -29 -147 29 -141
+<< nmos >>
+rect -15 -69 15 131
+<< ndiff >>
+rect -73 93 -15 131
+rect -73 -31 -61 93
+rect -27 -31 -15 93
+rect -73 -69 -15 -31
+rect 15 93 73 131
+rect 15 -31 27 93
+rect 61 -31 73 93
+rect 15 -69 73 -31
+<< ndiffc >>
+rect -61 -31 -27 93
+rect 27 -31 61 93
+<< poly >>
+rect -15 131 15 157
+rect -15 -91 15 -69
+rect -33 -107 33 -91
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+rect -33 -157 33 -141
+<< polycont >>
+rect -17 -141 17 -107
+<< locali >>
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+<< viali >>
+rect -61 93 -27 119
+rect -61 -31 -27 93
+rect -61 -57 -27 -31
+rect 27 93 61 119
+rect 27 -31 61 93
+rect 27 -57 61 -31
+rect -17 -141 17 -107
+<< metal1 >>
+rect -67 119 -21 131
+rect -67 -57 -61 119
+rect -27 -57 -21 119
+rect -67 -69 -21 -57
+rect 21 119 67 131
+rect 21 -57 27 119
+rect 61 -57 67 119
+rect 21 -69 67 -57
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect 17 -141 29 -107
+rect -29 -147 29 -141
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_8P2286.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_8P2286.mag
new file mode 100755
index 0000000..4f08242
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_8P2286.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< error_p >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 19 232 77 238
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -77 -278 -19 -272
+<< nmos >>
+rect -63 -200 -33 200
+rect 33 -200 63 200
+<< ndiff >>
+rect -121 144 -63 200
+rect -125 132 -63 144
+rect -125 -132 -113 132
+rect -79 -132 -63 132
+rect -125 -144 -63 -132
+rect -121 -200 -63 -144
+rect -33 132 33 200
+rect -33 -132 -17 132
+rect 17 -132 33 132
+rect -33 -200 33 -132
+rect 63 144 121 200
+rect 63 132 125 144
+rect 63 -132 79 132
+rect 113 -132 125 132
+rect 63 -144 125 -132
+rect 63 -200 121 -144
+<< ndiffc >>
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+<< poly >>
+rect 15 272 81 288
+rect 15 238 31 272
+rect 65 238 81 272
+rect -63 200 -33 226
+rect 15 222 81 238
+rect 33 200 63 222
+rect -63 -222 -33 -200
+rect -81 -238 -15 -222
+rect 33 -226 63 -200
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+rect -81 -288 -15 -272
+<< polycont >>
+rect 31 238 65 272
+rect -65 -272 -31 -238
+<< locali >>
+rect 15 238 31 272
+rect 65 238 81 272
+rect -113 132 -79 148
+rect -113 -148 -79 -132
+rect -17 132 17 148
+rect -17 -148 17 -132
+rect 79 132 113 148
+rect 79 -148 113 -132
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+<< viali >>
+rect 31 238 65 272
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect -65 -272 -31 -238
+<< metal1 >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 65 238 77 272
+rect 19 232 77 238
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -31 -272 -19 -238
+rect -77 -278 -19 -272
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_A2RL69.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_A2RL69.mag
new file mode 100755
index 0000000..0a0b357
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_A2RL69.mag
@@ -0,0 +1,90 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< error_p >>
+rect 19 172 77 178
+rect 19 138 31 172
+rect 19 132 77 138
+rect -77 -138 -19 -132
+rect -77 -172 -65 -138
+rect -77 -178 -19 -172
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -125 88 -63 100
+rect -125 -88 -113 88
+rect -79 -88 -63 88
+rect -125 -100 -63 -88
+rect -33 88 33 100
+rect -33 -88 -17 88
+rect 17 -88 33 88
+rect -33 -100 33 -88
+rect 63 88 125 100
+rect 63 -88 79 88
+rect 113 -88 125 88
+rect 63 -100 125 -88
+<< ndiffc >>
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+<< poly >>
+rect 15 172 81 188
+rect 15 138 31 172
+rect 65 138 81 172
+rect -63 100 -33 126
+rect 15 122 81 138
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect -81 -138 -15 -122
+rect 33 -126 63 -100
+rect -81 -172 -65 -138
+rect -31 -172 -15 -138
+rect -81 -188 -15 -172
+<< polycont >>
+rect 31 138 65 172
+rect -65 -172 -31 -138
+<< locali >>
+rect 15 138 31 172
+rect 65 138 81 172
+rect -113 88 -79 104
+rect -113 -104 -79 -88
+rect -17 88 17 104
+rect -17 -104 17 -88
+rect 79 88 113 104
+rect 79 -104 113 -88
+rect -81 -172 -65 -138
+rect -31 -172 -15 -138
+<< viali >>
+rect 31 138 65 172
+rect -113 -88 -79 88
+rect -17 -88 17 88
+rect 79 -88 113 88
+rect -65 -172 -31 -138
+<< metal1 >>
+rect 19 172 77 178
+rect 19 138 31 172
+rect 65 138 77 172
+rect 19 132 77 138
+rect -119 88 -73 100
+rect -119 -88 -113 88
+rect -79 -88 -73 88
+rect -119 -100 -73 -88
+rect -23 88 23 100
+rect -23 -88 -17 88
+rect 17 -88 23 88
+rect -23 -100 23 -88
+rect 73 88 119 100
+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
+rect -77 -138 -19 -132
+rect -77 -172 -65 -138
+rect -31 -172 -19 -138
+rect -77 -178 -19 -172
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_CJHXAH.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_CJHXAH.mag
new file mode 100755
index 0000000..4e90e0a
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_CJHXAH.mag
@@ -0,0 +1,119 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< error_p >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 19 232 77 238
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -77 -278 -19 -272
+<< pwell >>
+rect -263 -410 263 410
+<< nmos >>
+rect -63 -200 -33 200
+rect 33 -200 63 200
+<< ndiff >>
+rect -121 144 -63 200
+rect -125 132 -63 144
+rect -125 -132 -113 132
+rect -79 -132 -63 132
+rect -125 -144 -63 -132
+rect -121 -200 -63 -144
+rect -33 132 33 200
+rect -33 -132 -17 132
+rect 17 -132 33 132
+rect -33 -200 33 -132
+rect 63 144 121 200
+rect 63 132 125 144
+rect 63 -132 79 132
+rect 113 -132 125 132
+rect 63 -144 125 -132
+rect 63 -200 121 -144
+<< ndiffc >>
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+<< psubdiff >>
+rect -227 340 -92 374
+rect 92 340 227 374
+rect -227 195 -193 340
+rect -227 -340 -193 -195
+rect 193 195 227 340
+rect 193 -340 227 -195
+rect -227 -374 -92 -340
+rect 92 -374 227 -340
+<< psubdiffcont >>
+rect -92 340 92 374
+rect -227 -195 -193 195
+rect 193 -195 227 195
+rect -92 -374 92 -340
+<< poly >>
+rect 15 272 81 288
+rect 15 238 31 272
+rect 65 238 81 272
+rect -63 200 -33 226
+rect 15 222 81 238
+rect 33 200 63 222
+rect -63 -222 -33 -200
+rect -81 -238 -15 -222
+rect 33 -226 63 -200
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+rect -81 -288 -15 -272
+<< polycont >>
+rect 31 238 65 272
+rect -65 -272 -31 -238
+<< locali >>
+rect -227 340 -92 374
+rect 92 340 227 374
+rect -227 195 -193 340
+rect 15 238 31 272
+rect 65 238 81 272
+rect 193 195 227 340
+rect -113 132 -79 148
+rect -113 -148 -79 -132
+rect -17 132 17 148
+rect -17 -148 17 -132
+rect 79 132 113 148
+rect 79 -148 113 -132
+rect -227 -340 -193 -195
+rect -81 -272 -65 -238
+rect -31 -272 -15 -238
+rect 193 -340 227 -195
+rect -227 -374 -92 -340
+rect 92 -374 227 -340
+<< viali >>
+rect 31 238 65 272
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect -65 -272 -31 -238
+<< metal1 >>
+rect 19 272 77 278
+rect 19 238 31 272
+rect 65 238 77 272
+rect 19 232 77 238
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect -77 -238 -19 -232
+rect -77 -272 -65 -238
+rect -31 -272 -19 -238
+rect -77 -278 -19 -272
+<< properties >>
+string FIXED_BBOX -210 -357 210 357
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 1 glc 1 grc 1 gtc 1 gbc 1 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 1 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
new file mode 100755
index 0000000..f01472d
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
@@ -0,0 +1,54 @@
+timestamp 1646318752
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_321_116#" 20 13.53 321 116 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 540 96 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 456 -13.94 351 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 420 -13.94 255 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 420 -13.94 159 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 420 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 420 -13.94 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 420 -13.94 -225 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n321_n100#" 420 -13.94 -321 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n413_n74#" 456 -13.94 -413 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n353_n162#" 4022 764.376 -353 -162 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 90708 5568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_159_n100#" "a_255_n100#" 216.232
+cap "a_255_n100#" "a_351_n100#" 216.232
+cap "a_159_n100#" "a_351_n100#" 78.1987
+cap "a_255_n100#" "a_63_n100#" 78.1987
+cap "a_159_n100#" "a_63_n100#" 216.232
+cap "a_351_n100#" "a_63_n100#" 47.7884
+cap "a_n225_n100#" "a_159_n100#" 34.4127
+cap "a_n129_n100#" "a_159_n100#" 47.7884
+cap "a_255_n100#" "a_n33_n100#" 47.7884
+cap "a_159_n100#" "a_n33_n100#" 78.1987
+cap "a_n129_n100#" "a_255_n100#" 34.4127
+cap "a_n225_n100#" "a_63_n100#" 47.7884
+cap "a_n321_n100#" "a_63_n100#" 34.4127
+cap "a_351_n100#" "a_n33_n100#" 34.4127
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n129_n100#" "a_63_n100#" 78.1987
+cap "a_n225_n100#" "a_n321_n100#" 216.232
+cap "a_n225_n100#" "a_n33_n100#" 78.1987
+cap "a_n129_n100#" "a_n225_n100#" 216.232
+cap "a_n33_n100#" "a_n321_n100#" 47.7884
+cap "a_n129_n100#" "a_n321_n100#" 78.1987
+cap "a_n129_n100#" "a_n33_n100#" 216.232
+cap "li_321_116#" "a_n353_n162#" 9.069
+cap "a_n413_n74#" "a_n321_n100#" 216.232
+cap "a_n225_n100#" "a_n413_n74#" 78.1987
+cap "a_n129_n100#" "a_n413_n74#" 47.7884
+cap "a_n413_n74#" "a_n33_n100#" 34.4127
+device msubckt sky130_fd_pr__nfet_01v8 321 -100 322 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 225 -100 226 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 129 -100 130 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -159 -100 -158 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -255 -100 -254 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -351 -100 -350 -99 l=30 w=200 "VSUBS" "a_n353_n162#" 60 0 "a_n413_n74#" 200 0 "a_n321_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.mag
new file mode 100755
index 0000000..b7232f5
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.mag
@@ -0,0 +1,157 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646318752
+<< error_p >>
+rect 321 134 351 150
+rect 321 116 355 134
+<< nmos >>
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+<< ndiff >>
+rect -409 74 -351 100
+rect -413 62 -351 74
+rect -413 -62 -401 62
+rect -367 -62 -351 62
+rect -413 -74 -351 -62
+rect -409 -100 -351 -74
+rect -321 62 -255 100
+rect -321 -62 -305 62
+rect -271 -62 -255 62
+rect -321 -100 -255 -62
+rect -225 62 -159 100
+rect -225 -62 -209 62
+rect -175 -62 -159 62
+rect -225 -100 -159 -62
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 62 225 100
+rect 159 -62 175 62
+rect 209 -62 225 62
+rect 159 -100 225 -62
+rect 255 62 321 100
+rect 255 -62 271 62
+rect 305 -62 321 62
+rect 255 -100 321 -62
+rect 351 74 409 100
+rect 351 62 413 74
+rect 351 -62 367 62
+rect 401 -62 413 62
+rect 351 -74 413 -62
+rect 351 -100 409 -74
+<< ndiffc >>
+rect -401 -62 -367 62
+rect -305 -62 -271 62
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+rect 271 -62 305 62
+rect 367 -62 401 62
+<< poly >>
+rect -351 100 -321 136
+rect -255 100 -225 136
+rect -159 100 -129 134
+rect -63 100 -33 134
+rect 33 100 63 134
+rect 129 100 159 134
+rect 225 100 255 136
+rect 321 100 351 134
+rect -351 -120 -321 -100
+rect -255 -120 -225 -100
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect 225 -120 255 -100
+rect 321 -120 351 -100
+rect -353 -162 351 -120
+<< locali >>
+rect 321 116 351 134
+rect -401 62 -367 78
+rect -401 -78 -367 -62
+rect -305 62 -271 78
+rect -305 -78 -271 -62
+rect -209 62 -175 78
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect 175 62 209 78
+rect 175 -78 209 -62
+rect 271 62 305 78
+rect 271 -78 305 -62
+rect 367 62 401 78
+rect 367 -78 401 -62
+<< viali >>
+rect -401 -62 -367 62
+rect -305 -62 -271 62
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+rect 271 -62 305 62
+rect 367 -62 401 62
+<< metal1 >>
+rect -407 62 -361 74
+rect -407 -62 -401 62
+rect -367 -62 -361 62
+rect -407 -74 -361 -62
+rect -311 62 -265 74
+rect -311 -62 -305 62
+rect -271 -62 -265 62
+rect -311 -74 -265 -62
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+rect 265 62 311 74
+rect 265 -62 271 62
+rect 305 -62 311 62
+rect 265 -74 311 -62
+rect 361 62 407 74
+rect 361 -62 367 62
+rect 401 -62 407 62
+rect 361 -74 407 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 8 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
new file mode 100755
index 0000000..b0142d4
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
@@ -0,0 +1,15 @@
+timestamp 0
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n69#" 489 22.3916 15 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n69#" 489 22.3916 -73 -69 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7072 484 9200 492 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n157#" 513 114.359 -33 -157 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11796 760 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n69#" "a_15_n69#" 341.397
+cap "a_n33_n157#" "a_15_n69#" 17.0735
+cap "a_n73_n69#" "a_n33_n157#" 17.0735
+device msubckt sky130_fd_pr__nfet_01v8 -15 -69 -14 -68 l=30 w=200 "VSUBS" "a_n33_n157#" 60 0 "a_n73_n69#" 200 0 "a_15_n69#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.mag
new file mode 100755
index 0000000..30b7f23
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.mag
@@ -0,0 +1,60 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644851365
+<< error_p >>
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect -29 -147 29 -141
+<< nmos >>
+rect -15 -69 15 131
+<< ndiff >>
+rect -73 119 -15 131
+rect -73 -57 -61 119
+rect -27 -57 -15 119
+rect -73 -69 -15 -57
+rect 15 119 73 131
+rect 15 -57 27 119
+rect 61 -57 73 119
+rect 15 -69 73 -57
+<< ndiffc >>
+rect -61 -57 -27 119
+rect 27 -57 61 119
+<< poly >>
+rect -15 131 15 157
+rect -15 -91 15 -69
+rect -33 -107 33 -91
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+rect -33 -157 33 -141
+<< polycont >>
+rect -17 -141 17 -107
+<< locali >>
+rect -61 119 -27 135
+rect -61 -73 -27 -57
+rect 27 119 61 135
+rect 27 -73 61 -57
+rect -33 -141 -17 -107
+rect 17 -141 33 -107
+<< viali >>
+rect -61 -57 -27 119
+rect 27 -57 61 119
+rect -17 -141 17 -107
+<< metal1 >>
+rect -67 119 -21 131
+rect -67 -57 -61 119
+rect -27 -57 -21 119
+rect -67 -69 -21 -57
+rect 21 119 67 131
+rect 21 -57 27 119
+rect 61 -57 67 119
+rect 21 -69 67 -57
+rect -29 -107 29 -101
+rect -29 -141 -17 -107
+rect 17 -141 29 -107
+rect -29 -147 29 -141
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ7V57.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ7V57.mag
new file mode 100755
index 0000000..92bd77e
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ7V57.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646248588
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 88 -15 100
+rect -73 -88 -61 88
+rect -27 -88 -15 88
+rect -73 -100 -15 -88
+rect 15 88 73 100
+rect 15 -88 27 88
+rect 61 -88 73 88
+rect 15 -100 73 -88
+<< ndiffc >>
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+rect 27 -88 61 88
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
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+rect -61 -104 -27 -88
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+<< viali >>
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+<< metal1 >>
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+rect -67 -100 -21 -88
+rect 21 88 67 100
+rect 21 -88 27 88
+rect 61 -88 67 88
+rect 21 -100 67 -88
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
new file mode 100755
index 0000000..0004cc1
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
@@ -0,0 +1,107 @@
+timestamp 1646295505
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_735_n100#" 495 42.4035 735 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10960 660 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_639_n100#" 420 -13.94 639 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_543_n100#" 457 13.6771 543 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10756 648 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_447_n100#" 420 -13.94 447 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 457 13.6771 351 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10756 648 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 420 -13.94 255 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
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+node "a_63_n100#" 420 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 459 15.4725 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10892 656 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 420 -13.94 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 456 12.7794 -225 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10688 644 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n321_n100#" 420 -13.94 -321 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
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+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_159_n100#" "a_n33_n100#" 106.977
+cap "a_447_n100#" "a_255_n100#" 78.1987
+cap "a_543_n100#" "a_639_n100#" 217.373
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+cap "a_n705_n100#" "a_n513_n100#" 78.1987
+cap "a_n797_n74#" "a_n417_n100#" 47.0941
+cap "a_639_n100#" "a_255_n100#" 34.4127
+cap "a_63_n100#" "a_159_n100#" 216.82
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+cap "a_n797_n74#" "a_n513_n100#" 47.8028
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+cap "a_351_n100#" "a_735_n100#" 46.6114
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+cap "a_n225_n100#" "a_n609_n100#" 46.3995
+cap "a_n129_n100#" "a_63_n100#" 78.1987
+device msubckt sky130_fd_pr__nfet_01v8 705 -100 706 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 609 -100 610 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 513 -100 514 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 417 -100 418 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 321 -100 322 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 225 -100 226 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 129 -100 130 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -159 -100 -158 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -255 -100 -254 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -351 -100 -350 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -447 -100 -446 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -543 -100 -542 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -639 -100 -638 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -735 -100 -734 -99 l=30 w=200 "VSUBS" "a_n735_n176#" 60 0 "a_n797_n74#" 200 0 "a_n705_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.mag
new file mode 100755
index 0000000..a79051d
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.mag
@@ -0,0 +1,283 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646295505
+<< nmos >>
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+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 16 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_W9PLXN.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_W9PLXN.mag
new file mode 100755
index 0000000..8390e40
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_W9PLXN.mag
@@ -0,0 +1,110 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646259600
+<< error_p >>
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+<< nmos >>
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+<< ndiff >>
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+<< ndiffc >>
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+<< poly >>
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+<< locali >>
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+<< viali >>
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+<< metal1 >>
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+rect 169 132 215 144
+rect 169 -132 175 132
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+rect 169 -144 215 -132
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 2 l 0.150 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
new file mode 100755
index 0000000..bc7e422
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
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+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n100#" "a_63_n100#" 216.232
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+cap "a_n125_n74#" "a_63_n100#" 78.1987
+cap "a_33_n122#" "a_n63_n122#" 15.3333
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.mag b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
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+rect 33 -126 63 -122
+<< nmos >>
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+<< ndiffc >>
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+<< poly >>
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+rect 33 -122 63 -100
+<< locali >>
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+<< viali >>
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+<< metal1 >>
+rect -119 62 -73 74
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+rect 73 62 119 74
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+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
new file mode 100755
index 0000000..731757e
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
@@ -0,0 +1,411 @@
+timestamp 1646261959
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
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+node "w_n1601_n200#" 13709 3820.51 -1601 -200 nw 0 0 0 0 1273504 7204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_129_n126#" "w_n1601_n200#" 47.3
+cap "a_n831_n126#" "a_n543_n128#" 4.63566
+cap "a_1119_n100#" "a_1311_n100#" 78.1987
+cap "a_n705_n100#" "a_n321_n100#" 34.4127
+cap "a_1407_n100#" "a_1503_n100#" 216.232
+cap "a_n735_n128#" "a_n447_n126#" 4.63566
+cap "w_n1601_n200#" "a_n417_n100#" 157.44
+cap "a_n735_n128#" "a_n1119_n128#" 3.50847
+cap "a_63_n100#" "a_351_n100#" 47.7884
+cap "w_n1601_n200#" "a_n33_n100#" 157.44
+cap "a_n1473_n100#" "a_n1377_n100#" 216.232
+cap "a_447_n100#" "a_735_n100#" 47.7884
+cap "w_n1601_n200#" "a_n1089_n100#" 157.44
+cap "a_n801_n100#" "a_n417_n100#" 34.4127
+cap "a_n1185_n100#" "a_n1281_n100#" 216.232
+cap "a_n801_n100#" "a_n1089_n100#" 47.7884
+cap "a_225_n128#" "a_609_n128#" 3.50847
+cap "a_n1407_n126#" "a_n1023_n126#" 3.63842
+cap "a_n417_n100#" "a_n33_n100#" 34.4127
+cap "a_n897_n100#" "a_n1281_n100#" 34.4127
+cap "w_n1601_n200#" "a_801_n128#" 46.2
+cap "a_n159_n128#" "a_n447_n126#" 4.63566
+cap "a_n447_n126#" "a_n639_n126#" 7.95062
+cap "a_1281_n126#" "a_1089_n126#" 7.95062
+cap "a_n831_n126#" "a_n1215_n126#" 3.63842
+cap "a_1311_n100#" "a_1215_n100#" 216.232
+cap "a_1089_n126#" "w_n1601_n200#" 47.3
+cap "a_225_n128#" "a_n63_n126#" 4.63566
+cap "a_513_n126#" "a_417_n128#" 18.1212
+cap "a_831_n100#" "w_n1601_n200#" 157.44
+cap "a_705_n126#" "w_n1601_n200#" 47.3
+cap "a_33_n128#" "a_n351_n128#" 3.50847
+cap "a_n735_n128#" "a_n351_n128#" 3.50847
+cap "w_n1601_n200#" "a_1503_n100#" 157.44
+cap "a_1119_n100#" "a_1407_n100#" 47.7884
+cap "a_513_n126#" "a_321_n126#" 7.95062
+cap "w_n1601_n200#" "a_n129_n100#" 157.44
+cap "a_n63_n126#" "a_n255_n126#" 7.95062
+cap "a_n1185_n100#" "a_n897_n100#" 47.7884
+cap "a_n831_n126#" "a_n447_n126#" 3.63842
+cap "a_n1119_n128#" "a_n831_n126#" 4.63566
+cap "a_159_n100#" "a_255_n100#" 216.232
+cap "a_321_n126#" "a_417_n128#" 18.1212
+cap "w_n1601_n200#" "a_n1377_n100#" 157.44
+cap "a_1089_n126#" "a_801_n128#" 4.63566
+cap "a_n417_n100#" "a_n129_n100#" 47.7884
+cap "a_n705_n100#" "a_n609_n100#" 216.232
+cap "a_n159_n128#" "a_n351_n128#" 7.66667
+cap "a_n129_n100#" "a_n33_n100#" 216.232
+cap "a_n351_n128#" "a_n639_n126#" 4.63566
+cap "w_n1601_n200#" "a_n927_n128#" 46.2
+cap "w_n1601_n200#" "a_927_n100#" 157.44
+cap "a_n513_n100#" "w_n1601_n200#" 157.44
+cap "a_705_n126#" "a_801_n128#" 18.1212
+cap "a_1407_n100#" "a_1215_n100#" 78.1987
+cap "a_1311_n100#" "a_1023_n100#" 47.7884
+cap "a_447_n100#" "a_159_n100#" 47.7884
+cap "a_n513_n100#" "a_n801_n100#" 47.7884
+cap "a_n993_n100#" "a_n705_n100#" 47.7884
+cap "a_n1089_n100#" "a_n1377_n100#" 47.7884
+cap "a_225_n128#" "w_n1601_n200#" 46.2
+cap "a_1089_n126#" "a_705_n126#" 3.63842
+cap "w_n1601_n200#" "a_n321_n100#" 157.44
+cap "a_1377_n128#" "a_1185_n128#" 7.66667
+cap "a_63_n100#" "a_255_n100#" 78.1987
+cap "a_n513_n100#" "a_n417_n100#" 216.232
+cap "a_33_n128#" "a_417_n128#" 3.50847
+cap "a_n735_n128#" "a_n1023_n126#" 4.63566
+cap "w_n1601_n200#" "a_n543_n128#" 46.2
+cap "a_513_n126#" "a_897_n126#" 3.63842
+cap "a_129_n126#" "a_225_n128#" 18.1212
+cap "a_1119_n100#" "w_n1601_n200#" 157.44
+cap "w_n1601_n200#" "a_n255_n126#" 47.3
+cap "a_321_n126#" "a_33_n128#" 4.63566
+cap "w_n1601_n200#" "a_n225_n100#" 157.44
+cap "a_n417_n100#" "a_n321_n100#" 216.232
+cap "a_n63_n126#" "a_n447_n126#" 3.63842
+cap "a_n321_n100#" "a_n33_n100#" 47.7884
+cap "a_129_n126#" "a_n255_n126#" 3.63842
+cap "a_447_n100#" "a_63_n100#" 34.4127
+cap "a_351_n100#" "w_n1601_n200#" 157.44
+cap "a_n1473_n100#" "a_n1565_n74#" 216.232
+cap "w_n1601_n200#" "a_n1311_n128#" 46.2
+cap "a_n1023_n126#" "a_n639_n126#" 3.63842
+cap "a_n225_n100#" "a_n417_n100#" 78.1987
+cap "a_1473_n126#" "a_1377_n128#" 18.1212
+cap "a_n225_n100#" "a_n33_n100#" 78.1987
+cap "w_n1601_n200#" "a_n1215_n126#" 47.3
+cap "w_n1601_n200#" "a_1215_n100#" 157.44
+cap "a_1407_n100#" "a_1023_n100#" 34.4127
+cap "w_n1601_n200#" "a_543_n100#" 157.44
+cap "a_831_n100#" "a_927_n100#" 216.232
+cap "a_351_n100#" "a_n33_n100#" 34.4127
+cap "a_n513_n100#" "a_n129_n100#" 34.4127
+cap "a_1377_n128#" "a_993_n128#" 3.50847
+cap "a_n1473_n100#" "a_n1281_n100#" 78.1987
+cap "a_1185_n128#" "a_897_n126#" 4.63566
+cap "a_n1023_n126#" "a_n831_n126#" 7.95062
+cap "a_n63_n126#" "a_n351_n128#" 4.63566
+cap "a_1119_n100#" "a_831_n100#" 47.7884
+cap "a_n159_n128#" "a_33_n128#" 7.66667
+cap "w_n1601_n200#" "a_n447_n126#" 47.3
+cap "a_n321_n100#" "a_n129_n100#" 78.1987
+cap "a_n735_n128#" "a_n639_n126#" 18.1212
+cap "a_n1119_n128#" "w_n1601_n200#" 46.2
+cap "a_1119_n100#" "a_1503_n100#" 34.4127
+cap "w_n1601_n200#" "a_n609_n100#" 157.44
+cap "a_n897_n100#" "a_n705_n100#" 78.1987
+cap "a_1473_n126#" "a_1185_n128#" 4.63566
+cap "a_513_n126#" "a_609_n128#" 18.1212
+cap "a_n801_n100#" "a_n609_n100#" 78.1987
+cap "a_n225_n100#" "a_n129_n100#" 216.232
+cap "w_n1601_n200#" "a_n1565_n74#" 157.44
+cap "a_n609_n100#" "a_n417_n100#" 78.1987
+cap "w_n1601_n200#" "a_1023_n100#" 157.44
+cap "a_n993_n100#" "w_n1601_n200#" 157.44
+cap "a_417_n128#" "a_609_n128#" 7.66667
+cap "a_n543_n128#" "a_n927_n128#" 3.50847
+cap "a_n513_n100#" "a_n321_n100#" 78.1987
+cap "w_n1601_n200#" "a_639_n100#" 157.44
+cap "w_n1601_n200#" "a_n1503_n128#" 46.2
+cap "a_n1185_n100#" "a_n1473_n100#" 47.7884
+cap "a_1119_n100#" "a_927_n100#" 78.1987
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+cap "a_n993_n100#" "a_n801_n100#" 78.1987
+cap "a_1185_n128#" "a_993_n128#" 7.66667
+cap "a_831_n100#" "a_543_n100#" 47.7884
+cap "a_n735_n128#" "a_n831_n126#" 18.1212
+cap "a_1503_n100#" "a_1215_n100#" 47.7884
+cap "a_321_n126#" "a_609_n128#" 4.63566
+cap "a_159_n100#" "a_63_n100#" 216.232
+cap "a_n513_n100#" "a_n225_n100#" 47.7884
+cap "a_n993_n100#" "a_n1089_n100#" 216.232
+cap "w_n1601_n200#" "a_n351_n128#" 46.2
+cap "a_n1311_n128#" "a_n927_n128#" 3.50847
+cap "a_255_n100#" "w_n1601_n200#" 157.44
+cap "a_993_n128#" "a_897_n126#" 18.1212
+cap "a_n225_n100#" "a_n321_n100#" 216.232
+cap "w_n1601_n200#" "a_n1281_n100#" 157.44
+cap "a_n543_n128#" "a_n255_n126#" 4.63566
+cap "a_n63_n126#" "a_321_n126#" 3.63842
+cap "a_n831_n126#" "a_n639_n126#" 7.95062
+cap "a_n927_n128#" "a_n1215_n126#" 4.63566
+cap "a_n1407_n126#" "w_n1601_n200#" 47.3
+cap "a_1215_n100#" "a_927_n100#" 47.7884
+cap "a_927_n100#" "a_543_n100#" 34.4127
+cap "a_447_n100#" "w_n1601_n200#" 157.44
+cap "a_255_n100#" "a_n33_n100#" 47.7884
+cap "w_n1601_n200#" "a_735_n100#" 157.44
+cap "a_n1089_n100#" "a_n1281_n100#" 78.1987
+cap "a_513_n126#" "w_n1601_n200#" 47.3
+cap "a_831_n100#" "a_1023_n100#" 78.1987
+cap "a_897_n126#" "a_609_n128#" 4.63566
+cap "a_n63_n126#" "a_33_n128#" 18.1212
+cap "a_1119_n100#" "a_1215_n100#" 216.232
+cap "a_831_n100#" "a_639_n100#" 78.1987
+cap "a_n1119_n128#" "a_n927_n128#" 7.66667
+cap "a_n1185_n100#" "w_n1601_n200#" 157.44
+cap "a_1377_n128#" "a_1281_n126#" 18.1212
+cap "a_129_n126#" "a_513_n126#" 3.63842
+cap "a_1377_n128#" "w_n1601_n200#" 46.2
+cap "w_n1601_n200#" "a_417_n128#" 46.2
+cap "w_n1601_n200#" "a_n1023_n126#" 47.3
+cap "a_n513_n100#" "a_n609_n100#" 216.232
+cap "a_n1185_n100#" "a_n801_n100#" 34.4127
+cap "a_n897_n100#" "w_n1601_n200#" 157.44
+cap "a_n1565_n74#" "a_n1377_n100#" 78.1987
+cap "a_n1311_n128#" "a_n1215_n126#" 18.1212
+cap "a_n993_n100#" "a_n1377_n100#" 34.4127
+cap "a_321_n126#" "w_n1601_n200#" 47.3
+cap "a_129_n126#" "a_417_n128#" 4.63566
+cap "a_351_n100#" "a_543_n100#" 78.1987
+cap "a_n897_n100#" "a_n801_n100#" 216.232
+cap "a_n159_n128#" "a_n63_n126#" 18.1212
+cap "a_n543_n128#" "a_n447_n126#" 18.1212
+cap "a_n609_n100#" "a_n321_n100#" 47.7884
+cap "a_n1185_n100#" "a_n1089_n100#" 216.232
+cap "a_513_n126#" "a_801_n128#" 4.63566
+cap "a_1023_n100#" "a_927_n100#" 216.232
+cap "a_255_n100#" "a_n129_n100#" 34.4127
+cap "a_129_n126#" "a_321_n126#" 7.95062
+cap "a_n447_n126#" "a_n255_n126#" 7.95062
+cap "a_639_n100#" "a_927_n100#" 47.7884
+cap "a_993_n128#" "a_609_n128#" 3.50847
+cap "a_n897_n100#" "a_n1089_n100#" 78.1987
+cap "a_447_n100#" "a_831_n100#" 34.4127
+cap "a_n609_n100#" "a_n225_n100#" 34.4127
+cap "a_417_n128#" "a_801_n128#" 3.50847
+cap "a_831_n100#" "a_735_n100#" 216.232
+cap "a_1281_n126#" "a_1185_n128#" 18.1212
+cap "w_n1601_n200#" "a_33_n128#" 46.2
+cap "a_n735_n128#" "w_n1601_n200#" 46.2
+cap "a_n1119_n128#" "a_n1311_n128#" 7.66667
+cap "a_n1281_n100#" "a_n1377_n100#" 216.232
+cap "w_n1601_n200#" "a_1185_n128#" 46.2
+cap "a_1119_n100#" "a_1023_n100#" 216.232
+cap "a_1377_n128#" "a_1089_n126#" 4.63566
+cap "a_513_n126#" "a_705_n126#" 7.95062
+cap "a_1311_n100#" "a_1407_n100#" 216.232
+cap "a_129_n126#" "a_33_n128#" 18.1212
+cap "a_n1119_n128#" "a_n1215_n126#" 18.1212
+cap "a_159_n100#" "w_n1601_n200#" 157.44
+cap "a_1281_n126#" "a_897_n126#" 3.63842
+cap "w_n1601_n200#" "a_897_n126#" 47.3
+cap "a_705_n126#" "a_417_n128#" 4.63566
+cap "a_n159_n128#" "w_n1601_n200#" 46.2
+cap "a_n543_n128#" "a_n351_n128#" 7.66667
+cap "a_351_n100#" "a_639_n100#" 47.7884
+cap "w_n1601_n200#" "a_n639_n126#" 47.3
+cap "a_n1311_n128#" "a_n1503_n128#" 7.66667
+cap "a_321_n126#" "a_705_n126#" 3.63842
+cap "a_n351_n128#" "a_n255_n126#" 18.1212
+cap "a_1473_n126#" "a_1281_n126#" 7.95062
+cap "a_927_n100#" "a_735_n100#" 78.1987
+cap "a_1473_n126#" "w_n1601_n200#" 47.3
+cap "a_129_n126#" "a_n159_n128#" 4.63566
+cap "a_1023_n100#" "a_1215_n100#" 78.1987
+cap "a_159_n100#" "a_n33_n100#" 78.1987
+cap "a_1185_n128#" "a_801_n128#" 3.50847
+cap "a_n1185_n100#" "a_n1377_n100#" 78.1987
+cap "a_n1503_n128#" "a_n1215_n126#" 4.63566
+cap "a_639_n100#" "a_543_n100#" 216.232
+cap "a_351_n100#" "a_255_n100#" 216.232
+cap "a_63_n100#" "w_n1601_n200#" 157.44
+cap "a_1089_n126#" "a_1185_n128#" 18.1212
+cap "a_225_n128#" "a_513_n126#" 4.63566
+cap "a_n1023_n126#" "a_n927_n128#" 18.1212
+cap "a_1119_n100#" "a_735_n100#" 34.4127
+cap "a_801_n128#" "a_897_n126#" 18.1212
+cap "a_1281_n126#" "a_993_n128#" 4.63566
+cap "w_n1601_n200#" "a_993_n128#" 46.2
+cap "a_n1407_n126#" "a_n1311_n128#" 18.1212
+cap "a_1311_n100#" "w_n1601_n200#" 157.44
+cap "w_n1601_n200#" "a_n831_n126#" 47.3
+cap "a_n513_n100#" "a_n897_n100#" 34.4127
+cap "a_255_n100#" "a_543_n100#" 47.7884
+cap "a_n705_n100#" "w_n1601_n200#" 157.44
+cap "a_225_n128#" "a_417_n128#" 7.66667
+cap "a_63_n100#" "a_n33_n100#" 216.232
+cap "a_1089_n126#" "a_897_n126#" 7.95062
+cap "a_447_n100#" "a_351_n100#" 216.232
+cap "a_n1407_n126#" "a_n1215_n126#" 7.95062
+cap "a_n1119_n128#" "a_n1503_n128#" 3.50847
+cap "a_n705_n100#" "a_n801_n100#" 216.232
+cap "a_n993_n100#" "a_n609_n100#" 34.4127
+cap "a_351_n100#" "a_735_n100#" 34.4127
+cap "a_225_n128#" "a_321_n126#" 18.1212
+cap "a_705_n126#" "a_897_n126#" 7.95062
+cap "a_1473_n126#" "a_1089_n126#" 3.63842
+cap "a_n705_n100#" "a_n417_n100#" 47.7884
+cap "a_447_n100#" "a_543_n100#" 216.232
+cap "a_159_n100#" "a_n129_n100#" 47.7884
+cap "a_n705_n100#" "a_n1089_n100#" 34.4127
+cap "a_n447_n126#" "a_n351_n128#" 18.1212
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diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.mag
new file mode 100755
index 0000000..889bd28
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.mag
@@ -0,0 +1,520 @@
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+rect 1417 -74 1463 -62
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+rect 1513 -62 1519 62
+rect 1553 -62 1559 62
+rect 1513 -74 1559 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 32 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
new file mode 100755
index 0000000..83b67cb
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
@@ -0,0 +1,29 @@
+timestamp 0
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n200#" 1418 -341.94 63 -200 pdif 0 0 0 0 0 0 0 0 0 0 24800 924 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n200#" 1341 -341.94 -33 -200 pdif 0 0 0 0 0 0 0 0 0 0 26400 932 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n200#" 1418 -341.94 -125 -200 pdif 0 0 0 0 0 0 0 0 0 0 24800 924 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13872 884 18400 892 0 0 0 0 0 0 0 0 0 0
+node "a_n81_n297#" 850 -67.5651 -81 -297 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18066 1178 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "a_15_231#" 850 -67.5651 15 231 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18066 1178 0 0 2244 200 2668 208 0 0 0 0 0 0 0 0 0 0
+node "w_n161_n300#" 3562 557.712 -161 -300 nw 0 0 0 0 185904 1844 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n200#" "a_63_n200#" 577.161
+cap "a_15_231#" "a_n81_n297#" 18.1212
+cap "a_n33_n200#" "a_15_231#" 5.92513
+cap "w_n161_n300#" "a_n81_n297#" 187.59
+cap "a_n33_n200#" "w_n161_n300#" 364.332
+cap "a_63_n200#" "a_n125_n200#" 208.503
+cap "a_15_231#" "a_63_n200#" 5.92513
+cap "w_n161_n300#" "a_n125_n200#" 364.332
+cap "w_n161_n300#" "a_63_n200#" 364.332
+cap "a_n33_n200#" "a_n81_n297#" 5.92513
+cap "a_15_231#" "w_n161_n300#" 187.59
+cap "a_n81_n297#" "a_n125_n200#" 5.92513
+cap "a_n33_n200#" "a_n125_n200#" 577.161
+device msubckt sky130_fd_pr__pfet_01v8 33 -200 34 -199 l=30 w=400 "w_n161_n300#" "a_15_231#" 60 0 "a_n33_n200#" 400 0 "a_63_n200#" 400 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -200 -62 -199 l=30 w=400 "w_n161_n300#" "a_n81_n297#" 60 0 "a_n125_n200#" 400 0 "a_n33_n200#" 400 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.mag
new file mode 100755
index 0000000..fb63d39
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.mag
@@ -0,0 +1,94 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1644851365
+<< error_p >>
+rect 19 281 77 287
+rect 19 247 31 281
+rect 19 241 77 247
+rect -77 -247 -19 -241
+rect -77 -281 -65 -247
+rect -77 -287 -19 -281
+<< nwell >>
+rect -65 262 161 300
+rect -161 -262 161 262
+rect -161 -300 65 -262
+<< pmos >>
+rect -63 -200 -33 200
+rect 33 -200 63 200
+<< pdiff >>
+rect -125 188 -63 200
+rect -125 -188 -113 188
+rect -79 -188 -63 188
+rect -125 -200 -63 -188
+rect -33 188 33 200
+rect -33 -188 -17 188
+rect 17 -188 33 188
+rect -33 -200 33 -188
+rect 63 188 125 200
+rect 63 -188 79 188
+rect 113 -188 125 188
+rect 63 -200 125 -188
+<< pdiffc >>
+rect -113 -188 -79 188
+rect -17 -188 17 188
+rect 79 -188 113 188
+<< poly >>
+rect 15 281 81 297
+rect 15 247 31 281
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+rect 15 231 81 247
+rect -63 200 -33 226
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+rect -63 -231 -33 -200
+rect 33 -226 63 -200
+rect -81 -247 -15 -231
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+rect -31 -281 -15 -247
+rect -81 -297 -15 -281
+<< polycont >>
+rect 31 247 65 281
+rect -65 -281 -31 -247
+<< locali >>
+rect 15 247 31 281
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+rect -113 188 -79 204
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+<< viali >>
+rect 31 247 65 281
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+rect -65 -281 -31 -247
+<< metal1 >>
+rect 19 281 77 287
+rect 19 247 31 281
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+rect -77 -247 -19 -241
+rect -77 -281 -65 -247
+rect -31 -281 -19 -247
+rect -77 -287 -19 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2 l 0.15 m 1 nf 2 diffcov 100 polycov 100 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 100 rlcov 100 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_66F9W7.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_66F9W7.mag
new file mode 100755
index 0000000..42981d0
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_66F9W7.mag
@@ -0,0 +1,44 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645005148
+<< nwell >>
+rect -109 -162 109 162
+<< pmos >>
+rect -15 -100 15 100
+<< pdiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< pdiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< viali >>
+rect -61 62 -27 88
+rect -61 -62 -27 62
+rect -61 -88 -27 -62
+rect 27 62 61 88
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+rect 27 -88 61 -62
+<< metal1 >>
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+rect -27 -88 -21 88
+rect -67 -100 -21 -88
+rect 21 88 67 100
+rect 21 -88 27 88
+rect 61 -88 67 88
+rect 21 -100 67 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
new file mode 100755
index 0000000..d102d21
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
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+node "a_159_n100#" 753 -173.43 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
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+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n261_n726#" "li_n261_n290#" 3.09375
+cap "li_225_n726#" "li_217_n290#" 3.26562
+cap "a_n33_n100#" "li_229_174#" 2.80189
+cap "a_159_n100#" "li_229_174#" 29.7
+cap "w_n261_n210#" "li_229_174#" 13.1177
+cap "a_n33_n100#" "li_n261_174#" 2.7
+cap "a_n129_n100#" "a_159_n100#" 264.021
+cap "a_n129_n100#" "a_n33_n100#" 462.239
+cap "a_n221_n74#" "li_n261_174#" 21.2143
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+cap "a_n129_n100#" "w_n261_n210#" 447.025
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+cap "a_n221_n74#" "w_n261_n210#" 207.073
+cap "a_n159_n152#" "w_n261_n210#" 352
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
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+rect 229 174 263 224
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+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
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+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
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+<< poly >>
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+<< metal1 >>
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+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
new file mode 100755
index 0000000..5f8954f
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
@@ -0,0 +1,203 @@
+timestamp 1646319668
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_735_n100#" 712 -171.38 735 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_639_n100#" 653 -171.38 639 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_543_n100#" 653 -171.38 543 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_447_n100#" 653 -171.38 447 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_351_n100#" 653 -171.38 351 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_255_n100#" 653 -171.38 255 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 653 -171.38 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 653 -171.38 63 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 653 -171.38 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 653 -171.38 -129 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n225_n100#" 653 -171.38 -225 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n321_n100#" 653 -171.38 -321 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n417_n100#" 653 -171.38 -417 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n513_n100#" 653 -171.38 -513 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n609_n100#" 653 -171.38 -609 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n705_n100#" 653 -171.38 -705 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n797_n74#" 712 -171.38 -797 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_705_n126#" 411 4.452 705 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_609_n128#" 408 4.293 609 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_513_n126#" 411 4.452 513 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_417_n128#" 408 4.293 417 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_321_n126#" 411 4.452 321 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_225_n128#" 408 4.293 225 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_129_n126#" 411 4.452 129 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_33_n128#" 408 4.293 33 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n126#" 411 4.452 -63 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n128#" 408 4.293 -159 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n255_n126#" 411 4.452 -255 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n351_n128#" 408 4.293 -351 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n447_n126#" 411 4.452 -447 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n543_n128#" 408 4.293 -543 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n639_n126#" 411 4.452 -639 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7680 572 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n735_n128#" 408 4.293 -735 -128 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7620 568 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n833_n200#" 7208 1977.31 -833 -200 nw 0 0 0 0 659104 4132 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n833_n200#" "a_447_n100#" 157.44
+cap "w_n833_n200#" "a_n129_n100#" 157.44
+cap "a_n225_n100#" "w_n833_n200#" 157.44
+cap "a_n797_n74#" "a_n417_n100#" 34.4127
+cap "a_n797_n74#" "a_n609_n100#" 78.1987
+cap "a_513_n126#" "a_609_n128#" 18.1212
+cap "a_n797_n74#" "a_n513_n100#" 47.7884
+cap "a_513_n126#" "a_705_n126#" 7.95062
+cap "a_63_n100#" "w_n833_n200#" 157.44
+cap "a_n33_n100#" "w_n833_n200#" 157.44
+cap "a_159_n100#" "w_n833_n200#" 157.44
+cap "w_n833_n200#" "a_351_n100#" 157.44
+cap "w_n833_n200#" "a_255_n100#" 157.44
+cap "a_n609_n100#" "a_n705_n100#" 216.232
+cap "a_n705_n100#" "a_n417_n100#" 47.7884
+cap "a_n513_n100#" "a_n705_n100#" 78.1987
+cap "a_n321_n100#" "w_n833_n200#" 157.44
+cap "a_609_n128#" "a_225_n128#" 3.50847
+cap "a_321_n126#" "a_609_n128#" 4.63566
+cap "a_417_n128#" "a_705_n126#" 4.63566
+cap "a_417_n128#" "a_609_n128#" 7.66667
+cap "a_321_n126#" "a_705_n126#" 3.63842
+cap "a_n609_n100#" "a_n417_n100#" 78.1987
+cap "a_n513_n100#" "a_n609_n100#" 216.232
+cap "a_n513_n100#" "a_n417_n100#" 216.232
+cap "w_n833_n200#" "a_609_n128#" 46.2
+cap "w_n833_n200#" "a_705_n126#" 47.3
+cap "a_n797_n74#" "w_n833_n200#" 157.44
+cap "a_n159_n128#" "a_n63_n126#" 18.1212
+cap "w_n833_n200#" "a_n705_n100#" 157.44
+cap "a_129_n126#" "a_513_n126#" 3.63842
+cap "a_33_n128#" "a_n63_n126#" 18.1212
+cap "a_n159_n128#" "a_33_n128#" 7.66667
+cap "a_513_n126#" "a_225_n128#" 4.63566
+cap "a_129_n126#" "a_n63_n126#" 7.95062
+cap "a_n159_n128#" "a_129_n126#" 4.63566
+cap "a_513_n126#" "a_321_n126#" 7.95062
+cap "a_513_n126#" "a_417_n128#" 18.1212
+cap "a_129_n126#" "a_33_n128#" 18.1212
+cap "w_n833_n200#" "a_n417_n100#" 157.44
+cap "a_n513_n100#" "w_n833_n200#" 157.44
+cap "w_n833_n200#" "a_n609_n100#" 157.44
+cap "a_225_n128#" "a_n63_n126#" 4.63566
+cap "a_n159_n128#" "a_225_n128#" 3.50847
+cap "a_321_n126#" "a_n63_n126#" 3.63842
+cap "a_513_n126#" "w_n833_n200#" 47.3
+cap "a_33_n128#" "a_225_n128#" 7.66667
+cap "a_321_n126#" "a_33_n128#" 4.63566
+cap "a_n159_n128#" "a_n255_n126#" 18.1212
+cap "a_129_n126#" "a_225_n128#" 18.1212
+cap "a_417_n128#" "a_33_n128#" 3.50847
+cap "a_n159_n128#" "w_n833_n200#" 46.2
+cap "a_n255_n126#" "a_n63_n126#" 7.95062
+cap "a_129_n126#" "a_321_n126#" 7.95062
+cap "w_n833_n200#" "a_n63_n126#" 47.3
+cap "a_129_n126#" "a_417_n128#" 4.63566
+cap "a_33_n128#" "w_n833_n200#" 46.2
+cap "a_n255_n126#" "a_33_n128#" 4.63566
+cap "a_n255_n126#" "a_129_n126#" 3.63842
+cap "a_n159_n128#" "a_n543_n128#" 3.50847
+cap "a_417_n128#" "a_225_n128#" 7.66667
+cap "a_321_n126#" "a_225_n128#" 18.1212
+cap "a_129_n126#" "w_n833_n200#" 47.3
+cap "a_n159_n128#" "a_n447_n126#" 4.63566
+cap "a_n447_n126#" "a_n63_n126#" 3.63842
+cap "a_321_n126#" "a_417_n128#" 18.1212
+cap "a_n159_n128#" "a_n351_n128#" 7.66667
+cap "w_n833_n200#" "a_225_n128#" 46.2
+cap "a_n351_n128#" "a_n63_n126#" 4.63566
+cap "a_321_n126#" "w_n833_n200#" 47.3
+cap "a_33_n128#" "a_n351_n128#" 3.50847
+cap "a_417_n128#" "w_n833_n200#" 46.2
+cap "a_n255_n126#" "w_n833_n200#" 47.3
+cap "a_n255_n126#" "a_n447_n126#" 7.95062
+cap "a_n255_n126#" "a_n543_n128#" 4.63566
+cap "a_n543_n128#" "w_n833_n200#" 46.2
+cap "a_n639_n126#" "a_n255_n126#" 3.63842
+cap "w_n833_n200#" "a_n735_n128#" 46.2
+cap "a_n447_n126#" "w_n833_n200#" 47.3
+cap "a_n639_n126#" "w_n833_n200#" 47.3
+cap "a_n255_n126#" "a_n351_n128#" 18.1212
+cap "a_n639_n126#" "a_n543_n128#" 18.1212
+cap "a_n543_n128#" "a_n735_n128#" 7.66667
+cap "a_n639_n126#" "a_n735_n128#" 18.1212
+cap "w_n833_n200#" "a_n351_n128#" 46.2
+cap "a_n543_n128#" "a_n447_n126#" 18.1212
+cap "a_n639_n126#" "a_n447_n126#" 7.95062
+cap "a_n447_n126#" "a_n735_n128#" 4.63566
+cap "a_n735_n128#" "a_n351_n128#" 3.50847
+cap "a_n447_n126#" "a_n351_n128#" 18.1212
+cap "a_n543_n128#" "a_n351_n128#" 7.66667
+cap "a_n639_n126#" "a_n351_n128#" 4.63566
+cap "a_639_n100#" "a_543_n100#" 216.232
+cap "a_543_n100#" "a_735_n100#" 78.1987
+cap "a_639_n100#" "a_735_n100#" 216.232
+cap "a_543_n100#" "a_447_n100#" 216.232
+cap "a_639_n100#" "a_447_n100#" 78.1987
+cap "a_735_n100#" "a_447_n100#" 47.7884
+cap "a_159_n100#" "a_543_n100#" 34.4127
+cap "a_543_n100#" "a_351_n100#" 78.1987
+cap "a_543_n100#" "a_255_n100#" 47.7884
+cap "a_639_n100#" "a_351_n100#" 47.7884
+cap "a_639_n100#" "a_255_n100#" 34.4127
+cap "a_735_n100#" "a_351_n100#" 34.4127
+cap "a_n225_n100#" "a_n129_n100#" 216.232
+cap "a_63_n100#" "a_447_n100#" 34.4127
+cap "a_159_n100#" "a_447_n100#" 47.7884
+cap "a_n33_n100#" "a_n225_n100#" 78.1987
+cap "a_63_n100#" "a_n129_n100#" 78.1987
+cap "a_n33_n100#" "a_n129_n100#" 216.232
+cap "a_n225_n100#" "a_63_n100#" 47.7884
+cap "a_351_n100#" "a_447_n100#" 216.232
+cap "a_255_n100#" "a_447_n100#" 78.1987
+cap "a_159_n100#" "a_n225_n100#" 34.4127
+cap "a_159_n100#" "a_n129_n100#" 47.7884
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n33_n100#" "a_159_n100#" 78.1987
+cap "a_n129_n100#" "a_255_n100#" 34.4127
+cap "a_159_n100#" "a_63_n100#" 216.232
+cap "a_n33_n100#" "a_351_n100#" 34.4127
+cap "a_n33_n100#" "a_255_n100#" 47.7884
+cap "a_n321_n100#" "a_n129_n100#" 78.1987
+cap "a_n225_n100#" "a_n321_n100#" 216.232
+cap "a_63_n100#" "a_351_n100#" 47.7884
+cap "a_63_n100#" "a_255_n100#" 78.1987
+cap "a_159_n100#" "a_351_n100#" 78.1987
+cap "a_159_n100#" "a_255_n100#" 216.232
+cap "a_n33_n100#" "a_n321_n100#" 47.7884
+cap "a_255_n100#" "a_351_n100#" 216.232
+cap "a_n321_n100#" "a_63_n100#" 34.4127
+cap "a_543_n100#" "w_n833_n200#" 157.44
+cap "a_639_n100#" "w_n833_n200#" 157.44
+cap "w_n833_n200#" "a_735_n100#" 157.44
+cap "a_n225_n100#" "a_n609_n100#" 34.4127
+cap "a_n129_n100#" "a_n417_n100#" 47.7884
+cap "a_n225_n100#" "a_n417_n100#" 78.1987
+cap "a_n513_n100#" "a_n129_n100#" 34.4127
+cap "a_n513_n100#" "a_n225_n100#" 47.7884
+cap "a_705_n126#" "a_609_n128#" 18.1212
+cap "a_n33_n100#" "a_n417_n100#" 34.4127
+cap "a_n321_n100#" "a_n705_n100#" 34.4127
+cap "a_n321_n100#" "a_n417_n100#" 216.232
+cap "a_n513_n100#" "a_n321_n100#" 78.1987
+cap "a_n321_n100#" "a_n609_n100#" 47.7884
+cap "a_n797_n74#" "a_n705_n100#" 216.232
+device msubckt sky130_fd_pr__pfet_01v8 705 -100 706 -99 l=30 w=200 "w_n833_n200#" "a_705_n126#" 60 0 "a_639_n100#" 200 0 "a_735_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 609 -100 610 -99 l=30 w=200 "w_n833_n200#" "a_609_n128#" 60 0 "a_543_n100#" 200 0 "a_639_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 513 -100 514 -99 l=30 w=200 "w_n833_n200#" "a_513_n126#" 60 0 "a_447_n100#" 200 0 "a_543_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 417 -100 418 -99 l=30 w=200 "w_n833_n200#" "a_417_n128#" 60 0 "a_351_n100#" 200 0 "a_447_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 321 -100 322 -99 l=30 w=200 "w_n833_n200#" "a_321_n126#" 60 0 "a_255_n100#" 200 0 "a_351_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 225 -100 226 -99 l=30 w=200 "w_n833_n200#" "a_225_n128#" 60 0 "a_159_n100#" 200 0 "a_255_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n833_n200#" "a_129_n126#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n833_n200#" "a_33_n128#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n833_n200#" "a_n63_n126#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n833_n200#" "a_n159_n128#" 60 0 "a_n225_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -255 -100 -254 -99 l=30 w=200 "w_n833_n200#" "a_n255_n126#" 60 0 "a_n321_n100#" 200 0 "a_n225_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -351 -100 -350 -99 l=30 w=200 "w_n833_n200#" "a_n351_n128#" 60 0 "a_n417_n100#" 200 0 "a_n321_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -447 -100 -446 -99 l=30 w=200 "w_n833_n200#" "a_n447_n126#" 60 0 "a_n513_n100#" 200 0 "a_n417_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -543 -100 -542 -99 l=30 w=200 "w_n833_n200#" "a_n543_n128#" 60 0 "a_n609_n100#" 200 0 "a_n513_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -639 -100 -638 -99 l=30 w=200 "w_n833_n200#" "a_n639_n126#" 60 0 "a_n705_n100#" 200 0 "a_n609_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -735 -100 -734 -99 l=30 w=200 "w_n833_n200#" "a_n735_n128#" 60 0 "a_n797_n74#" 200 0 "a_n705_n100#" 200 0
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.mag
new file mode 100755
index 0000000..bc38771
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.mag
@@ -0,0 +1,276 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646319668
+<< nwell >>
+rect -737 162 833 200
+rect -833 -162 833 162
+rect -833 -200 737 -162
+<< pmos >>
+rect -735 -100 -705 100
+rect -639 -100 -609 100
+rect -543 -100 -513 100
+rect -447 -100 -417 100
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+rect 417 -100 447 100
+rect 513 -100 543 100
+rect 609 -100 639 100
+rect 705 -100 735 100
+<< pdiff >>
+rect -793 74 -735 100
+rect -797 62 -735 74
+rect -797 -62 -785 62
+rect -751 -62 -735 62
+rect -797 -74 -735 -62
+rect -793 -100 -735 -74
+rect -705 62 -639 100
+rect -705 -62 -689 62
+rect -655 -62 -639 62
+rect -705 -100 -639 -62
+rect -609 62 -543 100
+rect -609 -62 -593 62
+rect -559 -62 -543 62
+rect -609 -100 -543 -62
+rect -513 62 -447 100
+rect -513 -62 -497 62
+rect -463 -62 -447 62
+rect -513 -100 -447 -62
+rect -417 62 -351 100
+rect -417 -62 -401 62
+rect -367 -62 -351 62
+rect -417 -100 -351 -62
+rect -321 62 -255 100
+rect -321 -62 -305 62
+rect -271 -62 -255 62
+rect -321 -100 -255 -62
+rect -225 62 -159 100
+rect -225 -62 -209 62
+rect -175 -62 -159 62
+rect -225 -100 -159 -62
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 62 225 100
+rect 159 -62 175 62
+rect 209 -62 225 62
+rect 159 -100 225 -62
+rect 255 62 321 100
+rect 255 -62 271 62
+rect 305 -62 321 62
+rect 255 -100 321 -62
+rect 351 62 417 100
+rect 351 -62 367 62
+rect 401 -62 417 62
+rect 351 -100 417 -62
+rect 447 62 513 100
+rect 447 -62 463 62
+rect 497 -62 513 62
+rect 447 -100 513 -62
+rect 543 62 609 100
+rect 543 -62 559 62
+rect 593 -62 609 62
+rect 543 -100 609 -62
+rect 639 62 705 100
+rect 639 -62 655 62
+rect 689 -62 705 62
+rect 639 -100 705 -62
+rect 735 74 793 100
+rect 735 62 797 74
+rect 735 -62 751 62
+rect 785 -62 797 62
+rect 735 -74 797 -62
+rect 735 -100 793 -74
+<< pdiffc >>
+rect -785 -62 -751 62
+rect -689 -62 -655 62
+rect -593 -62 -559 62
+rect -497 -62 -463 62
+rect -401 -62 -367 62
+rect -305 -62 -271 62
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+rect 271 -62 305 62
+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+<< poly >>
+rect -735 100 -705 126
+rect -639 100 -609 130
+rect -543 100 -513 126
+rect -447 100 -417 130
+rect -351 100 -321 126
+rect -255 100 -225 130
+rect -159 100 -129 126
+rect -63 100 -33 130
+rect 33 100 63 126
+rect 129 100 159 130
+rect 225 100 255 126
+rect 321 100 351 130
+rect 417 100 447 126
+rect 513 100 543 130
+rect 609 100 639 126
+rect 705 100 735 130
+rect -735 -128 -705 -100
+rect -639 -126 -609 -100
+rect -543 -128 -513 -100
+rect -447 -126 -417 -100
+rect -351 -128 -321 -100
+rect -255 -126 -225 -100
+rect -159 -128 -129 -100
+rect -63 -126 -33 -100
+rect 33 -128 63 -100
+rect 129 -126 159 -100
+rect 225 -128 255 -100
+rect 321 -126 351 -100
+rect 417 -128 447 -100
+rect 513 -126 543 -100
+rect 609 -128 639 -100
+rect 705 -126 735 -100
+<< locali >>
+rect -785 62 -751 78
+rect -785 -78 -751 -62
+rect -689 62 -655 78
+rect -689 -78 -655 -62
+rect -593 62 -559 78
+rect -593 -78 -559 -62
+rect -497 62 -463 78
+rect -497 -78 -463 -62
+rect -401 62 -367 78
+rect -401 -78 -367 -62
+rect -305 62 -271 78
+rect -305 -78 -271 -62
+rect -209 62 -175 78
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect 175 62 209 78
+rect 175 -78 209 -62
+rect 271 62 305 78
+rect 271 -78 305 -62
+rect 367 62 401 78
+rect 367 -78 401 -62
+rect 463 62 497 78
+rect 463 -78 497 -62
+rect 559 62 593 78
+rect 559 -78 593 -62
+rect 655 62 689 78
+rect 655 -78 689 -62
+rect 751 62 785 78
+rect 751 -78 785 -62
+<< viali >>
+rect -785 -62 -751 62
+rect -689 -62 -655 62
+rect -593 -62 -559 62
+rect -497 -62 -463 62
+rect -401 -62 -367 62
+rect -305 -62 -271 62
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+rect 271 -62 305 62
+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+<< metal1 >>
+rect -791 62 -745 74
+rect -791 -62 -785 62
+rect -751 -62 -745 62
+rect -791 -74 -745 -62
+rect -695 62 -649 74
+rect -695 -62 -689 62
+rect -655 -62 -649 62
+rect -695 -74 -649 -62
+rect -599 62 -553 74
+rect -599 -62 -593 62
+rect -559 -62 -553 62
+rect -599 -74 -553 -62
+rect -503 62 -457 74
+rect -503 -62 -497 62
+rect -463 -62 -457 62
+rect -503 -74 -457 -62
+rect -407 62 -361 74
+rect -407 -62 -401 62
+rect -367 -62 -361 62
+rect -407 -74 -361 -62
+rect -311 62 -265 74
+rect -311 -62 -305 62
+rect -271 -62 -265 62
+rect -311 -74 -265 -62
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+rect 265 62 311 74
+rect 265 -62 271 62
+rect 305 -62 311 62
+rect 265 -74 311 -62
+rect 361 62 407 74
+rect 361 -62 367 62
+rect 401 -62 407 62
+rect 361 -74 407 -62
+rect 457 62 503 74
+rect 457 -62 463 62
+rect 497 -62 503 62
+rect 457 -74 503 -62
+rect 553 62 599 74
+rect 553 -62 559 62
+rect 593 -62 599 62
+rect 553 -74 599 -62
+rect 649 62 695 74
+rect 649 -62 655 62
+rect 689 -62 695 62
+rect 649 -74 695 -62
+rect 745 62 791 74
+rect 745 -62 751 62
+rect 785 -62 791 62
+rect 745 -74 791 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 16 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RP57DD.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RP57DD.mag
new file mode 100755
index 0000000..2b87be0
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RP57DD.mag
@@ -0,0 +1,257 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646259600
+<< error_p >>
+rect -353 262 449 300
+rect -449 -262 449 262
+rect -449 -300 353 -262
+<< nwell >>
+rect -353 262 449 300
+rect -449 -262 449 262
+rect -449 -300 353 -262
+<< pmos >>
+rect -351 -200 -321 200
+rect -255 -200 -225 200
+rect -159 -200 -129 200
+rect -63 -200 -33 200
+rect 33 -200 63 200
+rect 129 -200 159 200
+rect 225 -200 255 200
+rect 321 -200 351 200
+<< pdiff >>
+rect -409 144 -351 200
+rect -413 132 -351 144
+rect -413 -132 -401 132
+rect -367 -132 -351 132
+rect -413 -144 -351 -132
+rect -409 -200 -351 -144
+rect -321 132 -255 200
+rect -321 -132 -305 132
+rect -271 -132 -255 132
+rect -321 -200 -255 -132
+rect -225 132 -159 200
+rect -225 -132 -209 132
+rect -175 -132 -159 132
+rect -225 -200 -159 -132
+rect -129 132 -63 200
+rect -129 -132 -113 132
+rect -79 -132 -63 132
+rect -129 -200 -63 -132
+rect -33 132 33 200
+rect -33 -132 -17 132
+rect 17 -132 33 132
+rect -33 -200 33 -132
+rect 63 132 129 200
+rect 63 -132 79 132
+rect 113 -132 129 132
+rect 63 -200 129 -132
+rect 159 132 225 200
+rect 159 -132 175 132
+rect 209 -132 225 132
+rect 159 -200 225 -132
+rect 255 132 321 200
+rect 255 -132 271 132
+rect 305 -132 321 132
+rect 255 -200 321 -132
+rect 351 144 409 200
+rect 351 132 413 144
+rect 351 -132 367 132
+rect 401 -132 413 132
+rect 351 -144 413 -132
+rect 351 -200 409 -144
+<< pdiffc >>
+rect -401 -132 -367 132
+rect -305 -132 -271 132
+rect -209 -132 -175 132
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect 175 -132 209 132
+rect 271 -132 305 132
+rect 367 -132 401 132
+<< poly >>
+rect -273 281 -207 297
+rect -273 247 -257 281
+rect -223 247 -207 281
+rect -273 231 -207 247
+rect -81 281 -15 297
+rect -81 247 -65 281
+rect -31 247 -15 281
+rect -81 231 -15 247
+rect 111 281 177 297
+rect 111 247 127 281
+rect 161 247 177 281
+rect 111 231 177 247
+rect 303 281 369 297
+rect 303 247 319 281
+rect 353 247 369 281
+rect 303 231 369 247
+rect -351 200 -321 226
+rect -255 200 -225 231
+rect -159 200 -129 226
+rect -63 200 -33 231
+rect 33 200 63 226
+rect 129 200 159 231
+rect 225 200 255 226
+rect 321 200 351 231
+rect -351 -231 -321 -200
+rect -255 -226 -225 -200
+rect -159 -231 -129 -200
+rect -63 -226 -33 -200
+rect 33 -231 63 -200
+rect 129 -226 159 -200
+rect 225 -231 255 -200
+rect 321 -226 351 -200
+rect -369 -247 -303 -231
+rect -369 -281 -353 -247
+rect -319 -281 -303 -247
+rect -369 -297 -303 -281
+rect -177 -247 -111 -231
+rect -177 -281 -161 -247
+rect -127 -281 -111 -247
+rect -177 -297 -111 -281
+rect 15 -247 81 -231
+rect 15 -281 31 -247
+rect 65 -281 81 -247
+rect 15 -297 81 -281
+rect 207 -247 273 -231
+rect 207 -281 223 -247
+rect 257 -281 273 -247
+rect 207 -297 273 -281
+<< polycont >>
+rect -257 247 -223 281
+rect -65 247 -31 281
+rect 127 247 161 281
+rect 319 247 353 281
+rect -353 -281 -319 -247
+rect -161 -281 -127 -247
+rect 31 -281 65 -247
+rect 223 -281 257 -247
+<< locali >>
+rect -273 247 -257 281
+rect -223 247 -207 281
+rect -81 247 -65 281
+rect -31 247 -15 281
+rect 111 247 127 281
+rect 161 247 177 281
+rect 303 247 319 281
+rect 353 247 369 281
+rect -401 132 -367 148
+rect -401 -148 -367 -132
+rect -305 132 -271 148
+rect -305 -148 -271 -132
+rect -209 132 -175 148
+rect -209 -148 -175 -132
+rect -113 132 -79 148
+rect -113 -148 -79 -132
+rect -17 132 17 148
+rect -17 -148 17 -132
+rect 79 132 113 148
+rect 79 -148 113 -132
+rect 175 132 209 148
+rect 175 -148 209 -132
+rect 271 132 305 148
+rect 271 -148 305 -132
+rect 367 132 401 148
+rect 367 -148 401 -132
+rect -369 -281 -353 -247
+rect -319 -281 -303 -247
+rect -177 -281 -161 -247
+rect -127 -281 -111 -247
+rect 15 -281 31 -247
+rect 65 -281 81 -247
+rect 207 -281 223 -247
+rect 257 -281 273 -247
+<< viali >>
+rect -257 247 -223 281
+rect -65 247 -31 281
+rect 127 247 161 281
+rect 319 247 353 281
+rect -401 -132 -367 132
+rect -305 -132 -271 132
+rect -209 -132 -175 132
+rect -113 -132 -79 132
+rect -17 -132 17 132
+rect 79 -132 113 132
+rect 175 -132 209 132
+rect 271 -132 305 132
+rect 367 -132 401 132
+rect -353 -281 -319 -247
+rect -161 -281 -127 -247
+rect 31 -281 65 -247
+rect 223 -281 257 -247
+<< metal1 >>
+rect -269 281 -211 287
+rect -269 247 -257 281
+rect -223 247 -211 281
+rect -269 241 -211 247
+rect -77 281 -19 287
+rect -77 247 -65 281
+rect -31 247 -19 281
+rect -77 241 -19 247
+rect 115 281 173 287
+rect 115 247 127 281
+rect 161 247 173 281
+rect 115 241 173 247
+rect 307 281 365 287
+rect 307 247 319 281
+rect 353 247 365 281
+rect 307 241 365 247
+rect -407 132 -361 144
+rect -407 -132 -401 132
+rect -367 -132 -361 132
+rect -407 -144 -361 -132
+rect -311 132 -265 144
+rect -311 -132 -305 132
+rect -271 -132 -265 132
+rect -311 -144 -265 -132
+rect -215 132 -169 144
+rect -215 -132 -209 132
+rect -175 -132 -169 132
+rect -215 -144 -169 -132
+rect -119 132 -73 144
+rect -119 -132 -113 132
+rect -79 -132 -73 132
+rect -119 -144 -73 -132
+rect -23 132 23 144
+rect -23 -132 -17 132
+rect 17 -132 23 132
+rect -23 -144 23 -132
+rect 73 132 119 144
+rect 73 -132 79 132
+rect 113 -132 119 132
+rect 73 -144 119 -132
+rect 169 132 215 144
+rect 169 -132 175 132
+rect 209 -132 215 132
+rect 169 -144 215 -132
+rect 265 132 311 144
+rect 265 -132 271 132
+rect 305 -132 311 132
+rect 265 -144 311 -132
+rect 361 132 407 144
+rect 361 -132 367 132
+rect 401 -132 407 132
+rect 361 -144 407 -132
+rect -365 -247 -307 -241
+rect -365 -281 -353 -247
+rect -319 -281 -307 -247
+rect -365 -287 -307 -281
+rect -173 -247 -115 -241
+rect -173 -281 -161 -247
+rect -127 -281 -115 -247
+rect -173 -287 -115 -281
+rect 19 -247 77 -241
+rect 19 -281 31 -247
+rect 65 -281 77 -247
+rect 19 -287 77 -281
+rect 211 -247 269 -241
+rect 211 -281 223 -247
+rect 257 -281 269 -247
+rect 211 -287 269 -281
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 2 l 0.15 m 1 nf 8 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_SBMASV.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_SBMASV.mag
new file mode 100755
index 0000000..b6f661d
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_SBMASV.mag
@@ -0,0 +1,87 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1645025748
+<< error_p >>
+rect 19 181 77 187
+rect 19 147 31 181
+rect 19 141 77 147
+<< nwell >>
+rect -317 -202 169 204
+<< pmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< pdiff >>
+rect -139 62 -63 100
+rect -139 -62 -113 62
+rect -79 -62 -63 62
+rect -139 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< pdiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< nsubdiff >>
+rect -267 100 -179 124
+rect -179 -100 -139 100
+rect -267 -124 -179 -100
+<< nsubdiffcont >>
+rect -267 -100 -179 100
+<< poly >>
+rect 15 181 81 197
+rect 15 147 31 181
+rect 65 147 81 181
+rect 15 131 81 147
+rect -63 100 -33 126
+rect 33 100 63 131
+rect -63 -130 -33 -100
+rect 33 -126 63 -100
+<< polycont >>
+rect 31 147 65 181
+<< locali >>
+rect 15 147 31 181
+rect 65 147 81 181
+rect -267 100 -179 116
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect -267 -116 -179 -100
+<< viali >>
+rect 31 147 65 181
+rect -113 -44 -79 44
+rect -17 -44 17 44
+rect 79 -44 113 44
+<< metal1 >>
+rect 19 181 77 187
+rect 19 147 31 181
+rect 65 147 77 181
+rect 19 141 77 147
+rect -119 44 -73 56
+rect -119 -44 -113 44
+rect -79 -44 -73 44
+rect -119 -56 -73 -44
+rect -23 44 23 56
+rect -23 -44 -17 44
+rect 17 -44 23 44
+rect -23 -56 23 -44
+rect 73 44 119 56
+rect 73 -44 79 44
+rect 113 -44 119 44
+rect 73 -56 119 -44
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 50 viadrn 50 viagate 50 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_U9MAPM.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_U9MAPM.mag
new file mode 100755
index 0000000..6d34b43
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_U9MAPM.mag
@@ -0,0 +1,8 @@
+magic
+tech sky130A
+timestamp 1645025748
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 1 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 20 viadrn 20 viagate 20 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_YHFVVH.mag b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_YHFVVH.mag
new file mode 100755
index 0000000..aaf2415
--- /dev/null
+++ b/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_YHFVVH.mag
@@ -0,0 +1,337 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646261223
+<< error_p >>
+rect -737 162 833 200
+rect -833 -162 833 162
+rect -833 -200 737 -162
+rect -637 -412 -625 -384
+rect -637 -414 -607 -412
+<< nwell >>
+rect -737 162 833 200
+rect -833 -162 833 162
+rect -833 -200 737 -162
+<< pmos >>
+rect -735 -100 -705 100
+rect -639 -100 -609 100
+rect -543 -100 -513 100
+rect -447 -100 -417 100
+rect -351 -100 -321 100
+rect -255 -100 -225 100
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+rect 225 -100 255 100
+rect 321 -100 351 100
+rect 417 -100 447 100
+rect 513 -100 543 100
+rect 609 -100 639 100
+rect 705 -100 735 100
+<< ndiff >>
+rect -637 -414 -625 -412
+<< pdiff >>
+rect -793 74 -735 100
+rect -797 62 -735 74
+rect -797 -62 -785 62
+rect -751 -62 -735 62
+rect -797 -74 -735 -62
+rect -793 -100 -735 -74
+rect -705 62 -639 100
+rect -705 -62 -689 62
+rect -655 -62 -639 62
+rect -705 -100 -639 -62
+rect -609 62 -543 100
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+rect 735 62 797 74
+rect 735 -62 751 62
+rect 785 -62 797 62
+rect 735 -74 797 -62
+rect 735 -100 793 -74
+<< pdiffc >>
+rect -785 -62 -751 62
+rect -689 -62 -655 62
+rect -593 -62 -559 62
+rect -497 -62 -463 62
+rect -401 -62 -367 62
+rect -305 -62 -271 62
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+rect 271 -62 305 62
+rect 367 -62 401 62
+rect 463 -62 497 62
+rect 559 -62 593 62
+rect 655 -62 689 62
+rect 751 -62 785 62
+<< poly >>
+rect -735 100 -705 126
+rect -639 100 -609 130
+rect -543 100 -513 126
+rect -447 100 -417 130
+rect -351 100 -321 126
+rect -255 100 -225 130
+rect -159 100 -129 126
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+rect -667 -236 -543 -216
+rect -667 -282 -651 -236
+rect -601 -282 -543 -236
+rect -667 -300 -543 -282
+rect -603 -366 -543 -300
+<< polycont >>
+rect -651 -282 -601 -236
+<< locali >>
+rect -333 226 893 228
+rect -883 176 893 226
+rect -785 88 -751 176
+rect -593 88 -559 176
+rect -401 88 -367 176
+rect -211 88 -177 176
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+rect -733 -698 -699 -556
+rect -541 -684 -507 -542
+rect -349 -688 -315 -546
+rect -155 -694 -121 -552
+rect 35 -698 69 -556
+<< viali >>
+rect -785 62 -751 88
+rect -785 -62 -751 62
+rect -785 -88 -751 -62
+rect -689 62 -655 88
+rect -689 -62 -655 62
+rect -689 -88 -655 -62
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+rect 655 62 689 88
+rect 655 -62 689 62
+rect 655 -88 689 -62
+rect 751 62 785 88
+rect 751 -62 785 62
+rect 751 -88 785 -62
+<< metal1 >>
+rect -791 88 -745 100
+rect -791 -88 -785 88
+rect -751 -88 -745 88
+rect -791 -100 -745 -88
+rect -695 88 -649 100
+rect -695 -88 -689 88
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+rect 73 -88 79 88
+rect 113 -88 119 88
+rect 73 -100 119 -88
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+rect 169 -88 175 88
+rect 209 -88 215 88
+rect 169 -100 215 -88
+rect 265 88 311 100
+rect 265 -88 271 88
+rect 305 -88 311 88
+rect 265 -100 311 -88
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+rect 361 -88 367 88
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+rect 457 -88 463 88
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+rect 649 -100 695 -88
+rect 745 88 791 100
+rect 745 -88 751 88
+rect 785 -88 791 88
+rect 745 -100 791 -88
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 16 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 100 viadrn 100 viagate 100 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/.magicrc b/mag/preamp/.magicrc
new file mode 100755
index 0000000..ea1e753
--- /dev/null
+++ b/mag/preamp/.magicrc
@@ -0,0 +1,87 @@
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+# drc off
+drc euclidean on
+# Change this to a fixed number for repeatable behavior with GDS writes
+# e.g., "random seed 12345"
+catch {random seed}
+
+# Turn off the scale option on ext2spice or else it conflicts with the
+# scale in the model files.
+ext2spice scale off
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "/usr/local/share/pdk/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE mag
+}
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_ml_xx_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_sram_macros
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_sram_macros/${MAGTYPE}
+}
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/preamp/preamp_part1.ext b/mag/preamp/preamp_part1.ext
new file mode 100644
index 0000000..8705896
--- /dev/null
+++ b/mag/preamp/preamp_part1.ext
@@ -0,0 +1,137 @@
+timestamp 1646568821
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RFM3CD sky130_fd_pr__pfet_01v8_RFM3CD_1 1 0 539 0 1 648
+use sky130_fd_pr__pfet_01v8_RFM3CD sky130_fd_pr__pfet_01v8_RFM3CD_0 1 0 -267 0 1 648
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_1 1 0 547 0 1 122
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_0 1 0 -275 0 1 122
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_1 1 0 897 0 1 120
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_0 1 0 -625 0 1 116
+use sky130_fd_pr__nfet_01v8_8FHE5N sky130_fd_pr__nfet_01v8_8FHE5N_0 1 0 143 0 1 126
+node "m1_n692_190#" 0 17.1792 -692 190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968 132 0 0 0 0 0 0 0 0 0 0
+node "li_954_42#" 29 100.544 954 42 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10296 444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n720_n74#" 442 605.241 -720 -74 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114132 4180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n718_44#" 29 100.544 -718 44 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10296 444 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n484_188#" 577 723.792 -484 188 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54672 3284 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n720_824#" 508 779.211 -720 824 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 95636 4088 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_388_n260#" 122 549.325 388 -260 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82764 1200 0 0 30396 800 30396 800 0 0 0 0 0 0 0 0 0 0
+node "a_80_n258#" 135 463.845 80 -258 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39816 884 0 0 13824 472 13568 468 0 0 0 0 0 0 0 0 0 0
+node "a_n434_n260#" 105 547.609 -434 -260 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84192 1180 0 0 29988 792 30576 796 0 0 0 0 0 0 0 0 0 0
+node "a_864_270#" 156 548.981 864 270 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5668 344 0 0 4588 272 47476 2284 0 0 0 0 0 0 0 0 0 0
+node "a_n656_268#" 138 563.634 -656 268 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5368 324 0 0 4588 272 48220 2324 0 0 0 0 0 0 0 0 0 0
+node "a_506_940#" 368 272.18 506 940 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 640 0 0 5168 288 5168 288 0 0 0 0 0 0 0 0 0 0
+node "a_n302_940#" 400 273.412 -302 940 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10748 660 0 0 5168 288 5168 288 0 0 0 0 0 0 0 0 0 0
+node "w_n720_482#" 8846 1741.48 -720 482 nw 0 0 0 0 580492 4144 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_n720_n74#" "a_n434_n260#" 344.877
+cap "li_n484_188#" "a_n656_268#" 75.2844
+cap "li_n484_188#" "li_n718_44#" 2.90714
+cap "a_n656_268#" "a_n434_n260#" 11.325
+cap "li_n720_n74#" "a_388_n260#" 350.111
+cap "a_506_940#" "a_864_270#" 1.96875
+cap "li_n720_n74#" "a_80_n258#" 186.298
+cap "li_n484_188#" "a_864_270#" 72.9079
+cap "m1_n692_190#" "a_n656_268#" 32.7658
+cap "li_n484_188#" "a_n434_n260#" 25.375
+cap "li_n718_44#" "m1_n692_190#" 24.64
+cap "a_388_n260#" "a_864_270#" 9.58613
+cap "li_n484_188#" "a_388_n260#" 25.8506
+cap "li_n484_188#" "a_80_n258#" 11.6938
+cap "a_n302_940#" "li_n720_824#" 65.625
+cap "a_n302_940#" "w_n720_482#" 42.35
+cap "li_n720_n74#" "li_954_42#" 38.7455
+cap "a_80_n258#" "a_n434_n260#" 69.5567
+cap "li_n720_824#" "w_n720_482#" 119.005
+cap "a_n302_940#" "a_n656_268#" 1.81034
+cap "a_388_n260#" "a_80_n258#" 73.7878
+cap "li_n720_n74#" "a_n656_268#" 7.21111
+cap "w_n720_482#" "a_n656_268#" 58.372
+cap "li_n720_n74#" "li_n718_44#" 37.8889
+cap "li_n718_44#" "a_n656_268#" 1.94118
+cap "li_n484_188#" "li_954_42#" 1.33846
+cap "li_n720_824#" "a_506_940#" 66.9
+cap "li_n720_n74#" "a_864_270#" 7.24543
+cap "w_n720_482#" "a_506_940#" 37.4
+cap "w_n720_482#" "a_864_270#" 70.7256
+cap "li_n720_n74#" "li_n484_188#" 182.029
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" 9.69556
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 71.0899
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 20.76
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" 2.76
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 237.661
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 2.76
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" 4.87089
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -27.5
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 22.26
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" 81.2839
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 170.488
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 76.9611
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" -3.18889
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -54.8679
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 46.0275
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 2.88991
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 22.6607
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" -27.6128
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 9.91115
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" 613.198
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 135.987
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" -39.9664
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" 4.08628
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 16.3288
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 1.7148
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" 103.973
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 2.88991
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 113.829
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" 103.84
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 1.85057
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -22
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 193.876
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" 10.7545
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" 87.6941
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 76.539
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" -232.433
+cap "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 23.5227
+cap "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 47.3142
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" 13.0498
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n33_n50#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_159_n100#" -41.5877 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1082 -618 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_159_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n33_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n221_n74#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_159_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_159_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n33_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n33_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n221_n74#" "li_n484_188#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" "sky130_fd_pr__nfet_01v8_G6PLX8_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/VSUBS" "sky130_fd_pr__nfet_01v8_G6PLX8_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_33_n76#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" -43.072 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -480 -152 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n63_n76#" "a_80_n258#"
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_63_n50#" "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n125_n39#" -67.604 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 716 -340 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_8FHE5N_0/a_n125_n39#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "li_n720_n74#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "m1_n692_190#" -99.667 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5100 -368 0 -88 0 0 0 0 0 0 0 0 0 0
+merge "m1_n692_190#" "li_n718_44#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_63_n100#" -98.268 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 0 0 -4172 -456 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n129_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "a_n656_268#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n159_n122#" "a_388_n260#" -70.7932 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1512 -272 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_63_n100#" -59.4702 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2064 -84 0 0 0 0 6664 -352 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_63_n100#" "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n129_n100#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_1/a_n129_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "a_864_270#"
+merge "sky130_fd_pr__nfet_01v8_G6PLX8_0/a_n159_n122#" "a_n434_n260#" -81.108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -720 -288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" "a_506_940#" 2.544 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 960 -80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" "a_n302_940#" -1.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -600 -100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" -392.688 0 0 0 0 -130896 -2168 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "w_n720_482#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -2.028 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 -252 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "li_n720_824#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "li_954_42#" -65.9972 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7648 -320 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/mag/preamp/preamp_part1.mag b/mag/preamp/preamp_part1.mag
new file mode 100755
index 0000000..d8d50ef
--- /dev/null
+++ b/mag/preamp/preamp_part1.mag
@@ -0,0 +1,182 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646734260
+<< nwell >>
+rect -720 482 1018 816
+<< poly >>
+rect -302 1000 -234 1016
+rect -302 958 -286 1000
+rect -250 958 -234 1000
+rect -302 940 -234 958
+rect 506 1000 574 1016
+rect 506 958 522 1000
+rect 562 958 574 1000
+rect 506 940 574 958
+rect -282 754 -252 940
+rect 524 764 556 940
+rect -656 326 -594 342
+rect -656 284 -640 326
+rect -606 284 -594 326
+rect -656 268 -594 284
+rect 864 328 926 344
+rect 864 286 880 328
+rect 914 286 926 328
+rect 864 270 926 286
+rect -640 242 -610 268
+rect 882 234 912 270
+rect -434 4 -404 6
+rect -338 4 -308 6
+rect -242 4 -212 6
+rect -146 4 -116 6
+rect -434 -168 -116 4
+rect -434 -234 -406 -168
+rect -144 -234 -116 -168
+rect -434 -260 -116 -234
+rect 80 -170 206 58
+rect 80 -238 104 -170
+rect 180 -238 206 -170
+rect 80 -258 206 -238
+rect 388 -2 418 4
+rect 484 -2 514 4
+rect 580 -2 610 4
+rect 676 -2 706 4
+rect 388 -164 706 -2
+rect 388 -234 414 -164
+rect 680 -234 706 -164
+rect 388 -260 706 -234
+<< polycont >>
+rect -286 958 -250 1000
+rect 522 958 562 1000
+rect -640 284 -606 326
+rect 880 286 914 328
+rect -406 -234 -144 -168
+rect 104 -238 180 -170
+rect 414 -234 680 -164
+<< locali >>
+rect -302 1000 -234 1016
+rect -302 958 -286 1000
+rect -250 958 -234 1000
+rect -302 940 -234 958
+rect 506 1000 574 1016
+rect 506 958 522 1000
+rect 562 958 574 1000
+rect 506 940 574 958
+rect -720 824 1020 874
+rect -328 696 -294 824
+rect 566 698 600 824
+rect -656 326 -594 342
+rect -656 284 -642 326
+rect -606 284 -594 326
+rect -656 268 -594 284
+rect 864 328 926 344
+rect 864 286 878 328
+rect 914 286 926 328
+rect -484 238 756 272
+rect 864 270 926 286
+rect -718 44 -652 200
+rect -484 188 -450 238
+rect -292 194 -258 238
+rect -100 190 -66 238
+rect 126 148 160 238
+rect 338 192 372 238
+rect 530 194 564 238
+rect 722 192 756 238
+rect -598 -22 -564 52
+rect 30 48 66 88
+rect 222 48 256 86
+rect 30 -22 256 48
+rect 836 -22 870 54
+rect 954 42 1020 198
+rect -720 -74 1020 -22
+rect -422 -166 -128 -150
+rect -422 -234 -406 -166
+rect -144 -234 -128 -166
+rect -422 -252 -128 -234
+rect 78 -170 206 -152
+rect 78 -238 104 -170
+rect 180 -238 206 -170
+rect 78 -260 206 -238
+rect 398 -164 696 -148
+rect 398 -234 414 -164
+rect 680 -234 696 -164
+rect 398 -250 696 -234
+<< viali >>
+rect -286 958 -250 1000
+rect 522 958 562 1000
+rect -642 284 -640 326
+rect -640 284 -606 326
+rect 878 286 880 328
+rect 880 286 914 328
+rect -406 -168 -144 -166
+rect -406 -234 -144 -168
+rect 106 -238 180 -170
+rect 414 -234 680 -164
+<< metal1 >>
+rect -302 1000 -234 1016
+rect -302 958 -286 1000
+rect -250 958 -234 1000
+rect -302 940 -234 958
+rect 506 1000 574 1016
+rect 506 958 522 1000
+rect 562 958 574 1000
+rect 506 940 574 958
+rect -656 326 -594 342
+rect -248 326 -200 592
+rect 472 326 520 620
+rect 864 328 926 344
+rect 864 326 878 328
+rect -718 284 -642 326
+rect -606 284 -160 326
+rect -656 268 -594 284
+rect -692 190 -648 212
+rect -390 154 -352 284
+rect -198 150 -160 284
+rect 434 286 878 326
+rect 914 326 926 328
+rect 914 286 1020 326
+rect 434 284 1020 286
+rect 434 188 470 284
+rect 624 192 660 284
+rect 864 270 926 284
+rect -422 -166 -128 -150
+rect -422 -234 -406 -166
+rect -144 -234 -128 -166
+rect -422 -254 -128 -234
+rect 78 -170 206 -152
+rect 78 -238 106 -170
+rect 180 -238 206 -170
+rect 78 -258 206 -238
+rect 398 -164 696 -148
+rect 398 -234 414 -164
+rect 680 -234 696 -164
+rect 398 -250 696 -234
+use sky130_fd_pr__nfet_01v8_8FHE5N sky130_fd_pr__nfet_01v8_8FHE5N_0
+timestamp 1646423143
+transform 1 0 143 0 1 126
+box -125 -76 125 76
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_0
+timestamp 1646431323
+transform 1 0 -625 0 1 116
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_F5U58G#1 sky130_fd_pr__nfet_01v8_F5U58G_1
+timestamp 1646431323
+transform 1 0 897 0 1 120
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_0
+timestamp 1646422066
+transform 1 0 -275 0 1 122
+box -221 -126 221 150
+use sky130_fd_pr__nfet_01v8_G6PLX8 sky130_fd_pr__nfet_01v8_G6PLX8_1
+timestamp 1646422066
+transform 1 0 547 0 1 122
+box -221 -126 221 150
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0
+timestamp 1646431323
+transform 1 0 -267 0 1 648
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1
+timestamp 1646431323
+transform 1 0 539 0 1 648
+box -109 -162 109 162
+<< end >>
diff --git a/mag/preamp/preamp_part2.ext b/mag/preamp/preamp_part2.ext
new file mode 100644
index 0000000..eaf00fb
--- /dev/null
+++ b/mag/preamp/preamp_part2.ext
@@ -0,0 +1,98 @@
+timestamp 1646595273
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use sky130_fd_pr__pfet_01v8_RFM3CD sky130_fd_pr__pfet_01v8_RFM3CD_1 1 0 989 0 1 864
+use sky130_fd_pr__pfet_01v8_RFM3CD sky130_fd_pr__pfet_01v8_RFM3CD_0 1 0 407 0 1 864
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0 sky130_fd_pr__nfet_01v8_XJTKXQ_1 1 0 953 0 1 346
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0 1 0 443 0 1 346
+use sky130_fd_pr__nfet_01v8_F5U58G#0 sky130_fd_pr__nfet_01v8_F5U58G_2 1 0 1209 0 1 460
+use sky130_fd_pr__nfet_01v8_F5U58G#0 sky130_fd_pr__nfet_01v8_F5U58G_1 1 0 189 0 1 458
+use sky130_fd_pr__nfet_01v8_F5U58G#0 sky130_fd_pr__nfet_01v8_F5U58G_0 1 0 695 0 1 346
+node "m1_322_206#" 3 397.952 322 206 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38892 2024 0 0 0 0 0 0 0 0 0 0
+node "li_116_138#" 268 538.643 116 138 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70144 2596 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_928_394#" 180 292.614 928 394 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25572 1312 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_210_488#" 177 220.487 210 488 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26088 1316 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_116_1034#" 327 645.849 116 1034 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69696 2836 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_792_2#" 164 872.971 792 2 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37044 896 0 0 8836 376 64452 2328 0 0 0 0 0 0 0 0 0 0
+node "a_380_480#" 146 690.068 380 480 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27360 748 0 0 8836 376 51812 1784 0 0 0 0 0 0 0 0 0 0
+node "a_148_644#" 577 937.83 148 644 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15308 876 0 0 11108 596 11108 596 69948 2372 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "li_928_394#" "li_116_138#" 32.2917
+cap "a_380_480#" "li_210_488#" 178.188
+cap "li_116_1034#" "a_148_644#" 16.5106
+cap "a_380_480#" "li_928_394#" 57.6468
+cap "a_380_480#" "li_116_138#" 9.28743
+cap "m1_322_206#" "a_792_2#" 299.669
+cap "a_792_2#" "a_148_644#" 3.65854
+cap "li_210_488#" "li_116_1034#" 4.71429
+cap "li_210_488#" "a_148_644#" 50.1267
+cap "li_928_394#" "li_116_1034#" 4.59836
+cap "m1_322_206#" "li_116_138#" 37.0422
+cap "li_928_394#" "a_148_644#" 46.0691
+cap "m1_322_206#" "a_380_480#" 84.0424
+cap "a_380_480#" "a_148_644#" 146.458
+cap "li_116_138#" "a_792_2#" 228.975
+cap "li_210_488#" "li_116_138#" 31.6529
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 14.49
+cap "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 8.65496
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 17.5978
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 46.9936
+cap "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 8.03571
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 91.0061
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 58.6286
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 9.97778
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 259.594
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 29.4199
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 29.4199
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#" 5.84746
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 62.4517
+cap "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" 42.3584
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 12.4699
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 29.4199
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" 13.4145
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 124.301
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" 70.2119
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 12.0146
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" 129.657
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 10.5791
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#" 10.281
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 29.4199
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" 7.15771
+cap "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 7.03809
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 88.1138
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" 223.402
+cap "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" 457.398
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" 7.93451
+cap "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#" 42.3584
+cap "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" 12.0056
+cap "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126#" 2.89916
+merge "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n73_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n33_n100#" -152.488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2788 -368 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n33_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n73_n100#" "li_928_394#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/VSUBS" "sky130_fd_pr__nfet_01v8_F5U58G_2/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_2/VSUBS" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/VSUBS" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/VSUBS"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/VSUBS" "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/VSUBS" "VSUBS"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n73_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" -117.641 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4032 -316 0 0 0 0 -644 -120 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n63_n152#" "a_792_2#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_n73_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" -161.835 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3864 -628 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n125_n74#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_63_n100#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_63_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#"
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_1/a_n125_n74#" "m1_322_206#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_15_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" -141.364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2924 -376 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n33_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_15_n100#" "li_210_488#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_2/a_15_n100#" "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" -113.535 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2520 -292 0 0 0 0 -644 -120 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_XJTKXQ_0/a_n63_n152#" "a_380_480#"
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n73_n100#" "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" -98.3839 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -476 -164 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__pfet_01v8_RFM3CD_1/a_15_n100#" "li_116_1034#"
+merge "sky130_fd_pr__nfet_01v8_F5U58G_0/a_15_n100#" "li_116_138#" -43.6279 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -68 -72 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#" "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" -126.53 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -420 -148 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+merge "sky130_fd_pr__nfet_01v8_F5U58G_2/a_n15_n126#" "a_148_644#"
diff --git a/mag/preamp/preamp_part2.mag b/mag/preamp/preamp_part2.mag
new file mode 100755
index 0000000..36d4526
--- /dev/null
+++ b/mag/preamp/preamp_part2.mag
@@ -0,0 +1,143 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646734260
+<< poly >>
+rect 148 706 230 722
+rect 148 660 164 706
+rect 214 660 230 706
+rect 148 644 230 660
+rect 1170 704 1246 714
+rect 1170 668 1188 704
+rect 1228 668 1246 704
+rect 1170 652 1246 668
+rect 174 576 204 644
+rect 380 608 614 620
+rect 380 546 536 608
+rect 598 546 614 608
+rect 1194 580 1224 652
+rect 380 530 614 546
+rect 380 480 506 530
+rect 890 92 1016 226
+rect 792 80 1016 92
+rect 792 18 808 80
+rect 870 18 1016 80
+rect 792 2 1016 18
+<< polycont >>
+rect 164 660 214 706
+rect 1188 668 1228 704
+rect 536 546 598 608
+rect 808 18 870 80
+<< locali >>
+rect 116 1034 1282 1088
+rect 346 938 380 1034
+rect 1016 932 1050 1034
+rect 148 706 230 722
+rect 148 660 164 706
+rect 214 660 230 706
+rect 148 644 230 660
+rect 434 538 468 796
+rect 210 488 468 538
+rect 520 608 614 624
+rect 520 546 536 608
+rect 598 546 614 608
+rect 520 530 614 546
+rect 928 532 962 790
+rect 1170 704 1246 714
+rect 1170 668 1188 704
+rect 1228 668 1246 704
+rect 1170 652 1246 668
+rect 420 396 468 488
+rect 928 484 1188 532
+rect 928 394 976 484
+rect 722 196 756 270
+rect 116 138 1282 196
+rect 792 80 886 96
+rect 792 18 808 80
+rect 870 18 886 80
+rect 792 2 886 18
+<< viali >>
+rect 164 660 214 706
+rect 536 546 598 608
+rect 1188 668 1228 704
+rect 808 18 870 80
+<< metal1 >>
+rect 148 712 230 722
+rect 148 654 158 712
+rect 220 654 230 712
+rect 148 644 230 654
+rect 1170 710 1246 714
+rect 1170 658 1180 710
+rect 1236 658 1246 710
+rect 1170 652 1246 658
+rect 520 608 1276 624
+rect 520 546 536 608
+rect 598 562 1276 608
+rect 598 546 614 562
+rect 520 530 614 546
+rect 1230 520 1276 562
+rect 122 92 168 398
+rect 322 244 370 288
+rect 516 244 562 284
+rect 628 244 674 292
+rect 834 244 880 296
+rect 1026 244 1072 284
+rect 322 206 1072 244
+rect 792 92 886 96
+rect 122 80 886 92
+rect 122 30 808 80
+rect 792 18 808 30
+rect 870 18 886 80
+rect 792 2 886 18
+<< via1 >>
+rect 158 706 220 712
+rect 158 660 164 706
+rect 164 660 214 706
+rect 214 660 220 706
+rect 158 654 220 660
+rect 1180 704 1236 710
+rect 1180 668 1188 704
+rect 1188 668 1228 704
+rect 1228 668 1236 704
+rect 1180 658 1236 668
+<< metal2 >>
+rect 148 714 230 722
+rect 1180 714 1236 720
+rect 148 712 1246 714
+rect 148 654 158 712
+rect 220 710 1246 712
+rect 220 658 1180 710
+rect 1236 658 1246 710
+rect 220 654 1246 658
+rect 148 652 1246 654
+rect 148 644 230 652
+rect 1180 648 1236 652
+use sky130_fd_pr__nfet_01v8_F5U58G#0#0 sky130_fd_pr__nfet_01v8_F5U58G_0
+timestamp 1646431323
+transform 1 0 695 0 1 346
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_F5U58G#0#0 sky130_fd_pr__nfet_01v8_F5U58G_1
+timestamp 1646431323
+transform 1 0 189 0 1 458
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_F5U58G#0#0 sky130_fd_pr__nfet_01v8_F5U58G_2
+timestamp 1646431323
+transform 1 0 1209 0 1 460
+box -73 -126 73 126
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_0
+timestamp 1646429429
+transform 1 0 443 0 1 346
+box -125 -152 125 154
+use sky130_fd_pr__nfet_01v8_XJTKXQ#0#0 sky130_fd_pr__nfet_01v8_XJTKXQ_1
+timestamp 1646429429
+transform 1 0 953 0 1 346
+box -125 -152 125 154
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_0
+timestamp 1646431323
+transform 1 0 407 0 1 864
+box -109 -162 109 162
+use sky130_fd_pr__pfet_01v8_RFM3CD#0 sky130_fd_pr__pfet_01v8_RFM3CD_1
+timestamp 1646431323
+transform 1 0 989 0 1 864
+box -109 -162 109 162
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
new file mode 100644
index 0000000..ef1fa55
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
@@ -0,0 +1,19 @@
+timestamp 1646423143
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n50#" 236 -13.94 63 -50 ndif 0 0 0 0 0 0 0 0 6112 324 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 3588 248 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n50#" 213 -13.94 -33 -50 ndif 0 0 0 0 0 0 0 0 6600 332 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 3588 248 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n39#" 236 -13.94 -125 -39 ndif 0 0 0 0 0 0 0 0 6112 324 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2924 240 3588 248 0 0 0 0 0 0 0 0 0 0
+node "a_33_n76#" 244 49.234 33 -76 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4560 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n76#" 244 49.234 -63 -76 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4560 364 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n125_n39#" "a_n33_n50#" 115.974
+cap "a_n33_n50#" "a_63_n50#" 115.974
+cap "a_n125_n39#" "a_63_n50#" 42.0031
+cap "a_33_n76#" "a_n63_n76#" 18.1212
+device msubckt sky130_fd_pr__nfet_01v8 33 -50 34 -49 l=30 w=100 "VSUBS" "a_33_n76#" 60 0 "a_n33_n50#" 100 0 "a_63_n50#" 100 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -50 -62 -49 l=30 w=100 "VSUBS" "a_n63_n76#" 60 0 "a_n125_n39#" 100 0 "a_n33_n50#" 100 0
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.mag
new file mode 100755
index 0000000..1b9cf1d
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.mag
@@ -0,0 +1,62 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646423143
+<< nmos >>
+rect -63 -50 -33 50
+rect 33 -50 63 50
+<< ndiff >>
+rect -121 39 -63 50
+rect -125 27 -63 39
+rect -125 -27 -113 27
+rect -79 -27 -63 27
+rect -125 -39 -63 -27
+rect -121 -50 -63 -39
+rect -33 27 33 50
+rect -33 -27 -17 27
+rect 17 -27 33 27
+rect -33 -50 33 -27
+rect 63 39 121 50
+rect 63 27 125 39
+rect 63 -27 79 27
+rect 113 -27 125 27
+rect 63 -39 125 -27
+rect 63 -50 121 -39
+<< ndiffc >>
+rect -113 -27 -79 27
+rect -17 -27 17 27
+rect 79 -27 113 27
+<< poly >>
+rect -63 50 -33 76
+rect 33 50 63 76
+rect -63 -76 -33 -50
+rect 33 -76 63 -50
+<< locali >>
+rect -113 27 -79 43
+rect -113 -43 -79 -27
+rect -17 27 17 43
+rect -17 -43 17 -27
+rect 79 27 113 43
+rect 79 -43 113 -27
+<< viali >>
+rect -113 -27 -79 27
+rect -17 -27 17 27
+rect 79 -27 113 27
+<< metal1 >>
+rect -119 27 -73 39
+rect -119 -27 -113 27
+rect -79 -27 -73 27
+rect -119 -39 -73 -27
+rect -23 27 23 39
+rect -23 -27 -17 27
+rect 17 -27 23 27
+rect -23 -39 23 -27
+rect 73 27 119 39
+rect 73 -27 79 27
+rect 113 -27 119 27
+rect 73 -39 119 -27
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 0.5 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 1 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.ext"
new file mode 100644
index 0000000..470e5e2
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.ext"
@@ -0,0 +1,13 @@
+timestamp 1646431323
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 470 -13.94 15 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 470 -13.94 -73 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 49.234 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n100#" "a_15_n100#" 253.905
+device msubckt sky130_fd_pr__nfet_01v8 -15 -100 -14 -99 l=30 w=200 "VSUBS" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.mag"
new file mode 100755
index 0000000..8dc9818
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0430.mag"
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.ext"
new file mode 100644
index 0000000..470e5e2
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.ext"
@@ -0,0 +1,13 @@
+timestamp 1646431323
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 470 -13.94 15 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 470 -13.94 -73 -100 ndif 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 49.234 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n73_n100#" "a_15_n100#" 253.905
+device msubckt sky130_fd_pr__nfet_01v8 -15 -100 -14 -99 l=30 w=200 "VSUBS" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.mag"
new file mode 100755
index 0000000..8dc9818
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G\0431.mag"
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G.mag
new file mode 100755
index 0000000..8dc9818
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nmos >>
+rect -15 -100 15 100
+<< ndiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< ndiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
new file mode 100644
index 0000000..01cc9c5
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
@@ -0,0 +1,28 @@
+timestamp 1646422066
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_159_n100#" 456 -13.94 159 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_63_n100#" 420 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 420 -13.94 -129 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n74#" 456 -13.94 -221 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n122#" 2066 322.437 -159 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38580 2632 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n221_n74#" "a_159_n100#" 34.4127
+cap "a_n129_n100#" "a_n33_n100#" 216.232
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n33_n100#" "a_159_n100#" 78.1987
+cap "a_n129_n100#" "a_63_n100#" 78.1987
+cap "a_n129_n100#" "a_159_n100#" 47.7884
+cap "a_159_n100#" "a_63_n100#" 216.232
+cap "a_n221_n74#" "a_n33_n100#" 78.1987
+cap "a_n221_n74#" "a_n129_n100#" 216.232
+cap "a_n221_n74#" "a_63_n100#" 47.7884
+device msubckt sky130_fd_pr__nfet_01v8 129 -100 130 -99 l=30 w=200 "VSUBS" "a_n159_n122#" 60 0 "a_63_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n159_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n159_n122#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -159 -100 -158 -99 l=30 w=200 "VSUBS" "a_n159_n122#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.mag
new file mode 100755
index 0000000..866bb9e
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.mag
@@ -0,0 +1,98 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646422066
+<< error_p >>
+rect -159 -126 -129 -122
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+rect 129 -126 159 -122
+<< nmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< ndiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 74 217 100
+rect 159 62 221 74
+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< ndiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 120 159 150
+rect -159 100 -129 120
+rect -63 100 -33 120
+rect 33 100 63 120
+rect 129 100 159 120
+rect -159 -122 -129 -100
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+rect 129 -122 159 -100
+<< locali >>
+rect -209 62 -175 78
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+rect 175 62 209 78
+rect 175 -78 209 -62
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.ext" "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.ext"
new file mode 100644
index 0000000..9c0c33c
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.ext"
@@ -0,0 +1,17 @@
+timestamp 1646429429
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n152#" 1057 214.297 -63 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22716 1476 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_n63_n152#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n152#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git "a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.mag" "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.mag"
new file mode 100755
index 0000000..38cbd5d
--- /dev/null
+++ "b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ\0430.mag"
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646429429
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 122 63 154
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -118 -33 -100
+rect 33 -118 63 -100
+rect -63 -152 63 -118
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ.mag b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
new file mode 100755
index 0000000..38cbd5d
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
@@ -0,0 +1,64 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646429429
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 122 63 154
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -118 -33 -100
+rect 33 -118 63 -100
+rect -63 -152 63 -118
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
new file mode 100644
index 0000000..ba30850
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
@@ -0,0 +1,17 @@
+timestamp 1646431323
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_15_n100#" 736 -171.38 15 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n73_n100#" 736 -171.38 -73 -100 pdif 0 0 0 0 0 0 0 0 0 0 11600 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n15_n126#" 405 4.134 -15 -126 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7560 564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n109_n162#" 2527 211.896 -109 -162 nw 0 0 0 0 70632 1084 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_15_n100#" "w_n109_n162#" 157.44
+cap "a_n73_n100#" "a_15_n100#" 253.905
+cap "a_n73_n100#" "w_n109_n162#" 157.44
+cap "a_n15_n126#" "w_n109_n162#" 45.1
+device msubckt sky130_fd_pr__pfet_01v8 -15 -100 -14 -99 l=30 w=200 "w_n109_n162#" "a_n15_n126#" 60 0 "a_n73_n100#" 200 0 "a_15_n100#" 200 0
diff --git a/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.mag b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.mag
new file mode 100755
index 0000000..7091e97
--- /dev/null
+++ b/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.mag
@@ -0,0 +1,45 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646431323
+<< nwell >>
+rect -109 -162 109 162
+<< pmos >>
+rect -15 -100 15 100
+<< pdiff >>
+rect -73 62 -15 100
+rect -73 -62 -61 62
+rect -27 -62 -15 62
+rect -73 -100 -15 -62
+rect 15 62 73 100
+rect 15 -62 27 62
+rect 61 -62 73 62
+rect 15 -100 73 -62
+<< pdiffc >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< poly >>
+rect -15 100 15 126
+rect -15 -126 15 -100
+<< locali >>
+rect -61 62 -27 78
+rect -61 -78 -27 -62
+rect 27 62 61 78
+rect 27 -78 61 -62
+<< viali >>
+rect -61 -62 -27 62
+rect 27 -62 61 62
+<< metal1 >>
+rect -67 62 -21 74
+rect -67 -62 -61 62
+rect -27 -62 -21 62
+rect -67 -74 -21 -62
+rect 21 62 67 74
+rect 21 -62 27 62
+rect 61 -62 67 62
+rect 21 -74 67 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 1 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_FT76RJ.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT76RJ.mag
new file mode 100644
index 0000000..41301de
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT76RJ.mag
@@ -0,0 +1,51 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646980500
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 -51 147
+rect 51 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 -51 -113
+rect 51 -147 147 -113
+<< psubdiffcont >>
+rect -51 113 51 147
+rect -147 -51 -113 51
+rect 113 -51 147 51
+rect -51 -147 51 -113
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 -51 147
+rect 51 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 -51 -113
+rect 51 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 1 etc 1 ebc 1 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
new file mode 100644
index 0000000..48f8b44
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
@@ -0,0 +1,10 @@
+timestamp 1646995406
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__diode_pw2nd_05v5 a=area p=pj
+node "a_n45_n45#" 18 219.921 -45 -45 ndi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6468 328 7020 336 0 0 0 0 0 0 0 0 0 0
+substrate "w_n183_n183#" 0 0 -183 -183 pw 133956 1464 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0
+device ndiode sky130_fd_pr__diode_pw2nd_05v5 -45 -45 -44 -44 a=8100 p=360 "w_n183_n183#" "a_n45_n45#" 132 0 "w_n183_n183#" 0 0
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.mag
new file mode 100644
index 0000000..65f1b71
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect -147 -113 -113 -51
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< psubdiffcont >>
+rect -147 -51 -113 51
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect -147 -113 -113 -51
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 0 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_GT7G3L.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_GT7G3L.mag
new file mode 100644
index 0000000..bf4185d
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_GT7G3L.mag
@@ -0,0 +1,45 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< psubdiffcont >>
+rect -147 -51 -113 51
+rect 113 -51 147 51
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 51 -113 113
+rect 113 51 147 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect -147 -113 -113 -51
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 1 erc 1 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
new file mode 100644
index 0000000..48f8b44
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
@@ -0,0 +1,10 @@
+timestamp 1646995406
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__diode_pw2nd_05v5 a=area p=pj
+node "a_n45_n45#" 18 219.921 -45 -45 ndi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6468 328 7020 336 0 0 0 0 0 0 0 0 0 0
+substrate "w_n183_n183#" 0 0 -183 -183 pw 133956 1464 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35360 2080 0 0 0 0 0 0 0 0 0 0 0 0
+device ndiode sky130_fd_pr__diode_pw2nd_05v5 -45 -45 -44 -44 a=8100 p=360 "w_n183_n183#" "a_n45_n45#" 132 0 "w_n183_n183#" 0 0
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.mag
new file mode 100644
index 0000000..044caf4
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.mag
@@ -0,0 +1,42 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect 113 51 147 113
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< psubdiffcont >>
+rect 113 -51 147 51
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect 113 51 147 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect 113 -113 147 -51
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 0 erc 1 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git a/mag/sky130_fd_pr__diode_pw2nd_05v5_U68KKY.mag b/mag/sky130_fd_pr__diode_pw2nd_05v5_U68KKY.mag
new file mode 100644
index 0000000..2abe223
--- /dev/null
+++ b/mag/sky130_fd_pr__diode_pw2nd_05v5_U68KKY.mag
@@ -0,0 +1,38 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646995406
+<< pwell >>
+rect -183 -183 183 183
+<< psubdiff >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< ndiode >>
+rect -45 33 45 45
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -45 45 -33
+<< ndiodec >>
+rect -33 -33 33 33
+<< locali >>
+rect -147 113 147 147
+rect -147 -113 -113 113
+rect -49 -33 -33 33
+rect 33 -33 49 33
+rect 113 -113 147 113
+rect -147 -147 147 -113
+<< viali >>
+rect -33 -33 33 33
+<< metal1 >>
+rect -45 33 45 39
+rect -45 -33 -33 33
+rect 33 -33 45 33
+rect -45 -39 45 -33
+<< properties >>
+string FIXED_BBOX -130 -130 130 130
+string gencell sky130_fd_pr__diode_pw2nd_05v5
+string library sky130
+string parameters w 0.45 l 0.45 area 202.5m peri 1.8 nx 1 ny 1 dummy 0 lmin 0.45 wmin 0.45 elc 0 erc 0 etc 0 ebc 0 doverlap 0 compatible {sky130_fd_pr__diode_pw2nd_05v5 sky130_fd_pr__diode_pw2nd_05v5_lvt sky130_fd_pr__diode_pw2nd_05v5_nvt sky130_fd_pr__diode_pw2nd_11v0} full_metal 1 vias 1 viagb 0 viagt 0 viagl 0 viagr 0
+<< end >>
diff --git "a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext" "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext"
new file mode 100755
index 0000000..052c334
--- /dev/null
+++ "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.ext"
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n122#" 392 44.198 33 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n122#" 392 44.198 -63 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n33_n100#" "a_n125_n74#" 216.232
+cap "a_n63_n122#" "a_33_n122#" 15.3333
+cap "a_n33_n100#" "a_63_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git "a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag" "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag"
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ "b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ\0431.mag"
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -63 122 -33 126
+rect 33 122 63 126
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
new file mode 100755
index 0000000..e7e29c9
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
@@ -0,0 +1,19 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "a_63_n100#" 456 -13.94 63 -100 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 420 -13.94 -33 -100 ndif 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n125_n74#" 456 -13.94 -125 -74 ndif 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5304 380 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_33_n122#" 392 44.198 33 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_n63_n122#" 392 44.198 -63 -122 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7320 548 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_33_n122#" "a_n63_n122#" 15.3333
+cap "a_n125_n74#" "a_n33_n100#" 216.232
+cap "a_n125_n74#" "a_63_n100#" 78.1987
+cap "a_n33_n100#" "a_63_n100#" 216.232
+device msubckt sky130_fd_pr__nfet_01v8 33 -100 34 -99 l=30 w=200 "VSUBS" "a_33_n122#" 60 0 "a_n33_n100#" 200 0 "a_63_n100#" 200 0
+device msubckt sky130_fd_pr__nfet_01v8 -63 -100 -62 -99 l=30 w=200 "VSUBS" "a_n63_n122#" 60 0 "a_n125_n74#" 200 0 "a_n33_n100#" 200 0
diff --git a/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.mag b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
new file mode 100755
index 0000000..9e1b853
--- /dev/null
+++ b/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.mag
@@ -0,0 +1,67 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -63 122 -33 126
+rect 33 122 63 126
+rect -63 -126 -33 -122
+rect 33 -126 63 -122
+<< nmos >>
+rect -63 -100 -33 100
+rect 33 -100 63 100
+<< ndiff >>
+rect -121 74 -63 100
+rect -125 62 -63 74
+rect -125 -62 -113 62
+rect -79 -62 -63 62
+rect -125 -74 -63 -62
+rect -121 -100 -63 -74
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 74 121 100
+rect 63 62 125 74
+rect 63 -62 79 62
+rect 113 -62 125 62
+rect 63 -74 125 -62
+rect 63 -100 121 -74
+<< ndiffc >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< poly >>
+rect -63 100 -33 122
+rect 33 100 63 122
+rect -63 -122 -33 -100
+rect 33 -122 63 -100
+<< locali >>
+rect -113 62 -79 78
+rect -113 -78 -79 -62
+rect -17 62 17 78
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -78 113 -62
+<< viali >>
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+<< metal1 >>
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+<< properties >>
+string gencell sky130_fd_pr__nfet_01v8
+string library sky130
+string parameters w 1 l 0.150 m 1 nf 2 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__nfet_01v8 sky130_fd_pr__nfet_01v8_lvt sky130_fd_bs_flash__special_sonosfet_star sky130_fd_pr__nfet_g5v0d10v5 sky130_fd_pr__nfet_05v0_nvt sky130_fd_pr__nfet_03v3_nvt} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git "a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext" "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext"
new file mode 100755
index 0000000..d01e740
--- /dev/null
+++ "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.ext"
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n726#" 17 38.7278 -261 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_217_n290#" 15 44.2028 217 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n290#" 19 39.5848 -261 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2016 184 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_229_174#" 18 22.8948 229 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1700 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_174#" 25 20.6228 -261 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1200 148 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 753 -173.43 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 694 -173.43 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 1931 -368.685 -129 -100 pdif 0 0 0 0 0 0 0 0 0 0 26400 1064 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24300 1440 13616 776 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n74#" 753 -173.43 -221 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n152#" 2233 50.032 -159 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42880 2880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n261_n210#" 2173 644.52 -261 -210 nw 0 0 0 0 214840 1868 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "a_n129_n100#" "a_n221_n74#" 264.212
+cap "w_n261_n210#" "a_n159_n152#" 352
+cap "li_225_n726#" "li_217_n290#" 3.26562
+cap "a_159_n100#" "a_n33_n100#" 102.009
+cap "w_n261_n210#" "a_n221_n74#" 207.073
+cap "a_159_n100#" "a_n129_n100#" 264.021
+cap "w_n261_n210#" "li_n261_174#" 10.8272
+cap "w_n261_n210#" "li_229_174#" 13.1177
+cap "a_n129_n100#" "a_n33_n100#" 462.239
+cap "li_n261_n290#" "li_n261_n726#" 3.09375
+cap "li_n261_174#" "a_n221_n74#" 21.2143
+cap "a_159_n100#" "w_n261_n210#" 207.073
+cap "w_n261_n210#" "a_n33_n100#" 207.073
+cap "a_n159_n152#" "a_n129_n100#" 106.141
+cap "w_n261_n210#" "a_n129_n100#" 447.025
+cap "a_159_n100#" "a_n221_n74#" 45.1613
+cap "a_n221_n74#" "a_n33_n100#" 102.009
+cap "a_159_n100#" "li_229_174#" 29.7
+cap "li_n261_174#" "a_n33_n100#" 2.7
+cap "a_n33_n100#" "li_229_174#" 2.80189
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git "a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag" "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag"
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ "b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B\0430.mag"
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -261 174 -227 224
+rect -209 140 -203 192
+rect 195 140 209 192
+rect 229 174 263 224
+rect -261 -290 -225 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 74 217 100
+rect 159 62 221 74
+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< pdiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 100 -129 138
+rect -63 100 -33 138
+rect 33 100 63 138
+rect 129 100 159 138
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect -159 -152 161 -120
+rect 15 -208 45 -152
+<< locali >>
+rect -261 174 -237 224
+rect -209 62 -175 192
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -68 -79 -62
+rect -115 -116 -79 -68
+rect -17 62 17 192
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -64 113 -62
+rect 77 -116 113 -64
+rect 175 62 209 192
+rect 229 174 263 224
+rect 175 -78 209 -62
+rect -115 -154 113 -116
+rect 61 -220 95 -154
+rect -261 -290 -225 -234
+rect 217 -290 263 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
new file mode 100755
index 0000000..0889867
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
@@ -0,0 +1,44 @@
+timestamp 1646324451
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd
+node "li_225_n726#" 17 38.7278 225 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n726#" 17 38.7278 -261 -726 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1976 180 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_217_n290#" 15 44.2028 217 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2576 204 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_n290#" 19 39.5848 -261 -290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2016 184 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_229_174#" 18 22.8948 229 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1700 168 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_n261_174#" 25 20.6228 -261 174 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1200 148 0 0 0 0 0 0 0 0 0 0 0 0
+node "a_159_n100#" 753 -173.43 159 -100 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n33_n100#" 694 -173.43 -33 -100 pdif 0 0 0 0 0 0 0 0 0 0 13200 532 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n129_n100#" 1931 -368.685 -129 -100 pdif 0 0 0 0 0 0 0 0 0 0 26400 1064 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24300 1440 13616 776 0 0 0 0 0 0 0 0 0 0
+node "a_n221_n74#" 753 -173.43 -221 -74 pdif 0 0 0 0 0 0 0 0 0 0 12192 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9180 608 6808 388 0 0 0 0 0 0 0 0 0 0
+node "a_n159_n152#" 2233 50.032 -159 -152 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42880 2880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_n261_n210#" 2173 644.52 -261 -210 nw 0 0 0 0 214840 1868 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "w_n261_n210#" "li_n261_174#" 10.8272
+cap "a_n129_n100#" "a_n159_n152#" 106.141
+cap "li_229_174#" "a_n33_n100#" 2.80189
+cap "li_229_174#" "a_159_n100#" 29.7
+cap "a_n33_n100#" "li_n261_174#" 2.7
+cap "a_n159_n152#" "w_n261_n210#" 352
+cap "a_n221_n74#" "a_n129_n100#" 264.212
+cap "a_n221_n74#" "w_n261_n210#" 207.073
+cap "a_n221_n74#" "a_n33_n100#" 102.009
+cap "a_n221_n74#" "a_159_n100#" 45.1613
+cap "a_n129_n100#" "w_n261_n210#" 447.025
+cap "a_n129_n100#" "a_n33_n100#" 462.239
+cap "a_159_n100#" "a_n129_n100#" 264.021
+cap "a_n33_n100#" "w_n261_n210#" 207.073
+cap "a_159_n100#" "w_n261_n210#" 207.073
+cap "a_n221_n74#" "li_n261_174#" 21.2143
+cap "a_159_n100#" "a_n33_n100#" 102.009
+cap "li_n261_n290#" "li_n261_n726#" 3.09375
+cap "li_225_n726#" "li_217_n290#" 3.26562
+cap "li_229_174#" "w_n261_n210#" 13.1177
+device msubckt sky130_fd_pr__pfet_01v8 129 -100 130 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_159_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 33 -100 34 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n33_n100#" 200 0 "a_n129_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -63 -100 -62 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n129_n100#" 200 0 "a_n33_n100#" 200 0
+device msubckt sky130_fd_pr__pfet_01v8 -159 -100 -158 -99 l=30 w=200 "w_n261_n210#" "a_n159_n152#" 60 0 "a_n221_n74#" 200 0 "a_n129_n100#" 200 0
diff --git a/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.mag b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
new file mode 100755
index 0000000..dced6c3
--- /dev/null
+++ b/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.mag
@@ -0,0 +1,114 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1646324451
+<< error_p >>
+rect -261 174 -227 224
+rect -209 140 -203 192
+rect 195 140 209 192
+rect 229 174 263 224
+rect -261 -290 -225 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< nwell >>
+rect -261 -210 263 200
+<< pmos >>
+rect -159 -100 -129 100
+rect -63 -100 -33 100
+rect 33 -100 63 100
+rect 129 -100 159 100
+<< pdiff >>
+rect -217 74 -159 100
+rect -221 62 -159 74
+rect -221 -62 -209 62
+rect -175 -62 -159 62
+rect -221 -74 -159 -62
+rect -217 -100 -159 -74
+rect -129 62 -63 100
+rect -129 -62 -113 62
+rect -79 -62 -63 62
+rect -129 -100 -63 -62
+rect -33 62 33 100
+rect -33 -62 -17 62
+rect 17 -62 33 62
+rect -33 -100 33 -62
+rect 63 62 129 100
+rect 63 -62 79 62
+rect 113 -62 129 62
+rect 63 -100 129 -62
+rect 159 74 217 100
+rect 159 62 221 74
+rect 159 -62 175 62
+rect 209 -62 221 62
+rect 159 -74 221 -62
+rect 159 -100 217 -74
+<< pdiffc >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< poly >>
+rect -159 100 -129 138
+rect -63 100 -33 138
+rect 33 100 63 138
+rect 129 100 159 138
+rect -159 -120 -129 -100
+rect -63 -120 -33 -100
+rect 33 -120 63 -100
+rect 129 -120 159 -100
+rect -159 -152 161 -120
+rect 15 -208 45 -152
+<< locali >>
+rect -261 174 -237 224
+rect -209 62 -175 192
+rect -209 -78 -175 -62
+rect -113 62 -79 78
+rect -113 -68 -79 -62
+rect -115 -116 -79 -68
+rect -17 62 17 192
+rect -17 -78 17 -62
+rect 79 62 113 78
+rect 79 -64 113 -62
+rect 77 -116 113 -64
+rect 175 62 209 192
+rect 229 174 263 224
+rect 175 -78 209 -62
+rect -115 -154 113 -116
+rect 61 -220 95 -154
+rect -261 -290 -225 -234
+rect 217 -290 263 -234
+rect -261 -726 -223 -674
+rect 225 -726 263 -674
+<< viali >>
+rect -209 -62 -175 62
+rect -113 -62 -79 62
+rect -17 -62 17 62
+rect 79 -62 113 62
+rect 175 -62 209 62
+<< metal1 >>
+rect -215 62 -169 74
+rect -215 -62 -209 62
+rect -175 -62 -169 62
+rect -215 -74 -169 -62
+rect -119 62 -73 74
+rect -119 -62 -113 62
+rect -79 -62 -73 62
+rect -119 -74 -73 -62
+rect -23 62 23 74
+rect -23 -62 -17 62
+rect 17 -62 23 62
+rect -23 -74 23 -62
+rect 73 62 119 74
+rect 73 -62 79 62
+rect 113 -62 119 62
+rect 73 -74 119 -62
+rect 169 62 215 74
+rect 169 -62 175 62
+rect 209 -62 215 62
+rect 169 -74 215 -62
+<< properties >>
+string gencell sky130_fd_pr__pfet_01v8
+string library sky130
+string parameters w 1 l 0.15 m 1 nf 4 diffcov 70 polycov 70 guard 0 glc 0 grc 0 gtc 0 gbc 0 tbcov 70 rlcov 70 topc 0 botc 0 poverlap 0 doverlap 1 lmin 0.15 wmin 0.42 compatible {sky130_fd_pr__pfet_01v8 sky130_fd_pr__pfet_01v8_lvt sky130_fd_pr__pfet_01v8_hvt sky130_fd_pr__pfet_g5v0d10v5} full_metal 0 viasrc 70 viadrn 70 viagate 70 viagb 0 viagr 0 viagl 0 viagt 0
+<< end >>
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
new file mode 100644
index 0000000..8f24b02
--- /dev/null
+++ b/mag/user_analog_project_wrapper.ext
@@ -0,0 +1,1700 @@
+timestamp 1647578848
+version 8.3
+tech sky130A
+style ngspice()
+scale 1000 1 500000
+resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
+use compaartor_v4 compaartor_v4_0 0 1 418238 1 0 584732
+use buffer_12 buffer_12_1 1 0 405268 0 1 587128
+use buffer_12 buffer_12_0 1 0 405246 0 1 585052
+use buffer_2#1 buffer_2_1 0 -1 467924 1 0 685646
+use buffer_2#0 buffer_2_0 0 -1 415972 1 0 685864
+use buffer_1#0 buffer_1_1 0 -1 449484 1 0 655190
+use buffer_1#0 buffer_1_0 0 -1 440884 1 0 655190
+port "io_analog[4]" 41 329294 702300 334294 704800 m5
+port "io_analog[4]" 47 318994 702300 323994 704800 m5
+port "io_analog[4]" 41 329294 702300 334294 704800 m4
+port "io_analog[4]" 47 318994 702300 323994 704800 m4
+port "io_analog[5]" 48 217294 702300 222294 704800 m4
+port "io_analog[5]" 42 227594 702300 232594 704800 m4
+port "io_analog[6]" 49 165594 702300 170594 704800 m4
+port "io_analog[6]" 43 175894 702300 180894 704800 m4
+port "io_in_3v3[0]" 83 583520 1544 584800 1656 m3
+port "io_oeb[26]" 128 -800 1544 480 1656 m3
+port "io_in[0]" 56 583520 2726 584800 2838 m3
+port "io_out[26]" 155 -800 2726 480 2838 m3
+port "io_out[0]" 137 583520 3908 584800 4020 m3
+port "io_in[26]" 74 -800 3908 480 4020 m3
+port "io_oeb[0]" 110 583520 5090 584800 5202 m3
+port "io_in_3v3[26]" 101 -800 5090 480 5202 m3
+port "io_in_3v3[1]" 94 583520 6272 584800 6384 m3
+port "io_oeb[25]" 127 -800 6272 480 6384 m3
+port "io_in[1]" 67 583520 7454 584800 7566 m3
+port "io_out[25]" 154 -800 7454 480 7566 m3
+port "io_out[1]" 148 583520 8636 584800 8748 m3
+port "io_in[25]" 73 -800 8636 480 8748 m3
+port "io_oeb[1]" 121 583520 9818 584800 9930 m3
+port "io_in_3v3[25]" 100 -800 9818 480 9930 m3
+port "io_in_3v3[2]" 102 583520 11000 584800 11112 m3
+port "io_oeb[24]" 126 -800 11000 480 11112 m3
+port "io_in[2]" 75 583520 12182 584800 12294 m3
+port "io_out[24]" 153 -800 12182 480 12294 m3
+port "io_out[2]" 156 583520 13364 584800 13476 m3
+port "io_in[24]" 72 -800 13364 480 13476 m3
+port "io_oeb[2]" 129 583520 14546 584800 14658 m3
+port "io_in_3v3[24]" 99 -800 14546 480 14658 m3
+port "io_in_3v3[3]" 103 583520 15728 584800 15840 m3
+port "gpio_noesd[17]" 26 -800 15728 480 15840 m3
+port "io_in[3]" 76 583520 16910 584800 17022 m3
+port "gpio_analog[17]" 8 -800 16910 480 17022 m3
+port "io_out[3]" 157 583520 18092 584800 18204 m3
+port "io_oeb[3]" 130 583520 19274 584800 19386 m3
+port "io_in_3v3[4]" 104 583520 20456 584800 20568 m3
+port "io_in[4]" 77 583520 21638 584800 21750 m3
+port "io_out[4]" 158 583520 22820 584800 22932 m3
+port "io_oeb[4]" 131 583520 24002 584800 24114 m3
+port "io_oeb[23]" 125 -800 32422 480 32534 m3
+port "io_out[23]" 152 -800 33604 480 33716 m3
+port "io_in[23]" 71 -800 34786 480 34898 m3
+port "io_in_3v3[23]" 98 -800 35968 480 36080 m3
+port "gpio_noesd[16]" 25 -800 37150 480 37262 m3
+port "gpio_analog[16]" 7 -800 38332 480 38444 m3
+port "io_in_3v3[5]" 105 583520 46914 584800 47026 m3
+port "io_in[5]" 78 583520 48096 584800 48208 m3
+port "io_out[5]" 159 583520 49278 584800 49390 m3
+port "io_oeb[5]" 132 583520 50460 584800 50572 m3
+port "io_oeb[22]" 124 -800 75644 480 75756 m3
+port "io_out[22]" 151 -800 76826 480 76938 m3
+port "io_in[22]" 70 -800 78008 480 78120 m3
+port "io_in_3v3[22]" 97 -800 79190 480 79302 m3
+port "gpio_noesd[15]" 24 -800 80372 480 80484 m3
+port "gpio_analog[15]" 6 -800 81554 480 81666 m3
+port "io_in_3v3[6]" 106 583520 91572 584800 91684 m3
+port "io_in[6]" 79 583520 92754 584800 92866 m3
+port "io_out[6]" 160 583520 93936 584800 94048 m3
+port "io_oeb[6]" 133 583520 95118 584800 95230 m3
+port "io_oeb[21]" 123 -800 118866 480 118978 m3
+port "io_out[21]" 150 -800 120048 480 120160 m3
+port "io_in[21]" 69 -800 121230 480 121342 m3
+port "io_in_3v3[21]" 96 -800 122412 480 122524 m3
+port "gpio_noesd[14]" 23 -800 123594 480 123706 m3
+port "gpio_analog[14]" 5 -800 124776 480 124888 m3
+port "vssa1" 565 582340 136830 584800 141630 m3
+port "vssa1" 564 582340 146830 584800 151630 m3
+port "vssd2" 571 0 162888 1660 167688 m3
+port "vssd2" 570 0 172888 1660 177688 m3
+port "vssd1" 569 582340 181430 584800 186230 m3
+port "vssd1" 568 582340 191430 584800 196230 m3
+port "vdda2" 560 0 204888 1660 209688 m3
+port "vdda2" 561 0 214888 1660 219688 m3
+port "vdda1" 559 582340 225230 584800 230030 m3
+port "vdda1" 558 582340 235230 584800 240030 m3
+port "io_oeb[20]" 122 -800 246488 480 246600 m3
+port "io_out[20]" 149 -800 247670 480 247782 m3
+port "io_in[20]" 68 -800 248852 480 248964 m3
+port "io_in_3v3[20]" 95 -800 250034 480 250146 m3
+port "gpio_noesd[13]" 22 -800 251216 480 251328 m3
+port "gpio_analog[13]" 4 -800 252398 480 252510 m3
+port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
+port "gpio_noesd[0]" 18 583520 270412 584800 270524 m3
+port "io_in_3v3[7]" 107 583520 271594 584800 271706 m3
+port "io_in[7]" 80 583520 272776 584800 272888 m3
+port "io_out[7]" 161 583520 273958 584800 274070 m3
+port "io_oeb[7]" 134 583520 275140 584800 275252 m3
+port "io_oeb[19]" 120 -800 289510 480 289622 m3
+port "io_out[19]" 147 -800 290692 480 290804 m3
+port "io_in[19]" 66 -800 291874 480 291986 m3
+port "io_in_3v3[19]" 93 -800 293056 480 293168 m3
+port "gpio_noesd[12]" 21 -800 294238 480 294350 m3
+port "gpio_analog[12]" 3 -800 295420 480 295532 m3
+port "gpio_analog[1]" 9 583520 313652 584800 313764 m3
+port "gpio_noesd[1]" 27 583520 314834 584800 314946 m3
+port "io_in_3v3[8]" 108 583520 316016 584800 316128 m3
+port "io_in[8]" 81 583520 317198 584800 317310 m3
+port "io_out[8]" 162 583520 318380 584800 318492 m3
+port "io_oeb[8]" 135 583520 319562 584800 319674 m3
+port "io_oeb[18]" 119 -800 332732 480 332844 m3
+port "io_out[18]" 146 -800 333914 480 334026 m3
+port "io_in[18]" 65 -800 335096 480 335208 m3
+port "io_in_3v3[18]" 92 -800 336278 480 336390 m3
+port "gpio_noesd[11]" 20 -800 337460 480 337572 m3
+port "gpio_analog[11]" 2 -800 338642 480 338754 m3
+port "gpio_analog[2]" 10 583520 358874 584800 358986 m3
+port "gpio_noesd[2]" 28 583520 360056 584800 360168 m3
+port "io_in_3v3[9]" 109 583520 361238 584800 361350 m3
+port "io_in[9]" 82 583520 362420 584800 362532 m3
+port "io_out[9]" 163 583520 363602 584800 363714 m3
+port "io_oeb[9]" 136 583520 364784 584800 364896 m3
+port "io_oeb[17]" 118 -800 375954 480 376066 m3
+port "io_out[17]" 145 -800 377136 480 377248 m3
+port "io_in[17]" 64 -800 378318 480 378430 m3
+port "io_in_3v3[17]" 91 -800 379500 480 379612 m3
+port "gpio_noesd[10]" 19 -800 380682 480 380794 m3
+port "gpio_analog[10]" 1 -800 381864 480 381976 m3
+port "gpio_analog[3]" 11 583520 405296 584800 405408 m3
+port "gpio_noesd[3]" 29 583520 406478 584800 406590 m3
+port "io_in_3v3[10]" 84 583520 407660 584800 407772 m3
+port "io_in[10]" 57 583520 408842 584800 408954 m3
+port "io_out[10]" 138 583520 410024 584800 410136 m3
+port "io_oeb[10]" 111 583520 411206 584800 411318 m3
+port "io_oeb[16]" 117 -800 419176 480 419288 m3
+port "io_out[16]" 144 -800 420358 480 420470 m3
+port "io_in[16]" 63 -800 421540 480 421652 m3
+port "io_in_3v3[16]" 90 -800 422722 480 422834 m3
+port "gpio_noesd[9]" 35 -800 423904 480 424016 m3
+port "gpio_analog[9]" 17 -800 425086 480 425198 m3
+port "gpio_analog[4]" 12 583520 449718 584800 449830 m3
+port "gpio_noesd[4]" 30 583520 450900 584800 451012 m3
+port "io_in_3v3[11]" 85 583520 452082 584800 452194 m3
+port "io_in[11]" 58 583520 453264 584800 453376 m3
+port "io_out[11]" 139 583520 454446 584800 454558 m3
+port "io_oeb[11]" 112 583520 455628 584800 455740 m3
+port "io_oeb[15]" 116 -800 462398 480 462510 m3
+port "io_out[15]" 143 -800 463580 480 463692 m3
+port "io_in[15]" 62 -800 464762 480 464874 m3
+port "io_in_3v3[15]" 89 -800 465944 480 466056 m3
+port "gpio_noesd[8]" 34 -800 467126 480 467238 m3
+port "gpio_analog[8]" 16 -800 468308 480 468420 m3
+port "gpio_analog[5]" 13 583520 494140 584800 494252 m3
+port "gpio_noesd[5]" 31 583520 495322 584800 495434 m3
+port "io_in_3v3[12]" 86 583520 496504 584800 496616 m3
+port "io_in[12]" 59 583520 497686 584800 497798 m3
+port "io_out[12]" 140 583520 498868 584800 498980 m3
+port "io_oeb[12]" 113 583520 500050 584800 500162 m3
+port "io_oeb[14]" 115 -800 505620 480 505732 m3
+port "io_out[14]" 142 -800 506802 480 506914 m3
+port "io_in[14]" 61 -800 507984 480 508096 m3
+port "io_in_3v3[14]" 88 -800 509166 480 509278 m3
+port "gpio_noesd[7]" 33 -800 510348 480 510460 m3
+port "gpio_analog[7]" 15 -800 511530 480 511642 m3
+port "vdda1" 556 582340 540562 584800 545362 m3
+port "vdda1" 557 582340 550562 584800 555362 m3
+port "vssa2" 567 0 549442 1660 554242 m3
+port "vssa2" 566 0 559442 1660 564242 m3
+port "gpio_analog[6]" 14 583520 583562 584800 583674 m3
+port "gpio_noesd[6]" 32 583520 584744 584800 584856 m3
+port "io_in_3v3[13]" 87 583520 585926 584800 586038 m3
+port "io_in[13]" 60 583520 587108 584800 587220 m3
+port "io_out[13]" 141 583520 588290 584800 588402 m3
+port "io_oeb[13]" 114 583520 589472 584800 589584 m3
+port "io_analog[0]" 36 582300 677984 584800 682984 m3
+port "io_analog[1]" 38 566594 702300 571594 704800 m3
+port "io_analog[4]" 41 329294 702300 334294 704800 m3
+port "io_clamp_high[0]" 50 326794 702300 328994 704800 m3
+port "io_clamp_low[0]" 53 324294 702300 326494 704800 m3
+port "io_analog[4]" 47 318994 702300 323994 704800 m3
+port "io_analog[5]" 42 227594 702300 232594 704800 m3
+port "io_analog[5]" 48 217294 702300 222294 704800 m3
+port "io_analog[6]" 43 175894 702300 180894 704800 m3
+port "io_analog[6]" 49 165594 702300 170594 704800 m3
+port "vccd2" 555 0 633842 1660 638642 m3
+port "vccd2" 554 0 643842 1660 648642 m3
+port "io_analog[10]" 37 0 680242 1700 685242 m3
+port "io_analog[9]" 46 16194 702300 21194 704800 m3
+port "user_irq[2]" 551 583250 -800 583362 480 m2
+port "user_irq[1]" 550 582068 -800 582180 480 m2
+port "user_irq[0]" 549 580886 -800 580998 480 m2
+port "user_clock2" 548 579704 -800 579816 480 m2
+port "la_oenb[127]" 450 578522 -800 578634 480 m2
+port "la_data_out[127]" 322 577340 -800 577452 480 m2
+port "la_data_in[127]" 194 576158 -800 576270 480 m2
+port "la_oenb[126]" 449 574976 -800 575088 480 m2
+port "la_data_out[126]" 321 573794 -800 573906 480 m2
+port "la_data_in[126]" 193 572612 -800 572724 480 m2
+port "la_oenb[125]" 448 571430 -800 571542 480 m2
+port "la_data_out[125]" 320 570248 -800 570360 480 m2
+port "la_data_in[125]" 192 569066 -800 569178 480 m2
+port "la_oenb[124]" 447 567884 -800 567996 480 m2
+port "la_data_out[124]" 319 566702 -800 566814 480 m2
+port "la_data_in[124]" 191 565520 -800 565632 480 m2
+port "la_oenb[123]" 446 564338 -800 564450 480 m2
+port "la_data_out[123]" 318 563156 -800 563268 480 m2
+port "la_data_in[123]" 190 561974 -800 562086 480 m2
+port "la_oenb[122]" 445 560792 -800 560904 480 m2
+port "la_data_out[122]" 317 559610 -800 559722 480 m2
+port "la_data_in[122]" 189 558428 -800 558540 480 m2
+port "la_oenb[121]" 444 557246 -800 557358 480 m2
+port "la_data_out[121]" 316 556064 -800 556176 480 m2
+port "la_data_in[121]" 188 554882 -800 554994 480 m2
+port "la_oenb[120]" 443 553700 -800 553812 480 m2
+port "la_data_out[120]" 315 552518 -800 552630 480 m2
+port "la_data_in[120]" 187 551336 -800 551448 480 m2
+port "la_oenb[119]" 441 550154 -800 550266 480 m2
+port "la_data_out[119]" 313 548972 -800 549084 480 m2
+port "la_data_in[119]" 185 547790 -800 547902 480 m2
+port "la_oenb[118]" 440 546608 -800 546720 480 m2
+port "la_data_out[118]" 312 545426 -800 545538 480 m2
+port "la_data_in[118]" 184 544244 -800 544356 480 m2
+port "la_oenb[117]" 439 543062 -800 543174 480 m2
+port "la_data_out[117]" 311 541880 -800 541992 480 m2
+port "la_data_in[117]" 183 540698 -800 540810 480 m2
+port "la_oenb[116]" 438 539516 -800 539628 480 m2
+port "la_data_out[116]" 310 538334 -800 538446 480 m2
+port "la_data_in[116]" 182 537152 -800 537264 480 m2
+port "la_oenb[115]" 437 535970 -800 536082 480 m2
+port "la_data_out[115]" 309 534788 -800 534900 480 m2
+port "la_data_in[115]" 181 533606 -800 533718 480 m2
+port "la_oenb[114]" 436 532424 -800 532536 480 m2
+port "la_data_out[114]" 308 531242 -800 531354 480 m2
+port "la_data_in[114]" 180 530060 -800 530172 480 m2
+port "la_oenb[113]" 435 528878 -800 528990 480 m2
+port "la_data_out[113]" 307 527696 -800 527808 480 m2
+port "la_data_in[113]" 179 526514 -800 526626 480 m2
+port "la_oenb[112]" 434 525332 -800 525444 480 m2
+port "la_data_out[112]" 306 524150 -800 524262 480 m2
+port "la_data_in[112]" 178 522968 -800 523080 480 m2
+port "la_oenb[111]" 433 521786 -800 521898 480 m2
+port "la_data_out[111]" 305 520604 -800 520716 480 m2
+port "la_data_in[111]" 177 519422 -800 519534 480 m2
+port "la_oenb[110]" 432 518240 -800 518352 480 m2
+port "la_data_out[110]" 304 517058 -800 517170 480 m2
+port "la_data_in[110]" 176 515876 -800 515988 480 m2
+port "la_oenb[109]" 430 514694 -800 514806 480 m2
+port "la_data_out[109]" 302 513512 -800 513624 480 m2
+port "la_data_in[109]" 174 512330 -800 512442 480 m2
+port "la_oenb[108]" 429 511148 -800 511260 480 m2
+port "la_data_out[108]" 301 509966 -800 510078 480 m2
+port "la_data_in[108]" 173 508784 -800 508896 480 m2
+port "la_oenb[107]" 428 507602 -800 507714 480 m2
+port "la_data_out[107]" 300 506420 -800 506532 480 m2
+port "la_data_in[107]" 172 505238 -800 505350 480 m2
+port "la_oenb[106]" 427 504056 -800 504168 480 m2
+port "la_data_out[106]" 299 502874 -800 502986 480 m2
+port "la_data_in[106]" 171 501692 -800 501804 480 m2
+port "la_oenb[105]" 426 500510 -800 500622 480 m2
+port "la_data_out[105]" 298 499328 -800 499440 480 m2
+port "la_data_in[105]" 170 498146 -800 498258 480 m2
+port "la_oenb[104]" 425 496964 -800 497076 480 m2
+port "la_data_out[104]" 297 495782 -800 495894 480 m2
+port "la_data_in[104]" 169 494600 -800 494712 480 m2
+port "la_oenb[103]" 424 493418 -800 493530 480 m2
+port "la_data_out[103]" 296 492236 -800 492348 480 m2
+port "la_data_in[103]" 168 491054 -800 491166 480 m2
+port "la_oenb[102]" 423 489872 -800 489984 480 m2
+port "la_data_out[102]" 295 488690 -800 488802 480 m2
+port "la_data_in[102]" 167 487508 -800 487620 480 m2
+port "la_oenb[101]" 422 486326 -800 486438 480 m2
+port "la_data_out[101]" 294 485144 -800 485256 480 m2
+port "la_data_in[101]" 166 483962 -800 484074 480 m2
+port "la_oenb[100]" 421 482780 -800 482892 480 m2
+port "la_data_out[100]" 293 481598 -800 481710 480 m2
+port "la_data_in[100]" 165 480416 -800 480528 480 m2
+port "la_oenb[99]" 546 479234 -800 479346 480 m2
+port "la_data_out[99]" 418 478052 -800 478164 480 m2
+port "la_data_in[99]" 290 476870 -800 476982 480 m2
+port "la_oenb[98]" 545 475688 -800 475800 480 m2
+port "la_data_out[98]" 417 474506 -800 474618 480 m2
+port "la_data_in[98]" 289 473324 -800 473436 480 m2
+port "la_oenb[97]" 544 472142 -800 472254 480 m2
+port "la_data_out[97]" 416 470960 -800 471072 480 m2
+port "la_data_in[97]" 288 469778 -800 469890 480 m2
+port "la_oenb[96]" 543 468596 -800 468708 480 m2
+port "la_data_out[96]" 415 467414 -800 467526 480 m2
+port "la_data_in[96]" 287 466232 -800 466344 480 m2
+port "la_oenb[95]" 542 465050 -800 465162 480 m2
+port "la_data_out[95]" 414 463868 -800 463980 480 m2
+port "la_data_in[95]" 286 462686 -800 462798 480 m2
+port "la_oenb[94]" 541 461504 -800 461616 480 m2
+port "la_data_out[94]" 413 460322 -800 460434 480 m2
+port "la_data_in[94]" 285 459140 -800 459252 480 m2
+port "la_oenb[93]" 540 457958 -800 458070 480 m2
+port "la_data_out[93]" 412 456776 -800 456888 480 m2
+port "la_data_in[93]" 284 455594 -800 455706 480 m2
+port "la_oenb[92]" 539 454412 -800 454524 480 m2
+port "la_data_out[92]" 411 453230 -800 453342 480 m2
+port "la_data_in[92]" 283 452048 -800 452160 480 m2
+port "la_oenb[91]" 538 450866 -800 450978 480 m2
+port "la_data_out[91]" 410 449684 -800 449796 480 m2
+port "la_data_in[91]" 282 448502 -800 448614 480 m2
+port "la_oenb[90]" 537 447320 -800 447432 480 m2
+port "la_data_out[90]" 409 446138 -800 446250 480 m2
+port "la_data_in[90]" 281 444956 -800 445068 480 m2
+port "la_oenb[89]" 535 443774 -800 443886 480 m2
+port "la_data_out[89]" 407 442592 -800 442704 480 m2
+port "la_data_in[89]" 279 441410 -800 441522 480 m2
+port "la_oenb[88]" 534 440228 -800 440340 480 m2
+port "la_data_out[88]" 406 439046 -800 439158 480 m2
+port "la_data_in[88]" 278 437864 -800 437976 480 m2
+port "la_oenb[87]" 533 436682 -800 436794 480 m2
+port "la_data_out[87]" 405 435500 -800 435612 480 m2
+port "la_data_in[87]" 277 434318 -800 434430 480 m2
+port "la_oenb[86]" 532 433136 -800 433248 480 m2
+port "la_data_out[86]" 404 431954 -800 432066 480 m2
+port "la_data_in[86]" 276 430772 -800 430884 480 m2
+port "la_oenb[85]" 531 429590 -800 429702 480 m2
+port "la_data_out[85]" 403 428408 -800 428520 480 m2
+port "la_data_in[85]" 275 427226 -800 427338 480 m2
+port "la_oenb[84]" 530 426044 -800 426156 480 m2
+port "la_data_out[84]" 402 424862 -800 424974 480 m2
+port "la_data_in[84]" 274 423680 -800 423792 480 m2
+port "la_oenb[83]" 529 422498 -800 422610 480 m2
+port "la_data_out[83]" 401 421316 -800 421428 480 m2
+port "la_data_in[83]" 273 420134 -800 420246 480 m2
+port "la_oenb[82]" 528 418952 -800 419064 480 m2
+port "la_data_out[82]" 400 417770 -800 417882 480 m2
+port "la_data_in[82]" 272 416588 -800 416700 480 m2
+port "la_oenb[81]" 527 415406 -800 415518 480 m2
+port "la_data_out[81]" 399 414224 -800 414336 480 m2
+port "la_data_in[81]" 271 413042 -800 413154 480 m2
+port "la_oenb[80]" 526 411860 -800 411972 480 m2
+port "la_data_out[80]" 398 410678 -800 410790 480 m2
+port "la_data_in[80]" 270 409496 -800 409608 480 m2
+port "la_oenb[79]" 524 408314 -800 408426 480 m2
+port "la_data_out[79]" 396 407132 -800 407244 480 m2
+port "la_data_in[79]" 268 405950 -800 406062 480 m2
+port "la_oenb[78]" 523 404768 -800 404880 480 m2
+port "la_data_out[78]" 395 403586 -800 403698 480 m2
+port "la_data_in[78]" 267 402404 -800 402516 480 m2
+port "la_oenb[77]" 522 401222 -800 401334 480 m2
+port "la_data_out[77]" 394 400040 -800 400152 480 m2
+port "la_data_in[77]" 266 398858 -800 398970 480 m2
+port "la_oenb[76]" 521 397676 -800 397788 480 m2
+port "la_data_out[76]" 393 396494 -800 396606 480 m2
+port "la_data_in[76]" 265 395312 -800 395424 480 m2
+port "la_oenb[75]" 520 394130 -800 394242 480 m2
+port "la_data_out[75]" 392 392948 -800 393060 480 m2
+port "la_data_in[75]" 264 391766 -800 391878 480 m2
+port "la_oenb[74]" 519 390584 -800 390696 480 m2
+port "la_data_out[74]" 391 389402 -800 389514 480 m2
+port "la_data_in[74]" 263 388220 -800 388332 480 m2
+port "la_oenb[73]" 518 387038 -800 387150 480 m2
+port "la_data_out[73]" 390 385856 -800 385968 480 m2
+port "la_data_in[73]" 262 384674 -800 384786 480 m2
+port "la_oenb[72]" 517 383492 -800 383604 480 m2
+port "la_data_out[72]" 389 382310 -800 382422 480 m2
+port "la_data_in[72]" 261 381128 -800 381240 480 m2
+port "la_oenb[71]" 516 379946 -800 380058 480 m2
+port "la_data_out[71]" 388 378764 -800 378876 480 m2
+port "la_data_in[71]" 260 377582 -800 377694 480 m2
+port "la_oenb[70]" 515 376400 -800 376512 480 m2
+port "la_data_out[70]" 387 375218 -800 375330 480 m2
+port "la_data_in[70]" 259 374036 -800 374148 480 m2
+port "la_oenb[69]" 513 372854 -800 372966 480 m2
+port "la_data_out[69]" 385 371672 -800 371784 480 m2
+port "la_data_in[69]" 257 370490 -800 370602 480 m2
+port "la_oenb[68]" 512 369308 -800 369420 480 m2
+port "la_data_out[68]" 384 368126 -800 368238 480 m2
+port "la_data_in[68]" 256 366944 -800 367056 480 m2
+port "la_oenb[67]" 511 365762 -800 365874 480 m2
+port "la_data_out[67]" 383 364580 -800 364692 480 m2
+port "la_data_in[67]" 255 363398 -800 363510 480 m2
+port "la_oenb[66]" 510 362216 -800 362328 480 m2
+port "la_data_out[66]" 382 361034 -800 361146 480 m2
+port "la_data_in[66]" 254 359852 -800 359964 480 m2
+port "la_oenb[65]" 509 358670 -800 358782 480 m2
+port "la_data_out[65]" 381 357488 -800 357600 480 m2
+port "la_data_in[65]" 253 356306 -800 356418 480 m2
+port "la_oenb[64]" 508 355124 -800 355236 480 m2
+port "la_data_out[64]" 380 353942 -800 354054 480 m2
+port "la_data_in[64]" 252 352760 -800 352872 480 m2
+port "la_oenb[63]" 507 351578 -800 351690 480 m2
+port "la_data_out[63]" 379 350396 -800 350508 480 m2
+port "la_data_in[63]" 251 349214 -800 349326 480 m2
+port "la_oenb[62]" 506 348032 -800 348144 480 m2
+port "la_data_out[62]" 378 346850 -800 346962 480 m2
+port "la_data_in[62]" 250 345668 -800 345780 480 m2
+port "la_oenb[61]" 505 344486 -800 344598 480 m2
+port "la_data_out[61]" 377 343304 -800 343416 480 m2
+port "la_data_in[61]" 249 342122 -800 342234 480 m2
+port "la_oenb[60]" 504 340940 -800 341052 480 m2
+port "la_data_out[60]" 376 339758 -800 339870 480 m2
+port "la_data_in[60]" 248 338576 -800 338688 480 m2
+port "la_oenb[59]" 502 337394 -800 337506 480 m2
+port "la_data_out[59]" 374 336212 -800 336324 480 m2
+port "la_data_in[59]" 246 335030 -800 335142 480 m2
+port "la_oenb[58]" 501 333848 -800 333960 480 m2
+port "la_data_out[58]" 373 332666 -800 332778 480 m2
+port "la_data_in[58]" 245 331484 -800 331596 480 m2
+port "la_oenb[57]" 500 330302 -800 330414 480 m2
+port "la_data_out[57]" 372 329120 -800 329232 480 m2
+port "la_data_in[57]" 244 327938 -800 328050 480 m2
+port "la_oenb[56]" 499 326756 -800 326868 480 m2
+port "la_data_out[56]" 371 325574 -800 325686 480 m2
+port "la_data_in[56]" 243 324392 -800 324504 480 m2
+port "la_oenb[55]" 498 323210 -800 323322 480 m2
+port "la_data_out[55]" 370 322028 -800 322140 480 m2
+port "la_data_in[55]" 242 320846 -800 320958 480 m2
+port "la_oenb[54]" 497 319664 -800 319776 480 m2
+port "la_data_out[54]" 369 318482 -800 318594 480 m2
+port "la_data_in[54]" 241 317300 -800 317412 480 m2
+port "la_oenb[53]" 496 316118 -800 316230 480 m2
+port "la_data_out[53]" 368 314936 -800 315048 480 m2
+port "la_data_in[53]" 240 313754 -800 313866 480 m2
+port "la_oenb[52]" 495 312572 -800 312684 480 m2
+port "la_data_out[52]" 367 311390 -800 311502 480 m2
+port "la_data_in[52]" 239 310208 -800 310320 480 m2
+port "la_oenb[51]" 494 309026 -800 309138 480 m2
+port "la_data_out[51]" 366 307844 -800 307956 480 m2
+port "la_data_in[51]" 238 306662 -800 306774 480 m2
+port "la_oenb[50]" 493 305480 -800 305592 480 m2
+port "la_data_out[50]" 365 304298 -800 304410 480 m2
+port "la_data_in[50]" 237 303116 -800 303228 480 m2
+port "la_oenb[49]" 491 301934 -800 302046 480 m2
+port "la_data_out[49]" 363 300752 -800 300864 480 m2
+port "la_data_in[49]" 235 299570 -800 299682 480 m2
+port "la_oenb[48]" 490 298388 -800 298500 480 m2
+port "la_data_out[48]" 362 297206 -800 297318 480 m2
+port "la_data_in[48]" 234 296024 -800 296136 480 m2
+port "la_oenb[47]" 489 294842 -800 294954 480 m2
+port "la_data_out[47]" 361 293660 -800 293772 480 m2
+port "la_data_in[47]" 233 292478 -800 292590 480 m2
+port "la_oenb[46]" 488 291296 -800 291408 480 m2
+port "la_data_out[46]" 360 290114 -800 290226 480 m2
+port "la_data_in[46]" 232 288932 -800 289044 480 m2
+port "la_oenb[45]" 487 287750 -800 287862 480 m2
+port "la_data_out[45]" 359 286568 -800 286680 480 m2
+port "la_data_in[45]" 231 285386 -800 285498 480 m2
+port "la_oenb[44]" 486 284204 -800 284316 480 m2
+port "la_data_out[44]" 358 283022 -800 283134 480 m2
+port "la_data_in[44]" 230 281840 -800 281952 480 m2
+port "la_oenb[43]" 485 280658 -800 280770 480 m2
+port "la_data_out[43]" 357 279476 -800 279588 480 m2
+port "la_data_in[43]" 229 278294 -800 278406 480 m2
+port "la_oenb[42]" 484 277112 -800 277224 480 m2
+port "la_data_out[42]" 356 275930 -800 276042 480 m2
+port "la_data_in[42]" 228 274748 -800 274860 480 m2
+port "la_oenb[41]" 483 273566 -800 273678 480 m2
+port "la_data_out[41]" 355 272384 -800 272496 480 m2
+port "la_data_in[41]" 227 271202 -800 271314 480 m2
+port "la_oenb[40]" 482 270020 -800 270132 480 m2
+port "la_data_out[40]" 354 268838 -800 268950 480 m2
+port "la_data_in[40]" 226 267656 -800 267768 480 m2
+port "la_oenb[39]" 480 266474 -800 266586 480 m2
+port "la_data_out[39]" 352 265292 -800 265404 480 m2
+port "la_data_in[39]" 224 264110 -800 264222 480 m2
+port "la_oenb[38]" 479 262928 -800 263040 480 m2
+port "la_data_out[38]" 351 261746 -800 261858 480 m2
+port "la_data_in[38]" 223 260564 -800 260676 480 m2
+port "la_oenb[37]" 478 259382 -800 259494 480 m2
+port "la_data_out[37]" 350 258200 -800 258312 480 m2
+port "la_data_in[37]" 222 257018 -800 257130 480 m2
+port "la_oenb[36]" 477 255836 -800 255948 480 m2
+port "la_data_out[36]" 349 254654 -800 254766 480 m2
+port "la_data_in[36]" 221 253472 -800 253584 480 m2
+port "la_oenb[35]" 476 252290 -800 252402 480 m2
+port "la_data_out[35]" 348 251108 -800 251220 480 m2
+port "la_data_in[35]" 220 249926 -800 250038 480 m2
+port "la_oenb[34]" 475 248744 -800 248856 480 m2
+port "la_data_out[34]" 347 247562 -800 247674 480 m2
+port "la_data_in[34]" 219 246380 -800 246492 480 m2
+port "la_oenb[33]" 474 245198 -800 245310 480 m2
+port "la_data_out[33]" 346 244016 -800 244128 480 m2
+port "la_data_in[33]" 218 242834 -800 242946 480 m2
+port "la_oenb[32]" 473 241652 -800 241764 480 m2
+port "la_data_out[32]" 345 240470 -800 240582 480 m2
+port "la_data_in[32]" 217 239288 -800 239400 480 m2
+port "la_oenb[31]" 472 238106 -800 238218 480 m2
+port "la_data_out[31]" 344 236924 -800 237036 480 m2
+port "la_data_in[31]" 216 235742 -800 235854 480 m2
+port "la_oenb[30]" 471 234560 -800 234672 480 m2
+port "la_data_out[30]" 343 233378 -800 233490 480 m2
+port "la_data_in[30]" 215 232196 -800 232308 480 m2
+port "la_oenb[29]" 469 231014 -800 231126 480 m2
+port "la_data_out[29]" 341 229832 -800 229944 480 m2
+port "la_data_in[29]" 213 228650 -800 228762 480 m2
+port "la_oenb[28]" 468 227468 -800 227580 480 m2
+port "la_data_out[28]" 340 226286 -800 226398 480 m2
+port "la_data_in[28]" 212 225104 -800 225216 480 m2
+port "la_oenb[27]" 467 223922 -800 224034 480 m2
+port "la_data_out[27]" 339 222740 -800 222852 480 m2
+port "la_data_in[27]" 211 221558 -800 221670 480 m2
+port "la_oenb[26]" 466 220376 -800 220488 480 m2
+port "la_data_out[26]" 338 219194 -800 219306 480 m2
+port "la_data_in[26]" 210 218012 -800 218124 480 m2
+port "la_oenb[25]" 465 216830 -800 216942 480 m2
+port "la_data_out[25]" 337 215648 -800 215760 480 m2
+port "la_data_in[25]" 209 214466 -800 214578 480 m2
+port "la_oenb[24]" 464 213284 -800 213396 480 m2
+port "la_data_out[24]" 336 212102 -800 212214 480 m2
+port "la_data_in[24]" 208 210920 -800 211032 480 m2
+port "la_oenb[23]" 463 209738 -800 209850 480 m2
+port "la_data_out[23]" 335 208556 -800 208668 480 m2
+port "la_data_in[23]" 207 207374 -800 207486 480 m2
+port "la_oenb[22]" 462 206192 -800 206304 480 m2
+port "la_data_out[22]" 334 205010 -800 205122 480 m2
+port "la_data_in[22]" 206 203828 -800 203940 480 m2
+port "la_oenb[21]" 461 202646 -800 202758 480 m2
+port "la_data_out[21]" 333 201464 -800 201576 480 m2
+port "la_data_in[21]" 205 200282 -800 200394 480 m2
+port "la_oenb[20]" 460 199100 -800 199212 480 m2
+port "la_data_out[20]" 332 197918 -800 198030 480 m2
+port "la_data_in[20]" 204 196736 -800 196848 480 m2
+port "la_oenb[19]" 458 195554 -800 195666 480 m2
+port "la_data_out[19]" 330 194372 -800 194484 480 m2
+port "la_data_in[19]" 202 193190 -800 193302 480 m2
+port "la_oenb[18]" 457 192008 -800 192120 480 m2
+port "la_data_out[18]" 329 190826 -800 190938 480 m2
+port "la_data_in[18]" 201 189644 -800 189756 480 m2
+port "la_oenb[17]" 456 188462 -800 188574 480 m2
+port "la_data_out[17]" 328 187280 -800 187392 480 m2
+port "la_data_in[17]" 200 186098 -800 186210 480 m2
+port "la_oenb[16]" 455 184916 -800 185028 480 m2
+port "la_data_out[16]" 327 183734 -800 183846 480 m2
+port "la_data_in[16]" 199 182552 -800 182664 480 m2
+port "la_oenb[15]" 454 181370 -800 181482 480 m2
+port "la_data_out[15]" 326 180188 -800 180300 480 m2
+port "la_data_in[15]" 198 179006 -800 179118 480 m2
+port "la_oenb[14]" 453 177824 -800 177936 480 m2
+port "la_data_out[14]" 325 176642 -800 176754 480 m2
+port "la_data_in[14]" 197 175460 -800 175572 480 m2
+port "la_oenb[13]" 452 174278 -800 174390 480 m2
+port "la_data_out[13]" 324 173096 -800 173208 480 m2
+port "la_data_in[13]" 196 171914 -800 172026 480 m2
+port "la_oenb[12]" 451 170732 -800 170844 480 m2
+port "la_data_out[12]" 323 169550 -800 169662 480 m2
+port "la_data_in[12]" 195 168368 -800 168480 480 m2
+port "la_oenb[11]" 442 167186 -800 167298 480 m2
+port "la_data_out[11]" 314 166004 -800 166116 480 m2
+port "la_data_in[11]" 186 164822 -800 164934 480 m2
+port "la_oenb[10]" 431 163640 -800 163752 480 m2
+port "la_data_out[10]" 303 162458 -800 162570 480 m2
+port "la_data_in[10]" 175 161276 -800 161388 480 m2
+port "la_oenb[9]" 547 160094 -800 160206 480 m2
+port "la_data_out[9]" 419 158912 -800 159024 480 m2
+port "la_data_in[9]" 291 157730 -800 157842 480 m2
+port "la_oenb[8]" 536 156548 -800 156660 480 m2
+port "la_data_out[8]" 408 155366 -800 155478 480 m2
+port "la_data_in[8]" 280 154184 -800 154296 480 m2
+port "la_oenb[7]" 525 153002 -800 153114 480 m2
+port "la_data_out[7]" 397 151820 -800 151932 480 m2
+port "la_data_in[7]" 269 150638 -800 150750 480 m2
+port "la_oenb[6]" 514 149456 -800 149568 480 m2
+port "la_data_out[6]" 386 148274 -800 148386 480 m2
+port "la_data_in[6]" 258 147092 -800 147204 480 m2
+port "la_oenb[5]" 503 145910 -800 146022 480 m2
+port "la_data_out[5]" 375 144728 -800 144840 480 m2
+port "la_data_in[5]" 247 143546 -800 143658 480 m2
+port "la_oenb[4]" 492 142364 -800 142476 480 m2
+port "la_data_out[4]" 364 141182 -800 141294 480 m2
+port "la_data_in[4]" 236 140000 -800 140112 480 m2
+port "la_oenb[3]" 481 138818 -800 138930 480 m2
+port "la_data_out[3]" 353 137636 -800 137748 480 m2
+port "la_data_in[3]" 225 136454 -800 136566 480 m2
+port "la_oenb[2]" 470 135272 -800 135384 480 m2
+port "la_data_out[2]" 342 134090 -800 134202 480 m2
+port "la_data_in[2]" 214 132908 -800 133020 480 m2
+port "la_oenb[1]" 459 131726 -800 131838 480 m2
+port "la_data_out[1]" 331 130544 -800 130656 480 m2
+port "la_data_in[1]" 203 129362 -800 129474 480 m2
+port "la_oenb[0]" 420 128180 -800 128292 480 m2
+port "la_data_out[0]" 292 126998 -800 127110 480 m2
+port "la_data_in[0]" 164 125816 -800 125928 480 m2
+port "wbs_dat_o[31]" 664 124634 -800 124746 480 m2
+port "wbs_dat_i[31]" 632 123452 -800 123564 480 m2
+port "wbs_adr_i[31]" 599 122270 -800 122382 480 m2
+port "wbs_dat_o[30]" 663 121088 -800 121200 480 m2
+port "wbs_dat_i[30]" 631 119906 -800 120018 480 m2
+port "wbs_adr_i[30]" 598 118724 -800 118836 480 m2
+port "wbs_dat_o[29]" 661 117542 -800 117654 480 m2
+port "wbs_dat_i[29]" 629 116360 -800 116472 480 m2
+port "wbs_adr_i[29]" 596 115178 -800 115290 480 m2
+port "wbs_dat_o[28]" 660 113996 -800 114108 480 m2
+port "wbs_dat_i[28]" 628 112814 -800 112926 480 m2
+port "wbs_adr_i[28]" 595 111632 -800 111744 480 m2
+port "wbs_dat_o[27]" 659 110450 -800 110562 480 m2
+port "wbs_dat_i[27]" 627 109268 -800 109380 480 m2
+port "wbs_adr_i[27]" 594 108086 -800 108198 480 m2
+port "wbs_dat_o[26]" 658 106904 -800 107016 480 m2
+port "wbs_dat_i[26]" 626 105722 -800 105834 480 m2
+port "wbs_adr_i[26]" 593 104540 -800 104652 480 m2
+port "wbs_dat_o[25]" 657 103358 -800 103470 480 m2
+port "wbs_dat_i[25]" 625 102176 -800 102288 480 m2
+port "wbs_adr_i[25]" 592 100994 -800 101106 480 m2
+port "wbs_dat_o[24]" 656 99812 -800 99924 480 m2
+port "wbs_dat_i[24]" 624 98630 -800 98742 480 m2
+port "wbs_adr_i[24]" 591 97448 -800 97560 480 m2
+port "wbs_dat_o[23]" 655 96266 -800 96378 480 m2
+port "wbs_dat_i[23]" 623 95084 -800 95196 480 m2
+port "wbs_adr_i[23]" 590 93902 -800 94014 480 m2
+port "wbs_dat_o[22]" 654 92720 -800 92832 480 m2
+port "wbs_dat_i[22]" 622 91538 -800 91650 480 m2
+port "wbs_adr_i[22]" 589 90356 -800 90468 480 m2
+port "wbs_dat_o[21]" 653 89174 -800 89286 480 m2
+port "wbs_dat_i[21]" 621 87992 -800 88104 480 m2
+port "wbs_adr_i[21]" 588 86810 -800 86922 480 m2
+port "wbs_dat_o[20]" 652 85628 -800 85740 480 m2
+port "wbs_dat_i[20]" 620 84446 -800 84558 480 m2
+port "wbs_adr_i[20]" 587 83264 -800 83376 480 m2
+port "wbs_dat_o[19]" 650 82082 -800 82194 480 m2
+port "wbs_dat_i[19]" 618 80900 -800 81012 480 m2
+port "wbs_adr_i[19]" 585 79718 -800 79830 480 m2
+port "wbs_dat_o[18]" 649 78536 -800 78648 480 m2
+port "wbs_dat_i[18]" 617 77354 -800 77466 480 m2
+port "wbs_adr_i[18]" 584 76172 -800 76284 480 m2
+port "wbs_dat_o[17]" 648 74990 -800 75102 480 m2
+port "wbs_dat_i[17]" 616 73808 -800 73920 480 m2
+port "wbs_adr_i[17]" 583 72626 -800 72738 480 m2
+port "wbs_dat_o[16]" 647 71444 -800 71556 480 m2
+port "wbs_dat_i[16]" 615 70262 -800 70374 480 m2
+port "wbs_adr_i[16]" 582 69080 -800 69192 480 m2
+port "wbs_dat_o[15]" 646 67898 -800 68010 480 m2
+port "wbs_dat_i[15]" 614 66716 -800 66828 480 m2
+port "wbs_adr_i[15]" 581 65534 -800 65646 480 m2
+port "wbs_dat_o[14]" 645 64352 -800 64464 480 m2
+port "wbs_dat_i[14]" 613 63170 -800 63282 480 m2
+port "wbs_adr_i[14]" 580 61988 -800 62100 480 m2
+port "wbs_dat_o[13]" 644 60806 -800 60918 480 m2
+port "wbs_dat_i[13]" 612 59624 -800 59736 480 m2
+port "wbs_adr_i[13]" 579 58442 -800 58554 480 m2
+port "wbs_dat_o[12]" 643 57260 -800 57372 480 m2
+port "wbs_dat_i[12]" 611 56078 -800 56190 480 m2
+port "wbs_adr_i[12]" 578 54896 -800 55008 480 m2
+port "wbs_dat_o[11]" 642 53714 -800 53826 480 m2
+port "wbs_dat_i[11]" 610 52532 -800 52644 480 m2
+port "wbs_adr_i[11]" 577 51350 -800 51462 480 m2
+port "wbs_dat_o[10]" 641 50168 -800 50280 480 m2
+port "wbs_dat_i[10]" 609 48986 -800 49098 480 m2
+port "wbs_adr_i[10]" 576 47804 -800 47916 480 m2
+port "wbs_dat_o[9]" 671 46622 -800 46734 480 m2
+port "wbs_dat_i[9]" 639 45440 -800 45552 480 m2
+port "wbs_adr_i[9]" 606 44258 -800 44370 480 m2
+port "wbs_dat_o[8]" 670 43076 -800 43188 480 m2
+port "wbs_dat_i[8]" 638 41894 -800 42006 480 m2
+port "wbs_adr_i[8]" 605 40712 -800 40824 480 m2
+port "wbs_dat_o[7]" 669 39530 -800 39642 480 m2
+port "wbs_dat_i[7]" 637 38348 -800 38460 480 m2
+port "wbs_adr_i[7]" 604 37166 -800 37278 480 m2
+port "wbs_dat_o[6]" 668 35984 -800 36096 480 m2
+port "wbs_dat_i[6]" 636 34802 -800 34914 480 m2
+port "wbs_adr_i[6]" 603 33620 -800 33732 480 m2
+port "wbs_dat_o[5]" 667 32438 -800 32550 480 m2
+port "wbs_dat_i[5]" 635 31256 -800 31368 480 m2
+port "wbs_adr_i[5]" 602 30074 -800 30186 480 m2
+port "wbs_dat_o[4]" 666 28892 -800 29004 480 m2
+port "wbs_dat_i[4]" 634 27710 -800 27822 480 m2
+port "wbs_adr_i[4]" 601 26528 -800 26640 480 m2
+port "wbs_sel_i[3]" 675 25346 -800 25458 480 m2
+port "wbs_dat_o[3]" 665 24164 -800 24276 480 m2
+port "wbs_dat_i[3]" 633 22982 -800 23094 480 m2
+port "wbs_adr_i[3]" 600 21800 -800 21912 480 m2
+port "wbs_sel_i[2]" 674 20618 -800 20730 480 m2
+port "wbs_dat_o[2]" 662 19436 -800 19548 480 m2
+port "wbs_dat_i[2]" 630 18254 -800 18366 480 m2
+port "wbs_adr_i[2]" 597 17072 -800 17184 480 m2
+port "wbs_sel_i[1]" 673 15890 -800 16002 480 m2
+port "wbs_dat_o[1]" 651 14708 -800 14820 480 m2
+port "wbs_dat_i[1]" 619 13526 -800 13638 480 m2
+port "wbs_adr_i[1]" 586 12344 -800 12456 480 m2
+port "wbs_sel_i[0]" 672 11162 -800 11274 480 m2
+port "wbs_dat_o[0]" 640 9980 -800 10092 480 m2
+port "wbs_dat_i[0]" 608 8798 -800 8910 480 m2
+port "wbs_adr_i[0]" 575 7616 -800 7728 480 m2
+port "wbs_we_i" 677 6434 -800 6546 480 m2
+port "wbs_stb_i" 676 5252 -800 5364 480 m2
+port "wbs_cyc_i" 607 4070 -800 4182 480 m2
+port "wbs_ack_o" 574 2888 -800 3000 480 m2
+port "wb_rst_i" 573 1706 -800 1818 480 m2
+port "wb_clk_i" 572 524 -800 636 480 m2
+port "io_analog[6]" 49 165594 702300 170594 704800 m5
+port "io_analog[6]" 43 175894 702300 180894 704800 m5
+port "io_analog[5]" 48 217294 702300 222294 704800 m5
+port "io_analog[5]" 42 227594 702300 232594 704800 m5
+port "io_analog[8]" 45 68194 702300 73194 704800 m3
+port "io_analog[7]" 44 120194 702300 125194 704800 m3
+port "vssa1" 563 510594 702340 515394 704800 m3
+port "vssa1" 562 520594 702340 525394 704800 m3
+port "io_clamp_low[2]" 55 170894 702300 173094 704800 m3
+port "io_clamp_low[1]" 54 222594 702300 224794 704800 m3
+port "vccd1" 553 582340 629784 584800 634584 m3
+port "vccd1" 552 582340 639784 584800 644584 m3
+port "io_clamp_high[2]" 52 173394 702300 175594 704800 m3
+port "io_clamp_high[1]" 51 225094 702300 227294 704800 m3
+port "io_analog[3]" 40 413394 702300 418394 704800 m3
+port "io_analog[2]" 39 465394 702300 470394 704800 m3
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+node "wbs_ack_o" 1 589.888 2888 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_rst_i" 1 589.888 1706 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "wb_clk_i" 1 589.888 524 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0 0 0
+node "Vn" 1 190462 416354 584730 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 774468 4764 487552 2836 487552 2836 487552 2836 931980844 795520 0 0
+equiv "Vn" "io_analog[6]"
+node "Vp" 1 180404 416354 585850 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 776924 4776 497772 2864 497772 2864 497772 2864 985573920 756748 0 0
+equiv "Vp" "io_analog[5]"
+node "li_422004_585422#" 15 535.841 422004 585422 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 190120 1756 0 0 0 0 0 0 0 0 0 0 0 0
+node "L4" 122 316.138 406062 585484 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38592 1368 0 0 0 0 0 0 0 0 0 0 0 0
+node "L3" 87 203.619 405550 585482 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21556 896 0 0 0 0 0 0 0 0 0 0 0 0
+node "li_411086_585488#" 78 3832.36 411086 585488 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65108 1476 47824 880 71764 1512 1233160 13064 0 0 0 0 0 0
+node "CLK" 17 389287 404984 585410 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53704 940 53704 940 53704 940 672471604 913680 0 0 0 0 0 0
+equiv "CLK" "io_analog[8]"
+node "CB" 77 7644.58 411110 587566 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62672 1428 240480 2648 237944 2636 3226936 27324 0 0 0 0 0 0
+node "CLKBAR" 35 362113 404984 587510 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 57624 1096 49784 900 49784 900 654801088 805376 0 0 0 0 0 0
+equiv "CLKBAR" "io_analog[7]"
+node "li_423100_584792#" 122 111187 423100 584792 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 331572 3972 8687528 57536 952444 8292 210788912 146420 0 0 0 0 0 0
+node "li_423086_585916#" 145 104525 423086 585916 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 332368 4188 6197096 40420 1130228 8540 207249076 143980 0 0 0 0 0 0
+node "L2" 189 85860.6 448816 657328 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 635684 6652 487892 3988 487892 3988 205784452 104536 0 0 0 0 0 0
+node "L1" 220 95755 415416 685126 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 624100 7060 487892 3988 487892 3988 230099472 115480 0 0 0 0 0 0
+node "GND" 15 1.14647e+06 405234 586572 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13878204 47304 33398472 55276 11530048 31656 491085020 324488 314226896 215140 4385384584 1400988 0 0
+equiv "GND" "vssa1"
+equiv "GND" "io_clamp_low[2]"
+equiv "GND" "io_clamp_low[1]"
+node "VDD" 23 1.63128e+06 405258 588056 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20251656 52364 8927280 39680 8927280 39680 2520221260 814296 2990957204 985856 0 0 0 0
+equiv "VDD" "vccd1"
+equiv "VDD" "io_clamp_high[2]"
+equiv "VDD" "io_clamp_high[1]"
+node "Outn" 44 30008 415416 690926 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 257852 2456 244512 1996 244512 1996 69461904 37908 0 0 0 0 0 0
+equiv "Outn" "io_analog[3]"
+node "Outp" 75 30250.8 467316 691026 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 275272 3020 242248 1988 242248 1988 69766312 37932 0 0 0 0 0 0
+equiv "Outp" "io_analog[2]"
+node "w_466970_685526#" 5208 230.172 466970 685526 nw 0 0 0 0 84104 1316 0 0 10800 508 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23376 636 0 0 0 0 0 0 0 0 0 0 0 0
+node "w_415018_685602#" 3086 459.642 415018 685602 nw 0 0 0 0 134384 1500 0 0 11232 524 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31760 720 0 0 0 0 0 0 0 0 0 0 0 0
+substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "CLK" "L3" 6.10274
+cap "L4" "L3" 14.5952
+cap "li_423100_584792#" "VDD" 66750.1
+cap "w_415018_685602#" "L1" 33.8948
+cap "Vp" "io_analog[5]" 787.64
+cap "io_analog[5]" "io_analog[5]" 27459.6
+cap "Vp" "li_411086_585488#" 221.824
+cap "Vn" "li_411086_585488#" 534.857
+cap "GND" "L2" 17190.7
+cap "io_analog[6]" "VDD" 842.1
+cap "io_clamp_low[0]" "io_clamp_high[0]" 525
+cap "GND" "io_analog[5]" 623.508
+cap "m4_186716_584374#" "CLK" 4197.46
+cap "GND" "CLK" 733.388
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "L2" "VDD" 439.871
+cap "io_analog[4]" "io_analog[4]" 26250
+cap "Vn" "io_analog[6]" 715.12
+cap "VDD" "m4_204098_586508#" 119000
+cap "Outn" "VDD" 35146.4
+cap "GND" "io_analog[6]" 2381.24
+cap "Vp" "CB" 2421.91
+cap "m3_417434_589490#" "VDD" 6748.76
+cap "m4_186716_584374#" "VDD" 104505
+cap "Vp" "io_analog[5]" 792.12
+cap "GND" "VDD" 289528
+cap "io_analog[5]" "io_analog[5]" 27466.5
+cap "Vp" "m4_204098_586508#" 518203
+cap "Vn" "CLK" 1462.2
+cap "li_423086_585916#" "VDD" 66750.7
+cap "io_analog[6]" "io_analog[6]" 27348.2
+cap "GND" "L1" 13680.4
+cap "GND" "Vp" 33079.8
+cap "GND" "io_analog[5]" 29541.5
+cap "m4_186716_584374#" "Vn" 469663
+cap "w_466970_685526#" "L2" 285.431
+cap "GND" "Vn" 32287.9
+cap "L1" "VDD" 436.85
+cap "Vn" "io_analog[6]" 1013.88
+cap "Vp" "VDD" 12302.8
+cap "VDD" "io_analog[5]" 27239.7
+cap "io_analog[4]" "io_clamp_high[0]" 525
+cap "Vn" "VDD" 9853.69
+cap "CLKBAR" "m4_204098_586508#" 4772.33
+cap "Vp" "io_analog[5]" 645879
+cap "GND" "io_analog[6]" 29547.4
+cap "CB" "li_422004_585422#" 768.642
+cap "m4_186716_584374#" "CLKBAR" 4197.46
+cap "io_analog[6]" "io_analog[6]" 115952
+cap "GND" "CLKBAR" 0.370787
+cap "VDD" "io_analog[6]" 30182.1
+cap "io_analog[4]" "io_clamp_low[0]" 525
+cap "CLKBAR" "VDD" 1169.18
+cap "io_analog[4]" "io_analog[4]" 21250
+cap "Vn" "io_analog[6]" 623011
+cap "Vp" "CLKBAR" 75519.6
+cap "Vn" "CLKBAR" 1462.2
+cap "GND" "li_423100_584792#" 1.81319
+cap "Outp" "VDD" 35296.1
+cap "io_analog[5]" "VDD" 525
+cap "compaartor_v4_0/GND" "Vn" 0.125841
+cap "compaartor_v4_0/GND" "compaartor_v4_0/GND" -72.6
+cap "compaartor_v4_0/GND" "compaartor_v4_0/GND" 6.48
+cap "Vn" "compaartor_v4_0/GND" 2.16217
+cap "compaartor_v4_0/GND" "compaartor_v4_0/GND" -70.256
+cap "compaartor_v4_0/GND" "compaartor_v4_0/GND" -88.313
+cap "buffer_12_0/GND" "buffer_12_0/buf_in" 0.177165
+cap "buffer_12_0/buffer_1_0/inv_W1_0/Vout" "buffer_12_0/buf_in" 0.142416
+cap "buffer_12_0/VDD" "buffer_12_0/buf_in" -46.69
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vout" "buffer_12_0/GND" 14.1844
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vout" "buffer_12_0/buffer_1_0/inv_W2_0/Vin" -14.0256
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vin" "buffer_12_0/GND" 15.717
+cap "buffer_12_0/VDD" "buffer_12_0/buf_in" 58.3705
+cap "buffer_12_0/GND" "buffer_12_0/buf_in" 134.348
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vin" "buffer_12_0/buf_in" 10.4926
+cap "buffer_12_0/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_12_0/buffer_1_0/inv_W2_0/Vout" 9.33791
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vout" "buffer_12_0/VDD" 0.631539
+cap "buffer_12_0/buffer_1_0/inv_W2_0/GND" "buffer_12_0/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 58.3099
+cap "buffer_12_0/buffer_1_0/inv_W2_0/GND" "buffer_12_0/buffer_1_0/inv_W2_0/Vout" 0.0741776
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vout" "buffer_12_0/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 3.71703
+cap "buffer_12_0/buffer_2_0/inv_W16_0/li_n14_0#" "buffer_12_0/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" 71.875
+cap "buffer_12_0/buf_out" "buffer_12_0/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#" 43.125
+cap "compaartor_v4_0/Vn" "compaartor_v4_0/CLK" 1152.1
+cap "compaartor_v4_0/preamp_part1_0/a_80_n258#" "compaartor_v4_0/Vn" 332.707
+cap "compaartor_v4_0/preamp_part1_0/a_80_n258#" "compaartor_v4_0/CLK" 2.84217e-14
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 241.307
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/latch_2_0/inv_W2_1/VDD" 24.6168
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/latch_2_0/inv_W2_1/VDD" 24.6168
+cap "compaartor_v4_0/SR_latch_0/GND" "compaartor_v4_0/Outp" 42.2749
+cap "compaartor_v4_0/SR_latch_0/VDD" "compaartor_v4_0/Outp" 27.5653
+cap "compaartor_v4_0/Outn" "compaartor_v4_0/SR_latch_0/VDD" 3.36898
+cap "compaartor_v4_0/Outn" "compaartor_v4_0/Outp" 1.21217
+cap "compaartor_v4_0/Outp" "compaartor_v4_0/a_366_4532#" 76.776
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/VDD" 241.307
+cap "compaartor_v4_0/SR_latch_0/GND" "compaartor_v4_0/CLKBAR" 73.975
+cap "compaartor_v4_0/Outp" "compaartor_v4_0/SR_latch_0/VDD" 41.2404
+cap "compaartor_v4_0/SR_latch_0/VDD" "compaartor_v4_0/Outn" 5.53476
+cap "buffer_12_0/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_12_0/VDD" 14.5455
+cap "buffer_12_0/buf_in" "buffer_12_0/VDD" 0.572254
+cap "buffer_12_1/buffer_1_0/inv_W1_0/Vin" "buffer_12_1/GND" 37.3002
+cap "buffer_12_1/GND" "buffer_12_1/buffer_1_0/inv_W2_0/Vin" 5.625
+cap "buffer_12_0/buffer_1_0/inv_W2_0/Vout" "buffer_12_0/VDD" 24.0766
+cap "buffer_12_1/buffer_1_0/inv_W2_0/Vout" "buffer_12_1/GND" 5.07353
+cap "buffer_12_0/buffer_2_0/inv_W16_0/li_n14_902#" "buffer_12_0/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 69.0909
+cap "buffer_12_1/buffer_1_0/inv_W2_0/GND" "buffer_12_1/buffer_2_0/inv_W8_0/sky130_fd_pr__nfet_01v8_KZU588_0/a_n321_n100#" 21.7895
+cap "buffer_12_0/buffer_2_0/inv_W16_0/li_n14_902#" "buffer_12_0/buffer_2_0/w_1666_500#" 74.62
+cap "buffer_12_0/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "buffer_12_0/buffer_2_0/inv_W16_0/li_n14_902#" 73.1818
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_0#" 26.9531
+cap "buffer_12_0/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#" "buffer_12_0/buf_out" 41.8182
+cap "buffer_12_1/buffer_2_0/Vout" "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#" 16.1719
+cap "compaartor_v4_0/Vp" "compaartor_v4_0/CLK" 1150.91
+cap "compaartor_v4_0/latch_2_0/inv_W2_1/VDD" "compaartor_v4_0/CLKBAR" 0.916667
+cap "compaartor_v4_0/latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" "compaartor_v4_0/CLKBAR" 3.125
+cap "compaartor_v4_0/SR_latch_0/a_518_392#" "compaartor_v4_0/Outn" 1.21217
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/SR_latch_0/GND" 1.66667
+cap "compaartor_v4_0/a_1048_4532#" "compaartor_v4_0/Outn" 63.7298
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/latch_2_0/inv_W2_1/VDD" 0.916667
+cap "compaartor_v4_0/SR_latch_0/VDD" "compaartor_v4_0/Outn" 22.5766
+cap "compaartor_v4_0/SR_latch_0/GND" "compaartor_v4_0/Outn" 7.36146
+cap "compaartor_v4_0/a_1048_4532#" "compaartor_v4_0/CLKBAR" 152.409
+cap "compaartor_v4_0/CLKBAR" "compaartor_v4_0/latch_2_0/sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n81_n100#" 3.125
+cap "compaartor_v4_0/SR_latch_0/VDD" "compaartor_v4_0/Outn" 221.448
+cap "buffer_12_1/buf_in" "Vp" -14.96
+cap "buffer_12_1/buffer_1_0/inv_W1_0/pmos_2uf2_0/a_n33_n100#" "buffer_12_1/buf_in" 2.85405
+cap "buffer_12_1/VDD" "buffer_12_1/buf_in" -27.88
+cap "Vp" "buffer_12_1/buffer_1_0/inv_W2_0/Vin" 236.682
+cap "buffer_12_1/GND" "buffer_12_1/buffer_1_0/inv_W2_0/Vout" 5.07353
+cap "buffer_12_1/GND" "buffer_12_1/buf_in" 37.3002
+cap "buffer_12_1/buffer_1_0/inv_W2_0/Vout" "buffer_12_1/VDD" 13.9865
+cap "buffer_12_1/buf_in" "buffer_12_1/VDD" 10.6398
+cap "Vp" "buffer_12_1/buffer_1_0/inv_W2_0/Vout" 268.669
+cap "buffer_12_1/buf_in" "buffer_12_1/buffer_1_0/inv_W2_0/Vin" 14.9147
+cap "Vp" "buffer_12_1/buf_in" -86.6252
+cap "buffer_12_1/VDD" "buffer_12_1/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 6.42857
+cap "buffer_12_1/GND" "buffer_12_1/buffer_1_0/inv_W2_0/Vin" 5.625
+cap "Vp" "buffer_12_1/GND" 206.266
+cap "Vp" "buffer_12_1/VDD" 762.794
+cap "Vp" "buffer_12_1/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" 83.7672
+cap "buffer_12_1/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_902#" 45
+cap "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_902#" "buffer_12_1/buffer_2_0/w_1666_500#" 246.415
+cap "buffer_12_1/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_12_1/buffer_1_0/inv_W2_0/GND" 21.7895
+cap "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_902#" "Vp" 460.103
+cap "Vp" "buffer_12_1/buffer_1_0/inv_W2_0/GND" 243.006
+cap "Vp" "buffer_12_1/buffer_1_0/inv_W2_0/Vout" -60.6659
+cap "buffer_12_1/buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "Vp" 540.468
+cap "Vp" "buffer_12_1/buffer_2_0/w_1666_500#" 130.358
+cap "buffer_12_1/buffer_2_0/inv_W16_0/a_82_816#" "Vp" 112.766
+cap "Vp" "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_902#" -69.3908
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_902#" 45
+cap "Vp" "buffer_12_1/buffer_2_0/w_1666_500#" 206.233
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_0#" 26.9531
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "Vp" 329.351
+cap "Vp" "buffer_12_1/buffer_2_0/inv_W16_0/li_n14_0#" 295.359
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "Vp" 570.537
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n735_n176#" "Vp" -105.554
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#" "Vp" 454.042
+cap "buffer_12_1/buf_out" "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n417_n100#" 25.7143
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#" "Vp" 147.253
+cap "buffer_12_1/buf_out" "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n33_n100#" 16.1719
+cap "buffer_12_1/buffer_2_0/inv_W16_0/a_82_816#" "Vp" -20.3738
+cap "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" "Vp" 130.298
+cap "buffer_12_1/buf_out" "Vp" 641.238
+cap "Vp" "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/w_n1601_n200#" -82.8252
+cap "Vp" "buffer_12_1/buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_927_n100#" 127.711
+cap "Vp" "buffer_12_1/buffer_2_0/inv_W16_0/a_82_816#" 28.5345
+cap "buffer_12_1/buf_out" "Vp" -903.745
+cap "CB" "compaartor_v4_0/CLK" 328.622
+cap "compaartor_v4_0/VDD" "compaartor_v4_0/VDD" 56.76
+cap "compaartor_v4_0/VDD" "compaartor_v4_0/VDD" 25.8
+cap "CB" "compaartor_v4_0/CLK" 1186.38
+cap "CB" "compaartor_v4_0/VDD" 5.76
+cap "compaartor_v4_0/VDD" "CB" 156.252
+cap "compaartor_v4_0/CLK" "CB" 1191.89
+cap "CB" "compaartor_v4_0/VDD" 369.322
+cap "CB" "compaartor_v4_0/CLK" 509.108
+cap "compaartor_v4_0/VDD" "compaartor_v4_0/VDD" 55
+cap "compaartor_v4_0/VDD" "compaartor_v4_0/VDD" 121
+cap "m3_417434_589490#" "compaartor_v4_0/VDD" 8.2623
+cap "m3_417434_589490#" "compaartor_v4_0/VDD" 120.836
+cap "m3_417434_589490#" "compaartor_v4_0/VDD" 154.918
+cap "m3_417434_589490#" "compaartor_v4_0/VDD" 3.61475
+cap "compaartor_v4_0/VDD" "m3_417434_589490#" 90.8852
+cap "buffer_1_0/inv_W1_0/Vin" "buffer_1_0/inv_W2_0/GND" 0.020697
+cap "buffer_1_0/inv_W1_0/Vin" "buffer_1_0/inv_W2_0/Vin" 0.257812
+cap "buffer_1_1/inv_W2_0/VDD" "buffer_1_1/inv_W1_0/Vin" 0.863874
+cap "buffer_1_1/inv_W1_0/Vin" "buffer_1_1/inv_W2_0/Vin" 7.48936
+cap "buffer_1_1/inv_W1_0/Vin" "buffer_1_1/inv_W2_0/VDD" 6.67487
+cap "buffer_1_1/inv_W1_0/Vin" "buffer_1_1/inv_W2_0/GND" -1.62442
+cap "buffer_1_0/inv_W2_0/Vout" "buffer_1_0/inv_W2_0/VDD" 1.36082
+cap "buffer_1_0/inv_W2_0/Vout" "buffer_1_0/inv_W2_0/Vin" 4.52941
+cap "buffer_1_0/inv_W2_0/VDD" "buffer_1_0/inv_W2_0/Vout" 1.36082
+cap "buffer_1_0/inv_W2_0/GND" "buffer_1_0/inv_W2_0/Vout" -2.61182
+cap "buffer_1_1/inv_W2_0/VDD" "buffer_1_1/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/a_n129_n100#" 0.255155
+cap "buffer_1_1/inv_W2_0/GND" "buffer_1_1/inv_W2_0/Vout" -0.314831
+cap "buffer_1_1/inv_W2_0/Vin" "buffer_1_1/inv_W2_0/Vout" 4.01739
+cap "buffer_1_1/inv_W2_0/VDD" "buffer_1_1/inv_W2_0/Vout" 0.255155
+cap "buffer_1_1/inv_W2_0/VDD" "buffer_1_1/inv_W2_0/sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#" -137.35
+cap "buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_2_0/inv_W8_0/w_354_500#" 16.3975
+cap "buffer_2_0/inv_W8_0/w_354_500#" "buffer_2_0/inv_W8_0/a_804_430#" 5.17143
+cap "buffer_2_0/inv_W8_0/a_804_430#" "buffer_2_0/inv_W8_0/li_354_0#" 5.60784
+cap "buffer_2_1/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_2_1/inv_W8_0/a_804_430#" 12.7233
+cap "buffer_2_1/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n705_n100#" "buffer_2_1/inv_W8_0/w_354_500#" 4.70266
+cap "buffer_2_1/inv_W8_0/li_354_0#" "buffer_2_1/inv_W8_0/a_804_430#" 4.95559
+cap "buffer_2_1/inv_W8_0/w_354_500#" "buffer_2_1/inv_W8_0/a_804_430#" 32.9783
+cap "buffer_2_0/w_1666_500#" "buffer_2_0/inv_W16_0/li_n14_902#" -574.82
+cap "buffer_2_0/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_n513_n100#" "buffer_2_0/inv_W16_0/li_n14_902#" 20.8819
+cap "buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "buffer_2_0/inv_W16_0/li_n14_902#" 13.6968
+cap "buffer_2_0/inv_W16_0/li_n14_0#" "buffer_2_0/inv_W16_0/a_82_816#" 6.38889
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" 1.62139
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1089_n100#" 1.62139
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_639_n100#" 1.62139
+cap "buffer_2_1/inv_W8_0/sky130_fd_pr__pfet_01v8_RL4NCG_0/a_447_n100#" "buffer_2_1/inv_W16_0/li_n14_902#" 1.62139
+cap "buffer_2_1/w_1666_500#" "buffer_2_1/inv_W16_0/li_n14_902#" -1119.71
+cap "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1281_n100#" "buffer_2_1/inv_W16_0/li_n14_902#" 1.62139
+cap "buffer_2_1/inv_W16_0/a_82_816#" "buffer_2_1/inv_W16_0/li_n14_0#" 1.13687e-13
+cap "buffer_2_1/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "buffer_2_1/inv_W16_0/li_n14_0#" 5.53476
+cap "buffer_2_1/inv_W16_0/a_82_816#" "buffer_2_1/inv_W16_0/li_n14_902#" 4.54747e-13
+cap "buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1473_n100#" "buffer_2_0/inv_W16_0/li_n14_902#" 24.6702
+cap "buffer_2_0/inv_W16_0/li_n14_902#" "buffer_2_0/w_1666_500#" -293.15
+cap "buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" "buffer_2_0/inv_W16_0/li_n14_0#" 19.0491
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n897_n100#" 1.62139
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n705_n100#" 1.62139
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n513_n100#" 1.62139
+cap "buffer_2_1/w_1666_500#" "buffer_2_1/inv_W16_0/li_n14_902#" -365.31
+cap "buffer_2_1/inv_W16_0/li_n14_0#" "buffer_2_1/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_n705_n100#" 16.6043
+cap "buffer_2_1/inv_W16_0/li_n14_902#" "buffer_2_1/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n1281_n100#" -4.54747e-13
+cap "buffer_2_0/Vout" "buffer_2_0/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_351_n100#" 5.16867
+cap "buffer_2_0/Vout" "buffer_2_0/inv_W16_0/sky130_fd_pr__pfet_01v8_3M44SC_0/a_n33_n100#" 0.116337
+cap "buffer_2_1/inv_W16_0/sky130_fd_pr__nfet_01v8_VJWT33_0/a_543_n100#" "buffer_2_1/Vout" 0.0436508
+cap "buffer_2_0/inv_W16_0/li_n14_0#" "buffer_2_0/Vout" 5.16867
+merge "buffer_12_1/buf_in" "buffer_12_1/buffer_1_0/inv_W1_0/Vin" -6556.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -143288 -248 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
+merge "buffer_12_1/buffer_1_0/inv_W1_0/Vin" "CLKBAR"
+merge "buffer_12_1/buf_out" "buffer_12_1/buffer_2_0/Vout" -3581.28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -812612 -736 -51236 -540 0 0 -118304 -11880 0 0 0 0 0 0
+merge "buffer_12_1/buffer_2_0/Vout" "compaartor_v4_0/CLKBAR"
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diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
new file mode 100644
index 0000000..e52f605
--- /dev/null
+++ b/mag/user_analog_project_wrapper.mag
@@ -0,0 +1,4724 @@
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+transform 0 -1 233962 1 0 342823
+box 0 0 2448 477
+use buffer_12 buffer_12_0 ~/mycomparator_copy1/layout/myinv_layout2
+timestamp 1646326465
+transform 1 0 202623 0 1 292526
+box 0 0 2943 477
+use buffer_12 buffer_12_1
+timestamp 1646326465
+transform 1 0 202634 0 1 293564
+box 0 0 2943 477
+use compaartor_v4 compaartor_v4_0
+timestamp 1647355571
+transform 0 1 209119 1 0 292366
+box -1299 -442 2269 2778
+<< labels >>
+flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
+port 0 nsew signal bidirectional
+flabel metal3 s -400 190932 240 190988 0 FreeSans 560 0 0 0 gpio_analog[10]
+port 1 nsew signal bidirectional
+flabel metal3 s -400 169321 240 169377 0 FreeSans 560 0 0 0 gpio_analog[11]
+port 2 nsew signal bidirectional
+flabel metal3 s -400 147710 240 147766 0 FreeSans 560 0 0 0 gpio_analog[12]
+port 3 nsew signal bidirectional
+flabel metal3 s -400 126199 240 126255 0 FreeSans 560 0 0 0 gpio_analog[13]
+port 4 nsew signal bidirectional
+flabel metal3 s -400 62388 240 62444 0 FreeSans 560 0 0 0 gpio_analog[14]
+port 5 nsew signal bidirectional
+flabel metal3 s -400 40777 240 40833 0 FreeSans 560 0 0 0 gpio_analog[15]
+port 6 nsew signal bidirectional
+flabel metal3 s -400 19166 240 19222 0 FreeSans 560 0 0 0 gpio_analog[16]
+port 7 nsew signal bidirectional
+flabel metal3 s -400 8455 240 8511 0 FreeSans 560 0 0 0 gpio_analog[17]
+port 8 nsew signal bidirectional
+flabel metal3 s 291760 156826 292400 156882 0 FreeSans 560 0 0 0 gpio_analog[1]
+port 9 nsew signal bidirectional
+flabel metal3 s 291760 179437 292400 179493 0 FreeSans 560 0 0 0 gpio_analog[2]
+port 10 nsew signal bidirectional
+flabel metal3 s 291760 202648 292400 202704 0 FreeSans 560 0 0 0 gpio_analog[3]
+port 11 nsew signal bidirectional
+flabel metal3 s 291760 224859 292400 224915 0 FreeSans 560 0 0 0 gpio_analog[4]
+port 12 nsew signal bidirectional
+flabel metal3 s 291760 247070 292400 247126 0 FreeSans 560 0 0 0 gpio_analog[5]
+port 13 nsew signal bidirectional
+flabel metal3 s 291760 291781 292400 291837 0 FreeSans 560 0 0 0 gpio_analog[6]
+port 14 nsew signal bidirectional
+flabel metal3 s -400 255765 240 255821 0 FreeSans 560 0 0 0 gpio_analog[7]
+port 15 nsew signal bidirectional
+flabel metal3 s -400 234154 240 234210 0 FreeSans 560 0 0 0 gpio_analog[8]
+port 16 nsew signal bidirectional
+flabel metal3 s -400 212543 240 212599 0 FreeSans 560 0 0 0 gpio_analog[9]
+port 17 nsew signal bidirectional
+flabel metal3 s 291760 135206 292400 135262 0 FreeSans 560 0 0 0 gpio_noesd[0]
+port 18 nsew signal bidirectional
+flabel metal3 s -400 190341 240 190397 0 FreeSans 560 0 0 0 gpio_noesd[10]
+port 19 nsew signal bidirectional
+flabel metal3 s -400 168730 240 168786 0 FreeSans 560 0 0 0 gpio_noesd[11]
+port 20 nsew signal bidirectional
+flabel metal3 s -400 147119 240 147175 0 FreeSans 560 0 0 0 gpio_noesd[12]
+port 21 nsew signal bidirectional
+flabel metal3 s -400 125608 240 125664 0 FreeSans 560 0 0 0 gpio_noesd[13]
+port 22 nsew signal bidirectional
+flabel metal3 s -400 61797 240 61853 0 FreeSans 560 0 0 0 gpio_noesd[14]
+port 23 nsew signal bidirectional
+flabel metal3 s -400 40186 240 40242 0 FreeSans 560 0 0 0 gpio_noesd[15]
+port 24 nsew signal bidirectional
+flabel metal3 s -400 18575 240 18631 0 FreeSans 560 0 0 0 gpio_noesd[16]
+port 25 nsew signal bidirectional
+flabel metal3 s -400 7864 240 7920 0 FreeSans 560 0 0 0 gpio_noesd[17]
+port 26 nsew signal bidirectional
+flabel metal3 s 291760 157417 292400 157473 0 FreeSans 560 0 0 0 gpio_noesd[1]
+port 27 nsew signal bidirectional
+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+rlabel metal4 279603 320735 279603 320735 1 VDD
+rlabel metal5 262406 341214 262406 341214 3 GND
+rlabel metal5 82776 349832 82776 349832 7 Vn
+rlabel metal5 108655 346985 108655 346985 7 Vp
+rlabel metal3 34076 349454 34076 349454 7 CLK
+rlabel metal3 60064 344634 60064 344634 7 CLKBAR
+rlabel metal3 232699 349450 232699 349450 7 Outp
+rlabel metal3 206695 349839 206695 349839 7 Outn
+rlabel metal3 209244 293869 209244 293869 1 CB
+rlabel metal3 219460 331025 219460 331025 7 L1
+rlabel metal3 223659 331037 223659 331037 7 L2
+rlabel locali 202871 292740 202871 292740 5 L3
+rlabel locali 203127 292741 203127 292741 5 L4
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git a/mag/user_analog_project_wrapper.spice b/mag/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..de780e7
--- /dev/null
+++ b/mag/user_analog_project_wrapper.spice
@@ -0,0 +1,537 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout VDD Vin GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1#0 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt buffer_1 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin inv_W2_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 w_n1601_n200# VSUBS 3.82fF
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+C0 a_82_816# VSUBS 2.90fF
+C1 w_82_814# VSUBS 3.92fF
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W8_0/li_354_902# VSUBS -3.18fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.10fF
+.ends
+
+.subckt buffer_12 buffer_1_0/inv_W2_0/Vout buf_in buffer_1_0/inv_W2_0/Vin VDD buf_out
++ GND
+Xbuffer_1_0 VDD buffer_1_0/inv_W2_0/Vout buf_in buffer_1_0/inv_W2_0/Vin GND buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+C0 VDD 0 3.98fF
+C1 GND 0 2.58fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B#0 a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#1 a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ#1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/Vin inv_W2_1/GND sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_0/Vin inv_W2_1/Vout VSUBS
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vin inv_W2_0/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vout inv_W2_1/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_1/VDD
++ inv_W2_1/VDD m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+C0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# VSUBS 2.01fF
+.ends
+
+.subckt compaartor_v4 Outn Vp Vn CLK VDD GND Outp CLKBAR
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin Outn VDD VDD GND GND
++ SR_latch
+Xpreamp_part1_0 latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin m1_n58_544# CLK CLK
++ VDD Vn CLK m1_1202_1938# VDD Vp GND GND preamp_part1
+Xlatch_2_0 VDD latch_2_0/inv_W2_1/Vin GND VDD CLKBAR latch_2_0/inv_W2_0/Vin latch_2_0/inv_W2_0/Vin
++ GND latch_2
+C0 latch_2_0/inv_W2_1/Vin GND 2.84fF
+C1 latch_2_0/inv_W2_0/Vin GND 4.28fF
+C2 CLK GND 17.54fF
+C3 VDD GND 22.81fF
+C4 m1_n58_544# GND 2.08fF
+.ends
+
+.subckt buffer_2#0 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W8_0/li_354_902# VSUBS -3.18fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.10fF
+.ends
+
+.subckt buffer_2#1 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W8_0/li_354_902# VSUBS -3.18fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.10fF
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_low[0] io_in[0] io_in[10] io_in[11]
++ io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19]
++ io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2]
++ io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10]
++ io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16]
++ io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21]
++ io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2]
++ io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9]
++ io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16]
++ io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23]
++ io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6]
++ io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13]
++ io_out[14] io_out[15] io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20]
++ io_out[21] io_out[22] io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3]
++ io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100]
++ la_data_in[101] la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105]
++ la_data_in[106] la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110]
++ la_data_in[111] la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115]
++ la_data_in[116] la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120]
++ la_data_in[121] la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125]
++ la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15]
++ la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20]
++ la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26]
++ la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31]
++ la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37]
++ la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42]
++ la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48]
++ la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53]
++ la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59]
++ la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64]
++ la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6]
++ la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75]
++ la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80]
++ la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86]
++ la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91]
++ la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97]
++ la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101]
++ la_data_out[102] la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106]
++ la_data_out[107] la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110]
++ la_data_out[111] la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115]
++ la_data_out[116] la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11]
++ la_data_out[120] la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124]
++ la_data_out[125] la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13]
++ la_data_out[14] la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18]
++ la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23]
++ la_data_out[24] la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28]
++ la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33]
++ la_data_out[34] la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38]
++ la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43]
++ la_data_out[44] la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48]
++ la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53]
++ la_data_out[54] la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58]
++ la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63]
++ la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68]
++ la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73]
++ la_data_out[74] la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78]
++ la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83]
++ la_data_out[84] la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88]
++ la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93]
++ la_data_out[94] la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98]
++ la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102]
++ la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109]
++ la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115]
++ la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121]
++ la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12]
++ la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19]
++ la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25]
++ la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31]
++ la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38]
++ la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44]
++ la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50]
++ la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57]
++ la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63]
++ la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6]
++ la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76]
++ la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82]
++ la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89]
++ la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95]
++ la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0]
++ user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_ack_o wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13]
++ wbs_adr_i[14] wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19]
++ wbs_adr_i[1] wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24]
++ wbs_adr_i[25] wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2]
++ wbs_adr_i[30] wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6]
++ wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11]
++ wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17]
++ wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22]
++ wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28]
++ wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4]
++ wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10]
++ wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16]
++ wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21]
++ wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27]
++ wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3]
++ wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0]
++ wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i
+Xbuffer_1_0 vccd1 L1 compaartor_v4_0/Outn vssa1 buffer_1#0
+Xbuffer_1_1 vccd1 L2 compaartor_v4_0/Outp vssa1 buffer_1#0
+Xbuffer_12_0 L4 io_analog[8] L3 vccd1 compaartor_v4_0/CLK vssa1 buffer_12
+Xbuffer_12_1 buffer_12_1/buffer_1_0/inv_W2_0/Vout io_analog[7] buffer_12_1/buffer_1_0/inv_W2_0/Vin
++ vccd1 CB vssa1 buffer_12
+Xcompaartor_v4_0 compaartor_v4_0/Outn io_analog[5] io_analog[6] compaartor_v4_0/CLK
++ vccd1 vssa1 compaartor_v4_0/Outp CB compaartor_v4
+Xbuffer_2_0 io_analog[3] vccd1 vccd1 L1 vssa1 vssa1 buffer_2#0
+Xbuffer_2_1 io_analog[2] vccd1 vccd1 L2 vssa1 vssa1 buffer_2#1
+C0 m4_204098_586508# io_analog[5] 518.20fF
+C1 vccd1 m4_186716_584374# 104.50fF
+C2 CB io_analog[5] 3.06fF
+C3 vccd1 io_analog[2] 35.31fF
+C4 vccd1 io_analog[5] 42.19fF
+C5 vccd1 io_analog[6] 40.88fF
+C6 io_analog[7] m4_186716_584374# 4.20fF
+C7 vccd1 m4_204098_586508# 119.00fF
+C8 vccd1 compaartor_v4_0/Outn 67.00fF
+C9 io_analog[5] io_analog[7] 75.42fF
+C10 m4_204098_586508# io_analog[7] 4.77fF
+C11 m4_186716_584374# io_analog[8] 4.20fF
+C12 io_analog[6] compaartor_v4_0/CLK 2.02fF
+C13 io_analog[3] vccd1 35.18fF
+C14 m3_417434_589490# vccd1 7.13fF
+C15 CB compaartor_v4_0/CLK 3.22fF
+C16 io_analog[6] m4_186716_584374# 469.66fF
+C17 vccd1 compaartor_v4_0/Outp 66.83fF
+C18 io_analog[4] vssa1 25.05fF
+C19 vssd2 vssa1 13.04fF
+C20 vssd1 vssa1 13.62fF
+C21 vdda2 vssa1 13.04fF
+C22 vdda1 vssa1 26.08fF
+C23 vssa2 vssa1 13.04fF
+C24 io_analog[0] vssa1 6.83fF
+C25 io_analog[1] vssa1 6.83fF
+C26 io_clamp_high[0] vssa1 3.58fF
+C27 io_clamp_low[0] vssa1 3.58fF
+C28 vccd2 vssa1 13.04fF
+C29 io_analog[10] vssa1 6.83fF
+C30 io_analog[9] vssa1 6.83fF
+C31 m4_204098_586508# vssa1 67.88fF **FLOATING
+C32 m4_186716_584374# vssa1 63.83fF **FLOATING
+C33 m3_417434_589490# vssa1 3.42fF **FLOATING
+C34 io_analog[2] vssa1 20.77fF
+C35 L2 vssa1 104.13fF
+C36 io_analog[3] vssa1 20.99fF
+C37 L1 vssa1 110.57fF
+C38 compaartor_v4_0/latch_2_0/inv_W2_1/Vin vssa1 2.76fF
+C39 compaartor_v4_0/latch_2_0/inv_W2_0/Vin vssa1 3.67fF
+C40 compaartor_v4_0/m1_n58_544# vssa1 2.02fF
+C41 io_analog[5] vssa1 339.85fF
+C42 io_analog[6] vssa1 358.66fF
+C43 compaartor_v4_0/Outp vssa1 111.06fF
+C44 compaartor_v4_0/Outn vssa1 104.23fF
+C45 CB vssa1 3.33fF
+C46 io_analog[7] vssa1 355.98fF
+C47 compaartor_v4_0/CLK vssa1 17.42fF
+C48 vccd1 vssa1 1929.80fF
+C49 io_analog[8] vssa1 383.53fF
+.ends
+
diff --git a/mag/user_analog_project_wrapper_empty.mag b/mag/user_analog_project_wrapper_empty.mag
new file mode 100644
index 0000000..02dbe79
--- /dev/null
+++ b/mag/user_analog_project_wrapper_empty.mag
@@ -0,0 +1,2091 @@
+magic
+tech sky130A
+timestamp 1632839657
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+<< comment >>
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+<< labels >>
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+flabel metal3 s 291760 180028 292400 180084 0 FreeSans 560 0 0 0 gpio_noesd[2]
+port 28 nsew signal bidirectional
+flabel metal3 s 291760 203239 292400 203295 0 FreeSans 560 0 0 0 gpio_noesd[3]
+port 29 nsew signal bidirectional
+flabel metal3 s 291760 225450 292400 225506 0 FreeSans 560 0 0 0 gpio_noesd[4]
+port 30 nsew signal bidirectional
+flabel metal3 s 291760 247661 292400 247717 0 FreeSans 560 0 0 0 gpio_noesd[5]
+port 31 nsew signal bidirectional
+flabel metal3 s 291760 292372 292400 292428 0 FreeSans 560 0 0 0 gpio_noesd[6]
+port 32 nsew signal bidirectional
+flabel metal3 s -400 255174 240 255230 0 FreeSans 560 0 0 0 gpio_noesd[7]
+port 33 nsew signal bidirectional
+flabel metal3 s -400 233563 240 233619 0 FreeSans 560 0 0 0 gpio_noesd[8]
+port 34 nsew signal bidirectional
+flabel metal3 s -400 211952 240 212008 0 FreeSans 560 0 0 0 gpio_noesd[9]
+port 35 nsew signal bidirectional
+flabel metal3 s 291150 338992 292400 341492 0 FreeSans 560 0 0 0 io_analog[0]
+port 36 nsew signal bidirectional
+flabel metal3 s 0 340121 850 342621 0 FreeSans 560 0 0 0 io_analog[10]
+port 37 nsew signal bidirectional
+flabel metal3 s 283297 351150 285797 352400 0 FreeSans 960 180 0 0 io_analog[1]
+port 38 nsew signal bidirectional
+flabel metal3 s 232697 351150 235197 352400 0 FreeSans 960 180 0 0 io_analog[2]
+port 39 nsew signal bidirectional
+flabel metal3 s 206697 351150 209197 352400 0 FreeSans 960 180 0 0 io_analog[3]
+port 40 nsew signal bidirectional
+flabel metal3 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal4 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal5 s 164647 351150 167147 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 41 nsew signal bidirectional
+flabel metal3 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal4 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal5 s 113797 351150 116297 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 42 nsew signal bidirectional
+flabel metal3 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal4 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal5 s 87947 351150 90447 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 43 nsew signal bidirectional
+flabel metal3 s 60097 351150 62597 352400 0 FreeSans 960 180 0 0 io_analog[7]
+port 44 nsew signal bidirectional
+flabel metal3 s 34097 351150 36597 352400 0 FreeSans 960 180 0 0 io_analog[8]
+port 45 nsew signal bidirectional
+flabel metal3 s 8097 351150 10597 352400 0 FreeSans 960 180 0 0 io_analog[9]
+port 46 nsew signal bidirectional
+flabel metal3 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal4 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal5 s 159497 351150 161997 352400 0 FreeSans 960 180 0 0 io_analog[4]
+port 47 nsew signal bidirectional
+flabel metal3 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal4 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal5 s 108647 351150 111147 352400 0 FreeSans 960 180 0 0 io_analog[5]
+port 48 nsew signal bidirectional
+flabel metal3 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal4 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal5 s 82797 351150 85297 352400 0 FreeSans 960 180 0 0 io_analog[6]
+port 49 nsew signal bidirectional
+flabel metal3 s 163397 351150 164497 352400 0 FreeSans 960 180 0 0 io_clamp_high[0]
+port 50 nsew signal bidirectional
+flabel metal3 s 112547 351150 113647 352400 0 FreeSans 960 180 0 0 io_clamp_high[1]
+port 51 nsew signal bidirectional
+flabel metal3 s 86697 351150 87797 352400 0 FreeSans 960 180 0 0 io_clamp_high[2]
+port 52 nsew signal bidirectional
+flabel metal3 s 162147 351150 163247 352400 0 FreeSans 960 180 0 0 io_clamp_low[0]
+port 53 nsew signal bidirectional
+flabel metal3 s 111297 351150 112397 352400 0 FreeSans 960 180 0 0 io_clamp_low[1]
+port 54 nsew signal bidirectional
+flabel metal3 s 85447 351150 86547 352400 0 FreeSans 960 180 0 0 io_clamp_low[2]
+port 55 nsew signal bidirectional
+flabel metal3 s 291760 1363 292400 1419 0 FreeSans 560 0 0 0 io_in[0]
+port 56 nsew signal input
+flabel metal3 s 291760 204421 292400 204477 0 FreeSans 560 0 0 0 io_in[10]
+port 57 nsew signal input
+flabel metal3 s 291760 226632 292400 226688 0 FreeSans 560 0 0 0 io_in[11]
+port 58 nsew signal input
+flabel metal3 s 291760 248843 292400 248899 0 FreeSans 560 0 0 0 io_in[12]
+port 59 nsew signal input
+flabel metal3 s 291760 293554 292400 293610 0 FreeSans 560 0 0 0 io_in[13]
+port 60 nsew signal input
+flabel metal3 s -400 253992 240 254048 0 FreeSans 560 0 0 0 io_in[14]
+port 61 nsew signal input
+flabel metal3 s -400 232381 240 232437 0 FreeSans 560 0 0 0 io_in[15]
+port 62 nsew signal input
+flabel metal3 s -400 210770 240 210826 0 FreeSans 560 0 0 0 io_in[16]
+port 63 nsew signal input
+flabel metal3 s -400 189159 240 189215 0 FreeSans 560 0 0 0 io_in[17]
+port 64 nsew signal input
+flabel metal3 s -400 167548 240 167604 0 FreeSans 560 0 0 0 io_in[18]
+port 65 nsew signal input
+flabel metal3 s -400 145937 240 145993 0 FreeSans 560 0 0 0 io_in[19]
+port 66 nsew signal input
+flabel metal3 s 291760 3727 292400 3783 0 FreeSans 560 0 0 0 io_in[1]
+port 67 nsew signal input
+flabel metal3 s -400 124426 240 124482 0 FreeSans 560 0 0 0 io_in[20]
+port 68 nsew signal input
+flabel metal3 s -400 60615 240 60671 0 FreeSans 560 0 0 0 io_in[21]
+port 69 nsew signal input
+flabel metal3 s -400 39004 240 39060 0 FreeSans 560 0 0 0 io_in[22]
+port 70 nsew signal input
+flabel metal3 s -400 17393 240 17449 0 FreeSans 560 0 0 0 io_in[23]
+port 71 nsew signal input
+flabel metal3 s -400 6682 240 6738 0 FreeSans 560 0 0 0 io_in[24]
+port 72 nsew signal input
+flabel metal3 s -400 4318 240 4374 0 FreeSans 560 0 0 0 io_in[25]
+port 73 nsew signal input
+flabel metal3 s -400 1954 240 2010 0 FreeSans 560 0 0 0 io_in[26]
+port 74 nsew signal input
+flabel metal3 s 291760 6091 292400 6147 0 FreeSans 560 0 0 0 io_in[2]
+port 75 nsew signal input
+flabel metal3 s 291760 8455 292400 8511 0 FreeSans 560 0 0 0 io_in[3]
+port 76 nsew signal input
+flabel metal3 s 291760 10819 292400 10875 0 FreeSans 560 0 0 0 io_in[4]
+port 77 nsew signal input
+flabel metal3 s 291760 24048 292400 24104 0 FreeSans 560 0 0 0 io_in[5]
+port 78 nsew signal input
+flabel metal3 s 291760 46377 292400 46433 0 FreeSans 560 0 0 0 io_in[6]
+port 79 nsew signal input
+flabel metal3 s 291760 136388 292400 136444 0 FreeSans 560 0 0 0 io_in[7]
+port 80 nsew signal input
+flabel metal3 s 291760 158599 292400 158655 0 FreeSans 560 0 0 0 io_in[8]
+port 81 nsew signal input
+flabel metal3 s 291760 181210 292400 181266 0 FreeSans 560 0 0 0 io_in[9]
+port 82 nsew signal input
+flabel metal3 s 291760 772 292400 828 0 FreeSans 560 0 0 0 io_in_3v3[0]
+port 83 nsew signal input
+flabel metal3 s 291760 203830 292400 203886 0 FreeSans 560 0 0 0 io_in_3v3[10]
+port 84 nsew signal input
+flabel metal3 s 291760 226041 292400 226097 0 FreeSans 560 0 0 0 io_in_3v3[11]
+port 85 nsew signal input
+flabel metal3 s 291760 248252 292400 248308 0 FreeSans 560 0 0 0 io_in_3v3[12]
+port 86 nsew signal input
+flabel metal3 s 291760 292963 292400 293019 0 FreeSans 560 0 0 0 io_in_3v3[13]
+port 87 nsew signal input
+flabel metal3 s -400 254583 240 254639 0 FreeSans 560 0 0 0 io_in_3v3[14]
+port 88 nsew signal input
+flabel metal3 s -400 232972 240 233028 0 FreeSans 560 0 0 0 io_in_3v3[15]
+port 89 nsew signal input
+flabel metal3 s -400 211361 240 211417 0 FreeSans 560 0 0 0 io_in_3v3[16]
+port 90 nsew signal input
+flabel metal3 s -400 189750 240 189806 0 FreeSans 560 0 0 0 io_in_3v3[17]
+port 91 nsew signal input
+flabel metal3 s -400 168139 240 168195 0 FreeSans 560 0 0 0 io_in_3v3[18]
+port 92 nsew signal input
+flabel metal3 s -400 146528 240 146584 0 FreeSans 560 0 0 0 io_in_3v3[19]
+port 93 nsew signal input
+flabel metal3 s 291760 3136 292400 3192 0 FreeSans 560 0 0 0 io_in_3v3[1]
+port 94 nsew signal input
+flabel metal3 s -400 125017 240 125073 0 FreeSans 560 0 0 0 io_in_3v3[20]
+port 95 nsew signal input
+flabel metal3 s -400 61206 240 61262 0 FreeSans 560 0 0 0 io_in_3v3[21]
+port 96 nsew signal input
+flabel metal3 s -400 39595 240 39651 0 FreeSans 560 0 0 0 io_in_3v3[22]
+port 97 nsew signal input
+flabel metal3 s -400 17984 240 18040 0 FreeSans 560 0 0 0 io_in_3v3[23]
+port 98 nsew signal input
+flabel metal3 s -400 7273 240 7329 0 FreeSans 560 0 0 0 io_in_3v3[24]
+port 99 nsew signal input
+flabel metal3 s -400 4909 240 4965 0 FreeSans 560 0 0 0 io_in_3v3[25]
+port 100 nsew signal input
+flabel metal3 s -400 2545 240 2601 0 FreeSans 560 0 0 0 io_in_3v3[26]
+port 101 nsew signal input
+flabel metal3 s 291760 5500 292400 5556 0 FreeSans 560 0 0 0 io_in_3v3[2]
+port 102 nsew signal input
+flabel metal3 s 291760 7864 292400 7920 0 FreeSans 560 0 0 0 io_in_3v3[3]
+port 103 nsew signal input
+flabel metal3 s 291760 10228 292400 10284 0 FreeSans 560 0 0 0 io_in_3v3[4]
+port 104 nsew signal input
+flabel metal3 s 291760 23457 292400 23513 0 FreeSans 560 0 0 0 io_in_3v3[5]
+port 105 nsew signal input
+flabel metal3 s 291760 45786 292400 45842 0 FreeSans 560 0 0 0 io_in_3v3[6]
+port 106 nsew signal input
+flabel metal3 s 291760 135797 292400 135853 0 FreeSans 560 0 0 0 io_in_3v3[7]
+port 107 nsew signal input
+flabel metal3 s 291760 158008 292400 158064 0 FreeSans 560 0 0 0 io_in_3v3[8]
+port 108 nsew signal input
+flabel metal3 s 291760 180619 292400 180675 0 FreeSans 560 0 0 0 io_in_3v3[9]
+port 109 nsew signal input
+flabel metal3 s 291760 2545 292400 2601 0 FreeSans 560 0 0 0 io_oeb[0]
+port 110 nsew signal tristate
+flabel metal3 s 291760 205603 292400 205659 0 FreeSans 560 0 0 0 io_oeb[10]
+port 111 nsew signal tristate
+flabel metal3 s 291760 227814 292400 227870 0 FreeSans 560 0 0 0 io_oeb[11]
+port 112 nsew signal tristate
+flabel metal3 s 291760 250025 292400 250081 0 FreeSans 560 0 0 0 io_oeb[12]
+port 113 nsew signal tristate
+flabel metal3 s 291760 294736 292400 294792 0 FreeSans 560 0 0 0 io_oeb[13]
+port 114 nsew signal tristate
+flabel metal3 s -400 252810 240 252866 0 FreeSans 560 0 0 0 io_oeb[14]
+port 115 nsew signal tristate
+flabel metal3 s -400 231199 240 231255 0 FreeSans 560 0 0 0 io_oeb[15]
+port 116 nsew signal tristate
+flabel metal3 s -400 209588 240 209644 0 FreeSans 560 0 0 0 io_oeb[16]
+port 117 nsew signal tristate
+flabel metal3 s -400 187977 240 188033 0 FreeSans 560 0 0 0 io_oeb[17]
+port 118 nsew signal tristate
+flabel metal3 s -400 166366 240 166422 0 FreeSans 560 0 0 0 io_oeb[18]
+port 119 nsew signal tristate
+flabel metal3 s -400 144755 240 144811 0 FreeSans 560 0 0 0 io_oeb[19]
+port 120 nsew signal tristate
+flabel metal3 s 291760 4909 292400 4965 0 FreeSans 560 0 0 0 io_oeb[1]
+port 121 nsew signal tristate
+flabel metal3 s -400 123244 240 123300 0 FreeSans 560 0 0 0 io_oeb[20]
+port 122 nsew signal tristate
+flabel metal3 s -400 59433 240 59489 0 FreeSans 560 0 0 0 io_oeb[21]
+port 123 nsew signal tristate
+flabel metal3 s -400 37822 240 37878 0 FreeSans 560 0 0 0 io_oeb[22]
+port 124 nsew signal tristate
+flabel metal3 s -400 16211 240 16267 0 FreeSans 560 0 0 0 io_oeb[23]
+port 125 nsew signal tristate
+flabel metal3 s -400 5500 240 5556 0 FreeSans 560 0 0 0 io_oeb[24]
+port 126 nsew signal tristate
+flabel metal3 s -400 3136 240 3192 0 FreeSans 560 0 0 0 io_oeb[25]
+port 127 nsew signal tristate
+flabel metal3 s -400 772 240 828 0 FreeSans 560 0 0 0 io_oeb[26]
+port 128 nsew signal tristate
+flabel metal3 s 291760 7273 292400 7329 0 FreeSans 560 0 0 0 io_oeb[2]
+port 129 nsew signal tristate
+flabel metal3 s 291760 9637 292400 9693 0 FreeSans 560 0 0 0 io_oeb[3]
+port 130 nsew signal tristate
+flabel metal3 s 291760 12001 292400 12057 0 FreeSans 560 0 0 0 io_oeb[4]
+port 131 nsew signal tristate
+flabel metal3 s 291760 25230 292400 25286 0 FreeSans 560 0 0 0 io_oeb[5]
+port 132 nsew signal tristate
+flabel metal3 s 291760 47559 292400 47615 0 FreeSans 560 0 0 0 io_oeb[6]
+port 133 nsew signal tristate
+flabel metal3 s 291760 137570 292400 137626 0 FreeSans 560 0 0 0 io_oeb[7]
+port 134 nsew signal tristate
+flabel metal3 s 291760 159781 292400 159837 0 FreeSans 560 0 0 0 io_oeb[8]
+port 135 nsew signal tristate
+flabel metal3 s 291760 182392 292400 182448 0 FreeSans 560 0 0 0 io_oeb[9]
+port 136 nsew signal tristate
+flabel metal3 s 291760 1954 292400 2010 0 FreeSans 560 0 0 0 io_out[0]
+port 137 nsew signal tristate
+flabel metal3 s 291760 205012 292400 205068 0 FreeSans 560 0 0 0 io_out[10]
+port 138 nsew signal tristate
+flabel metal3 s 291760 227223 292400 227279 0 FreeSans 560 0 0 0 io_out[11]
+port 139 nsew signal tristate
+flabel metal3 s 291760 249434 292400 249490 0 FreeSans 560 0 0 0 io_out[12]
+port 140 nsew signal tristate
+flabel metal3 s 291760 294145 292400 294201 0 FreeSans 560 0 0 0 io_out[13]
+port 141 nsew signal tristate
+flabel metal3 s -400 253401 240 253457 0 FreeSans 560 0 0 0 io_out[14]
+port 142 nsew signal tristate
+flabel metal3 s -400 231790 240 231846 0 FreeSans 560 0 0 0 io_out[15]
+port 143 nsew signal tristate
+flabel metal3 s -400 210179 240 210235 0 FreeSans 560 0 0 0 io_out[16]
+port 144 nsew signal tristate
+flabel metal3 s -400 188568 240 188624 0 FreeSans 560 0 0 0 io_out[17]
+port 145 nsew signal tristate
+flabel metal3 s -400 166957 240 167013 0 FreeSans 560 0 0 0 io_out[18]
+port 146 nsew signal tristate
+flabel metal3 s -400 145346 240 145402 0 FreeSans 560 0 0 0 io_out[19]
+port 147 nsew signal tristate
+flabel metal3 s 291760 4318 292400 4374 0 FreeSans 560 0 0 0 io_out[1]
+port 148 nsew signal tristate
+flabel metal3 s -400 123835 240 123891 0 FreeSans 560 0 0 0 io_out[20]
+port 149 nsew signal tristate
+flabel metal3 s -400 60024 240 60080 0 FreeSans 560 0 0 0 io_out[21]
+port 150 nsew signal tristate
+flabel metal3 s -400 38413 240 38469 0 FreeSans 560 0 0 0 io_out[22]
+port 151 nsew signal tristate
+flabel metal3 s -400 16802 240 16858 0 FreeSans 560 0 0 0 io_out[23]
+port 152 nsew signal tristate
+flabel metal3 s -400 6091 240 6147 0 FreeSans 560 0 0 0 io_out[24]
+port 153 nsew signal tristate
+flabel metal3 s -400 3727 240 3783 0 FreeSans 560 0 0 0 io_out[25]
+port 154 nsew signal tristate
+flabel metal3 s -400 1363 240 1419 0 FreeSans 560 0 0 0 io_out[26]
+port 155 nsew signal tristate
+flabel metal3 s 291760 6682 292400 6738 0 FreeSans 560 0 0 0 io_out[2]
+port 156 nsew signal tristate
+flabel metal3 s 291760 9046 292400 9102 0 FreeSans 560 0 0 0 io_out[3]
+port 157 nsew signal tristate
+flabel metal3 s 291760 11410 292400 11466 0 FreeSans 560 0 0 0 io_out[4]
+port 158 nsew signal tristate
+flabel metal3 s 291760 24639 292400 24695 0 FreeSans 560 0 0 0 io_out[5]
+port 159 nsew signal tristate
+flabel metal3 s 291760 46968 292400 47024 0 FreeSans 560 0 0 0 io_out[6]
+port 160 nsew signal tristate
+flabel metal3 s 291760 136979 292400 137035 0 FreeSans 560 0 0 0 io_out[7]
+port 161 nsew signal tristate
+flabel metal3 s 291760 159190 292400 159246 0 FreeSans 560 0 0 0 io_out[8]
+port 162 nsew signal tristate
+flabel metal3 s 291760 181801 292400 181857 0 FreeSans 560 0 0 0 io_out[9]
+port 163 nsew signal tristate
+flabel metal2 s 62908 -400 62964 240 0 FreeSans 560 90 0 0 la_data_in[0]
+port 164 nsew signal input
+flabel metal2 s 240208 -400 240264 240 0 FreeSans 560 90 0 0 la_data_in[100]
+port 165 nsew signal input
+flabel metal2 s 241981 -400 242037 240 0 FreeSans 560 90 0 0 la_data_in[101]
+port 166 nsew signal input
+flabel metal2 s 243754 -400 243810 240 0 FreeSans 560 90 0 0 la_data_in[102]
+port 167 nsew signal input
+flabel metal2 s 245527 -400 245583 240 0 FreeSans 560 90 0 0 la_data_in[103]
+port 168 nsew signal input
+flabel metal2 s 247300 -400 247356 240 0 FreeSans 560 90 0 0 la_data_in[104]
+port 169 nsew signal input
+flabel metal2 s 249073 -400 249129 240 0 FreeSans 560 90 0 0 la_data_in[105]
+port 170 nsew signal input
+flabel metal2 s 250846 -400 250902 240 0 FreeSans 560 90 0 0 la_data_in[106]
+port 171 nsew signal input
+flabel metal2 s 252619 -400 252675 240 0 FreeSans 560 90 0 0 la_data_in[107]
+port 172 nsew signal input
+flabel metal2 s 254392 -400 254448 240 0 FreeSans 560 90 0 0 la_data_in[108]
+port 173 nsew signal input
+flabel metal2 s 256165 -400 256221 240 0 FreeSans 560 90 0 0 la_data_in[109]
+port 174 nsew signal input
+flabel metal2 s 80638 -400 80694 240 0 FreeSans 560 90 0 0 la_data_in[10]
+port 175 nsew signal input
+flabel metal2 s 257938 -400 257994 240 0 FreeSans 560 90 0 0 la_data_in[110]
+port 176 nsew signal input
+flabel metal2 s 259711 -400 259767 240 0 FreeSans 560 90 0 0 la_data_in[111]
+port 177 nsew signal input
+flabel metal2 s 261484 -400 261540 240 0 FreeSans 560 90 0 0 la_data_in[112]
+port 178 nsew signal input
+flabel metal2 s 263257 -400 263313 240 0 FreeSans 560 90 0 0 la_data_in[113]
+port 179 nsew signal input
+flabel metal2 s 265030 -400 265086 240 0 FreeSans 560 90 0 0 la_data_in[114]
+port 180 nsew signal input
+flabel metal2 s 266803 -400 266859 240 0 FreeSans 560 90 0 0 la_data_in[115]
+port 181 nsew signal input
+flabel metal2 s 268576 -400 268632 240 0 FreeSans 560 90 0 0 la_data_in[116]
+port 182 nsew signal input
+flabel metal2 s 270349 -400 270405 240 0 FreeSans 560 90 0 0 la_data_in[117]
+port 183 nsew signal input
+flabel metal2 s 272122 -400 272178 240 0 FreeSans 560 90 0 0 la_data_in[118]
+port 184 nsew signal input
+flabel metal2 s 273895 -400 273951 240 0 FreeSans 560 90 0 0 la_data_in[119]
+port 185 nsew signal input
+flabel metal2 s 82411 -400 82467 240 0 FreeSans 560 90 0 0 la_data_in[11]
+port 186 nsew signal input
+flabel metal2 s 275668 -400 275724 240 0 FreeSans 560 90 0 0 la_data_in[120]
+port 187 nsew signal input
+flabel metal2 s 277441 -400 277497 240 0 FreeSans 560 90 0 0 la_data_in[121]
+port 188 nsew signal input
+flabel metal2 s 279214 -400 279270 240 0 FreeSans 560 90 0 0 la_data_in[122]
+port 189 nsew signal input
+flabel metal2 s 280987 -400 281043 240 0 FreeSans 560 90 0 0 la_data_in[123]
+port 190 nsew signal input
+flabel metal2 s 282760 -400 282816 240 0 FreeSans 560 90 0 0 la_data_in[124]
+port 191 nsew signal input
+flabel metal2 s 284533 -400 284589 240 0 FreeSans 560 90 0 0 la_data_in[125]
+port 192 nsew signal input
+flabel metal2 s 286306 -400 286362 240 0 FreeSans 560 90 0 0 la_data_in[126]
+port 193 nsew signal input
+flabel metal2 s 288079 -400 288135 240 0 FreeSans 560 90 0 0 la_data_in[127]
+port 194 nsew signal input
+flabel metal2 s 84184 -400 84240 240 0 FreeSans 560 90 0 0 la_data_in[12]
+port 195 nsew signal input
+flabel metal2 s 85957 -400 86013 240 0 FreeSans 560 90 0 0 la_data_in[13]
+port 196 nsew signal input
+flabel metal2 s 87730 -400 87786 240 0 FreeSans 560 90 0 0 la_data_in[14]
+port 197 nsew signal input
+flabel metal2 s 89503 -400 89559 240 0 FreeSans 560 90 0 0 la_data_in[15]
+port 198 nsew signal input
+flabel metal2 s 91276 -400 91332 240 0 FreeSans 560 90 0 0 la_data_in[16]
+port 199 nsew signal input
+flabel metal2 s 93049 -400 93105 240 0 FreeSans 560 90 0 0 la_data_in[17]
+port 200 nsew signal input
+flabel metal2 s 94822 -400 94878 240 0 FreeSans 560 90 0 0 la_data_in[18]
+port 201 nsew signal input
+flabel metal2 s 96595 -400 96651 240 0 FreeSans 560 90 0 0 la_data_in[19]
+port 202 nsew signal input
+flabel metal2 s 64681 -400 64737 240 0 FreeSans 560 90 0 0 la_data_in[1]
+port 203 nsew signal input
+flabel metal2 s 98368 -400 98424 240 0 FreeSans 560 90 0 0 la_data_in[20]
+port 204 nsew signal input
+flabel metal2 s 100141 -400 100197 240 0 FreeSans 560 90 0 0 la_data_in[21]
+port 205 nsew signal input
+flabel metal2 s 101914 -400 101970 240 0 FreeSans 560 90 0 0 la_data_in[22]
+port 206 nsew signal input
+flabel metal2 s 103687 -400 103743 240 0 FreeSans 560 90 0 0 la_data_in[23]
+port 207 nsew signal input
+flabel metal2 s 105460 -400 105516 240 0 FreeSans 560 90 0 0 la_data_in[24]
+port 208 nsew signal input
+flabel metal2 s 107233 -400 107289 240 0 FreeSans 560 90 0 0 la_data_in[25]
+port 209 nsew signal input
+flabel metal2 s 109006 -400 109062 240 0 FreeSans 560 90 0 0 la_data_in[26]
+port 210 nsew signal input
+flabel metal2 s 110779 -400 110835 240 0 FreeSans 560 90 0 0 la_data_in[27]
+port 211 nsew signal input
+flabel metal2 s 112552 -400 112608 240 0 FreeSans 560 90 0 0 la_data_in[28]
+port 212 nsew signal input
+flabel metal2 s 114325 -400 114381 240 0 FreeSans 560 90 0 0 la_data_in[29]
+port 213 nsew signal input
+flabel metal2 s 66454 -400 66510 240 0 FreeSans 560 90 0 0 la_data_in[2]
+port 214 nsew signal input
+flabel metal2 s 116098 -400 116154 240 0 FreeSans 560 90 0 0 la_data_in[30]
+port 215 nsew signal input
+flabel metal2 s 117871 -400 117927 240 0 FreeSans 560 90 0 0 la_data_in[31]
+port 216 nsew signal input
+flabel metal2 s 119644 -400 119700 240 0 FreeSans 560 90 0 0 la_data_in[32]
+port 217 nsew signal input
+flabel metal2 s 121417 -400 121473 240 0 FreeSans 560 90 0 0 la_data_in[33]
+port 218 nsew signal input
+flabel metal2 s 123190 -400 123246 240 0 FreeSans 560 90 0 0 la_data_in[34]
+port 219 nsew signal input
+flabel metal2 s 124963 -400 125019 240 0 FreeSans 560 90 0 0 la_data_in[35]
+port 220 nsew signal input
+flabel metal2 s 126736 -400 126792 240 0 FreeSans 560 90 0 0 la_data_in[36]
+port 221 nsew signal input
+flabel metal2 s 128509 -400 128565 240 0 FreeSans 560 90 0 0 la_data_in[37]
+port 222 nsew signal input
+flabel metal2 s 130282 -400 130338 240 0 FreeSans 560 90 0 0 la_data_in[38]
+port 223 nsew signal input
+flabel metal2 s 132055 -400 132111 240 0 FreeSans 560 90 0 0 la_data_in[39]
+port 224 nsew signal input
+flabel metal2 s 68227 -400 68283 240 0 FreeSans 560 90 0 0 la_data_in[3]
+port 225 nsew signal input
+flabel metal2 s 133828 -400 133884 240 0 FreeSans 560 90 0 0 la_data_in[40]
+port 226 nsew signal input
+flabel metal2 s 135601 -400 135657 240 0 FreeSans 560 90 0 0 la_data_in[41]
+port 227 nsew signal input
+flabel metal2 s 137374 -400 137430 240 0 FreeSans 560 90 0 0 la_data_in[42]
+port 228 nsew signal input
+flabel metal2 s 139147 -400 139203 240 0 FreeSans 560 90 0 0 la_data_in[43]
+port 229 nsew signal input
+flabel metal2 s 140920 -400 140976 240 0 FreeSans 560 90 0 0 la_data_in[44]
+port 230 nsew signal input
+flabel metal2 s 142693 -400 142749 240 0 FreeSans 560 90 0 0 la_data_in[45]
+port 231 nsew signal input
+flabel metal2 s 144466 -400 144522 240 0 FreeSans 560 90 0 0 la_data_in[46]
+port 232 nsew signal input
+flabel metal2 s 146239 -400 146295 240 0 FreeSans 560 90 0 0 la_data_in[47]
+port 233 nsew signal input
+flabel metal2 s 148012 -400 148068 240 0 FreeSans 560 90 0 0 la_data_in[48]
+port 234 nsew signal input
+flabel metal2 s 149785 -400 149841 240 0 FreeSans 560 90 0 0 la_data_in[49]
+port 235 nsew signal input
+flabel metal2 s 70000 -400 70056 240 0 FreeSans 560 90 0 0 la_data_in[4]
+port 236 nsew signal input
+flabel metal2 s 151558 -400 151614 240 0 FreeSans 560 90 0 0 la_data_in[50]
+port 237 nsew signal input
+flabel metal2 s 153331 -400 153387 240 0 FreeSans 560 90 0 0 la_data_in[51]
+port 238 nsew signal input
+flabel metal2 s 155104 -400 155160 240 0 FreeSans 560 90 0 0 la_data_in[52]
+port 239 nsew signal input
+flabel metal2 s 156877 -400 156933 240 0 FreeSans 560 90 0 0 la_data_in[53]
+port 240 nsew signal input
+flabel metal2 s 158650 -400 158706 240 0 FreeSans 560 90 0 0 la_data_in[54]
+port 241 nsew signal input
+flabel metal2 s 160423 -400 160479 240 0 FreeSans 560 90 0 0 la_data_in[55]
+port 242 nsew signal input
+flabel metal2 s 162196 -400 162252 240 0 FreeSans 560 90 0 0 la_data_in[56]
+port 243 nsew signal input
+flabel metal2 s 163969 -400 164025 240 0 FreeSans 560 90 0 0 la_data_in[57]
+port 244 nsew signal input
+flabel metal2 s 165742 -400 165798 240 0 FreeSans 560 90 0 0 la_data_in[58]
+port 245 nsew signal input
+flabel metal2 s 167515 -400 167571 240 0 FreeSans 560 90 0 0 la_data_in[59]
+port 246 nsew signal input
+flabel metal2 s 71773 -400 71829 240 0 FreeSans 560 90 0 0 la_data_in[5]
+port 247 nsew signal input
+flabel metal2 s 169288 -400 169344 240 0 FreeSans 560 90 0 0 la_data_in[60]
+port 248 nsew signal input
+flabel metal2 s 171061 -400 171117 240 0 FreeSans 560 90 0 0 la_data_in[61]
+port 249 nsew signal input
+flabel metal2 s 172834 -400 172890 240 0 FreeSans 560 90 0 0 la_data_in[62]
+port 250 nsew signal input
+flabel metal2 s 174607 -400 174663 240 0 FreeSans 560 90 0 0 la_data_in[63]
+port 251 nsew signal input
+flabel metal2 s 176380 -400 176436 240 0 FreeSans 560 90 0 0 la_data_in[64]
+port 252 nsew signal input
+flabel metal2 s 178153 -400 178209 240 0 FreeSans 560 90 0 0 la_data_in[65]
+port 253 nsew signal input
+flabel metal2 s 179926 -400 179982 240 0 FreeSans 560 90 0 0 la_data_in[66]
+port 254 nsew signal input
+flabel metal2 s 181699 -400 181755 240 0 FreeSans 560 90 0 0 la_data_in[67]
+port 255 nsew signal input
+flabel metal2 s 183472 -400 183528 240 0 FreeSans 560 90 0 0 la_data_in[68]
+port 256 nsew signal input
+flabel metal2 s 185245 -400 185301 240 0 FreeSans 560 90 0 0 la_data_in[69]
+port 257 nsew signal input
+flabel metal2 s 73546 -400 73602 240 0 FreeSans 560 90 0 0 la_data_in[6]
+port 258 nsew signal input
+flabel metal2 s 187018 -400 187074 240 0 FreeSans 560 90 0 0 la_data_in[70]
+port 259 nsew signal input
+flabel metal2 s 188791 -400 188847 240 0 FreeSans 560 90 0 0 la_data_in[71]
+port 260 nsew signal input
+flabel metal2 s 190564 -400 190620 240 0 FreeSans 560 90 0 0 la_data_in[72]
+port 261 nsew signal input
+flabel metal2 s 192337 -400 192393 240 0 FreeSans 560 90 0 0 la_data_in[73]
+port 262 nsew signal input
+flabel metal2 s 194110 -400 194166 240 0 FreeSans 560 90 0 0 la_data_in[74]
+port 263 nsew signal input
+flabel metal2 s 195883 -400 195939 240 0 FreeSans 560 90 0 0 la_data_in[75]
+port 264 nsew signal input
+flabel metal2 s 197656 -400 197712 240 0 FreeSans 560 90 0 0 la_data_in[76]
+port 265 nsew signal input
+flabel metal2 s 199429 -400 199485 240 0 FreeSans 560 90 0 0 la_data_in[77]
+port 266 nsew signal input
+flabel metal2 s 201202 -400 201258 240 0 FreeSans 560 90 0 0 la_data_in[78]
+port 267 nsew signal input
+flabel metal2 s 202975 -400 203031 240 0 FreeSans 560 90 0 0 la_data_in[79]
+port 268 nsew signal input
+flabel metal2 s 75319 -400 75375 240 0 FreeSans 560 90 0 0 la_data_in[7]
+port 269 nsew signal input
+flabel metal2 s 204748 -400 204804 240 0 FreeSans 560 90 0 0 la_data_in[80]
+port 270 nsew signal input
+flabel metal2 s 206521 -400 206577 240 0 FreeSans 560 90 0 0 la_data_in[81]
+port 271 nsew signal input
+flabel metal2 s 208294 -400 208350 240 0 FreeSans 560 90 0 0 la_data_in[82]
+port 272 nsew signal input
+flabel metal2 s 210067 -400 210123 240 0 FreeSans 560 90 0 0 la_data_in[83]
+port 273 nsew signal input
+flabel metal2 s 211840 -400 211896 240 0 FreeSans 560 90 0 0 la_data_in[84]
+port 274 nsew signal input
+flabel metal2 s 213613 -400 213669 240 0 FreeSans 560 90 0 0 la_data_in[85]
+port 275 nsew signal input
+flabel metal2 s 215386 -400 215442 240 0 FreeSans 560 90 0 0 la_data_in[86]
+port 276 nsew signal input
+flabel metal2 s 217159 -400 217215 240 0 FreeSans 560 90 0 0 la_data_in[87]
+port 277 nsew signal input
+flabel metal2 s 218932 -400 218988 240 0 FreeSans 560 90 0 0 la_data_in[88]
+port 278 nsew signal input
+flabel metal2 s 220705 -400 220761 240 0 FreeSans 560 90 0 0 la_data_in[89]
+port 279 nsew signal input
+flabel metal2 s 77092 -400 77148 240 0 FreeSans 560 90 0 0 la_data_in[8]
+port 280 nsew signal input
+flabel metal2 s 222478 -400 222534 240 0 FreeSans 560 90 0 0 la_data_in[90]
+port 281 nsew signal input
+flabel metal2 s 224251 -400 224307 240 0 FreeSans 560 90 0 0 la_data_in[91]
+port 282 nsew signal input
+flabel metal2 s 226024 -400 226080 240 0 FreeSans 560 90 0 0 la_data_in[92]
+port 283 nsew signal input
+flabel metal2 s 227797 -400 227853 240 0 FreeSans 560 90 0 0 la_data_in[93]
+port 284 nsew signal input
+flabel metal2 s 229570 -400 229626 240 0 FreeSans 560 90 0 0 la_data_in[94]
+port 285 nsew signal input
+flabel metal2 s 231343 -400 231399 240 0 FreeSans 560 90 0 0 la_data_in[95]
+port 286 nsew signal input
+flabel metal2 s 233116 -400 233172 240 0 FreeSans 560 90 0 0 la_data_in[96]
+port 287 nsew signal input
+flabel metal2 s 234889 -400 234945 240 0 FreeSans 560 90 0 0 la_data_in[97]
+port 288 nsew signal input
+flabel metal2 s 236662 -400 236718 240 0 FreeSans 560 90 0 0 la_data_in[98]
+port 289 nsew signal input
+flabel metal2 s 238435 -400 238491 240 0 FreeSans 560 90 0 0 la_data_in[99]
+port 290 nsew signal input
+flabel metal2 s 78865 -400 78921 240 0 FreeSans 560 90 0 0 la_data_in[9]
+port 291 nsew signal input
+flabel metal2 s 63499 -400 63555 240 0 FreeSans 560 90 0 0 la_data_out[0]
+port 292 nsew signal tristate
+flabel metal2 s 240799 -400 240855 240 0 FreeSans 560 90 0 0 la_data_out[100]
+port 293 nsew signal tristate
+flabel metal2 s 242572 -400 242628 240 0 FreeSans 560 90 0 0 la_data_out[101]
+port 294 nsew signal tristate
+flabel metal2 s 244345 -400 244401 240 0 FreeSans 560 90 0 0 la_data_out[102]
+port 295 nsew signal tristate
+flabel metal2 s 246118 -400 246174 240 0 FreeSans 560 90 0 0 la_data_out[103]
+port 296 nsew signal tristate
+flabel metal2 s 247891 -400 247947 240 0 FreeSans 560 90 0 0 la_data_out[104]
+port 297 nsew signal tristate
+flabel metal2 s 249664 -400 249720 240 0 FreeSans 560 90 0 0 la_data_out[105]
+port 298 nsew signal tristate
+flabel metal2 s 251437 -400 251493 240 0 FreeSans 560 90 0 0 la_data_out[106]
+port 299 nsew signal tristate
+flabel metal2 s 253210 -400 253266 240 0 FreeSans 560 90 0 0 la_data_out[107]
+port 300 nsew signal tristate
+flabel metal2 s 254983 -400 255039 240 0 FreeSans 560 90 0 0 la_data_out[108]
+port 301 nsew signal tristate
+flabel metal2 s 256756 -400 256812 240 0 FreeSans 560 90 0 0 la_data_out[109]
+port 302 nsew signal tristate
+flabel metal2 s 81229 -400 81285 240 0 FreeSans 560 90 0 0 la_data_out[10]
+port 303 nsew signal tristate
+flabel metal2 s 258529 -400 258585 240 0 FreeSans 560 90 0 0 la_data_out[110]
+port 304 nsew signal tristate
+flabel metal2 s 260302 -400 260358 240 0 FreeSans 560 90 0 0 la_data_out[111]
+port 305 nsew signal tristate
+flabel metal2 s 262075 -400 262131 240 0 FreeSans 560 90 0 0 la_data_out[112]
+port 306 nsew signal tristate
+flabel metal2 s 263848 -400 263904 240 0 FreeSans 560 90 0 0 la_data_out[113]
+port 307 nsew signal tristate
+flabel metal2 s 265621 -400 265677 240 0 FreeSans 560 90 0 0 la_data_out[114]
+port 308 nsew signal tristate
+flabel metal2 s 267394 -400 267450 240 0 FreeSans 560 90 0 0 la_data_out[115]
+port 309 nsew signal tristate
+flabel metal2 s 269167 -400 269223 240 0 FreeSans 560 90 0 0 la_data_out[116]
+port 310 nsew signal tristate
+flabel metal2 s 270940 -400 270996 240 0 FreeSans 560 90 0 0 la_data_out[117]
+port 311 nsew signal tristate
+flabel metal2 s 272713 -400 272769 240 0 FreeSans 560 90 0 0 la_data_out[118]
+port 312 nsew signal tristate
+flabel metal2 s 274486 -400 274542 240 0 FreeSans 560 90 0 0 la_data_out[119]
+port 313 nsew signal tristate
+flabel metal2 s 83002 -400 83058 240 0 FreeSans 560 90 0 0 la_data_out[11]
+port 314 nsew signal tristate
+flabel metal2 s 276259 -400 276315 240 0 FreeSans 560 90 0 0 la_data_out[120]
+port 315 nsew signal tristate
+flabel metal2 s 278032 -400 278088 240 0 FreeSans 560 90 0 0 la_data_out[121]
+port 316 nsew signal tristate
+flabel metal2 s 279805 -400 279861 240 0 FreeSans 560 90 0 0 la_data_out[122]
+port 317 nsew signal tristate
+flabel metal2 s 281578 -400 281634 240 0 FreeSans 560 90 0 0 la_data_out[123]
+port 318 nsew signal tristate
+flabel metal2 s 283351 -400 283407 240 0 FreeSans 560 90 0 0 la_data_out[124]
+port 319 nsew signal tristate
+flabel metal2 s 285124 -400 285180 240 0 FreeSans 560 90 0 0 la_data_out[125]
+port 320 nsew signal tristate
+flabel metal2 s 286897 -400 286953 240 0 FreeSans 560 90 0 0 la_data_out[126]
+port 321 nsew signal tristate
+flabel metal2 s 288670 -400 288726 240 0 FreeSans 560 90 0 0 la_data_out[127]
+port 322 nsew signal tristate
+flabel metal2 s 84775 -400 84831 240 0 FreeSans 560 90 0 0 la_data_out[12]
+port 323 nsew signal tristate
+flabel metal2 s 86548 -400 86604 240 0 FreeSans 560 90 0 0 la_data_out[13]
+port 324 nsew signal tristate
+flabel metal2 s 88321 -400 88377 240 0 FreeSans 560 90 0 0 la_data_out[14]
+port 325 nsew signal tristate
+flabel metal2 s 90094 -400 90150 240 0 FreeSans 560 90 0 0 la_data_out[15]
+port 326 nsew signal tristate
+flabel metal2 s 91867 -400 91923 240 0 FreeSans 560 90 0 0 la_data_out[16]
+port 327 nsew signal tristate
+flabel metal2 s 93640 -400 93696 240 0 FreeSans 560 90 0 0 la_data_out[17]
+port 328 nsew signal tristate
+flabel metal2 s 95413 -400 95469 240 0 FreeSans 560 90 0 0 la_data_out[18]
+port 329 nsew signal tristate
+flabel metal2 s 97186 -400 97242 240 0 FreeSans 560 90 0 0 la_data_out[19]
+port 330 nsew signal tristate
+flabel metal2 s 65272 -400 65328 240 0 FreeSans 560 90 0 0 la_data_out[1]
+port 331 nsew signal tristate
+flabel metal2 s 98959 -400 99015 240 0 FreeSans 560 90 0 0 la_data_out[20]
+port 332 nsew signal tristate
+flabel metal2 s 100732 -400 100788 240 0 FreeSans 560 90 0 0 la_data_out[21]
+port 333 nsew signal tristate
+flabel metal2 s 102505 -400 102561 240 0 FreeSans 560 90 0 0 la_data_out[22]
+port 334 nsew signal tristate
+flabel metal2 s 104278 -400 104334 240 0 FreeSans 560 90 0 0 la_data_out[23]
+port 335 nsew signal tristate
+flabel metal2 s 106051 -400 106107 240 0 FreeSans 560 90 0 0 la_data_out[24]
+port 336 nsew signal tristate
+flabel metal2 s 107824 -400 107880 240 0 FreeSans 560 90 0 0 la_data_out[25]
+port 337 nsew signal tristate
+flabel metal2 s 109597 -400 109653 240 0 FreeSans 560 90 0 0 la_data_out[26]
+port 338 nsew signal tristate
+flabel metal2 s 111370 -400 111426 240 0 FreeSans 560 90 0 0 la_data_out[27]
+port 339 nsew signal tristate
+flabel metal2 s 113143 -400 113199 240 0 FreeSans 560 90 0 0 la_data_out[28]
+port 340 nsew signal tristate
+flabel metal2 s 114916 -400 114972 240 0 FreeSans 560 90 0 0 la_data_out[29]
+port 341 nsew signal tristate
+flabel metal2 s 67045 -400 67101 240 0 FreeSans 560 90 0 0 la_data_out[2]
+port 342 nsew signal tristate
+flabel metal2 s 116689 -400 116745 240 0 FreeSans 560 90 0 0 la_data_out[30]
+port 343 nsew signal tristate
+flabel metal2 s 118462 -400 118518 240 0 FreeSans 560 90 0 0 la_data_out[31]
+port 344 nsew signal tristate
+flabel metal2 s 120235 -400 120291 240 0 FreeSans 560 90 0 0 la_data_out[32]
+port 345 nsew signal tristate
+flabel metal2 s 122008 -400 122064 240 0 FreeSans 560 90 0 0 la_data_out[33]
+port 346 nsew signal tristate
+flabel metal2 s 123781 -400 123837 240 0 FreeSans 560 90 0 0 la_data_out[34]
+port 347 nsew signal tristate
+flabel metal2 s 125554 -400 125610 240 0 FreeSans 560 90 0 0 la_data_out[35]
+port 348 nsew signal tristate
+flabel metal2 s 127327 -400 127383 240 0 FreeSans 560 90 0 0 la_data_out[36]
+port 349 nsew signal tristate
+flabel metal2 s 129100 -400 129156 240 0 FreeSans 560 90 0 0 la_data_out[37]
+port 350 nsew signal tristate
+flabel metal2 s 130873 -400 130929 240 0 FreeSans 560 90 0 0 la_data_out[38]
+port 351 nsew signal tristate
+flabel metal2 s 132646 -400 132702 240 0 FreeSans 560 90 0 0 la_data_out[39]
+port 352 nsew signal tristate
+flabel metal2 s 68818 -400 68874 240 0 FreeSans 560 90 0 0 la_data_out[3]
+port 353 nsew signal tristate
+flabel metal2 s 134419 -400 134475 240 0 FreeSans 560 90 0 0 la_data_out[40]
+port 354 nsew signal tristate
+flabel metal2 s 136192 -400 136248 240 0 FreeSans 560 90 0 0 la_data_out[41]
+port 355 nsew signal tristate
+flabel metal2 s 137965 -400 138021 240 0 FreeSans 560 90 0 0 la_data_out[42]
+port 356 nsew signal tristate
+flabel metal2 s 139738 -400 139794 240 0 FreeSans 560 90 0 0 la_data_out[43]
+port 357 nsew signal tristate
+flabel metal2 s 141511 -400 141567 240 0 FreeSans 560 90 0 0 la_data_out[44]
+port 358 nsew signal tristate
+flabel metal2 s 143284 -400 143340 240 0 FreeSans 560 90 0 0 la_data_out[45]
+port 359 nsew signal tristate
+flabel metal2 s 145057 -400 145113 240 0 FreeSans 560 90 0 0 la_data_out[46]
+port 360 nsew signal tristate
+flabel metal2 s 146830 -400 146886 240 0 FreeSans 560 90 0 0 la_data_out[47]
+port 361 nsew signal tristate
+flabel metal2 s 148603 -400 148659 240 0 FreeSans 560 90 0 0 la_data_out[48]
+port 362 nsew signal tristate
+flabel metal2 s 150376 -400 150432 240 0 FreeSans 560 90 0 0 la_data_out[49]
+port 363 nsew signal tristate
+flabel metal2 s 70591 -400 70647 240 0 FreeSans 560 90 0 0 la_data_out[4]
+port 364 nsew signal tristate
+flabel metal2 s 152149 -400 152205 240 0 FreeSans 560 90 0 0 la_data_out[50]
+port 365 nsew signal tristate
+flabel metal2 s 153922 -400 153978 240 0 FreeSans 560 90 0 0 la_data_out[51]
+port 366 nsew signal tristate
+flabel metal2 s 155695 -400 155751 240 0 FreeSans 560 90 0 0 la_data_out[52]
+port 367 nsew signal tristate
+flabel metal2 s 157468 -400 157524 240 0 FreeSans 560 90 0 0 la_data_out[53]
+port 368 nsew signal tristate
+flabel metal2 s 159241 -400 159297 240 0 FreeSans 560 90 0 0 la_data_out[54]
+port 369 nsew signal tristate
+flabel metal2 s 161014 -400 161070 240 0 FreeSans 560 90 0 0 la_data_out[55]
+port 370 nsew signal tristate
+flabel metal2 s 162787 -400 162843 240 0 FreeSans 560 90 0 0 la_data_out[56]
+port 371 nsew signal tristate
+flabel metal2 s 164560 -400 164616 240 0 FreeSans 560 90 0 0 la_data_out[57]
+port 372 nsew signal tristate
+flabel metal2 s 166333 -400 166389 240 0 FreeSans 560 90 0 0 la_data_out[58]
+port 373 nsew signal tristate
+flabel metal2 s 168106 -400 168162 240 0 FreeSans 560 90 0 0 la_data_out[59]
+port 374 nsew signal tristate
+flabel metal2 s 72364 -400 72420 240 0 FreeSans 560 90 0 0 la_data_out[5]
+port 375 nsew signal tristate
+flabel metal2 s 169879 -400 169935 240 0 FreeSans 560 90 0 0 la_data_out[60]
+port 376 nsew signal tristate
+flabel metal2 s 171652 -400 171708 240 0 FreeSans 560 90 0 0 la_data_out[61]
+port 377 nsew signal tristate
+flabel metal2 s 173425 -400 173481 240 0 FreeSans 560 90 0 0 la_data_out[62]
+port 378 nsew signal tristate
+flabel metal2 s 175198 -400 175254 240 0 FreeSans 560 90 0 0 la_data_out[63]
+port 379 nsew signal tristate
+flabel metal2 s 176971 -400 177027 240 0 FreeSans 560 90 0 0 la_data_out[64]
+port 380 nsew signal tristate
+flabel metal2 s 178744 -400 178800 240 0 FreeSans 560 90 0 0 la_data_out[65]
+port 381 nsew signal tristate
+flabel metal2 s 180517 -400 180573 240 0 FreeSans 560 90 0 0 la_data_out[66]
+port 382 nsew signal tristate
+flabel metal2 s 182290 -400 182346 240 0 FreeSans 560 90 0 0 la_data_out[67]
+port 383 nsew signal tristate
+flabel metal2 s 184063 -400 184119 240 0 FreeSans 560 90 0 0 la_data_out[68]
+port 384 nsew signal tristate
+flabel metal2 s 185836 -400 185892 240 0 FreeSans 560 90 0 0 la_data_out[69]
+port 385 nsew signal tristate
+flabel metal2 s 74137 -400 74193 240 0 FreeSans 560 90 0 0 la_data_out[6]
+port 386 nsew signal tristate
+flabel metal2 s 187609 -400 187665 240 0 FreeSans 560 90 0 0 la_data_out[70]
+port 387 nsew signal tristate
+flabel metal2 s 189382 -400 189438 240 0 FreeSans 560 90 0 0 la_data_out[71]
+port 388 nsew signal tristate
+flabel metal2 s 191155 -400 191211 240 0 FreeSans 560 90 0 0 la_data_out[72]
+port 389 nsew signal tristate
+flabel metal2 s 192928 -400 192984 240 0 FreeSans 560 90 0 0 la_data_out[73]
+port 390 nsew signal tristate
+flabel metal2 s 194701 -400 194757 240 0 FreeSans 560 90 0 0 la_data_out[74]
+port 391 nsew signal tristate
+flabel metal2 s 196474 -400 196530 240 0 FreeSans 560 90 0 0 la_data_out[75]
+port 392 nsew signal tristate
+flabel metal2 s 198247 -400 198303 240 0 FreeSans 560 90 0 0 la_data_out[76]
+port 393 nsew signal tristate
+flabel metal2 s 200020 -400 200076 240 0 FreeSans 560 90 0 0 la_data_out[77]
+port 394 nsew signal tristate
+flabel metal2 s 201793 -400 201849 240 0 FreeSans 560 90 0 0 la_data_out[78]
+port 395 nsew signal tristate
+flabel metal2 s 203566 -400 203622 240 0 FreeSans 560 90 0 0 la_data_out[79]
+port 396 nsew signal tristate
+flabel metal2 s 75910 -400 75966 240 0 FreeSans 560 90 0 0 la_data_out[7]
+port 397 nsew signal tristate
+flabel metal2 s 205339 -400 205395 240 0 FreeSans 560 90 0 0 la_data_out[80]
+port 398 nsew signal tristate
+flabel metal2 s 207112 -400 207168 240 0 FreeSans 560 90 0 0 la_data_out[81]
+port 399 nsew signal tristate
+flabel metal2 s 208885 -400 208941 240 0 FreeSans 560 90 0 0 la_data_out[82]
+port 400 nsew signal tristate
+flabel metal2 s 210658 -400 210714 240 0 FreeSans 560 90 0 0 la_data_out[83]
+port 401 nsew signal tristate
+flabel metal2 s 212431 -400 212487 240 0 FreeSans 560 90 0 0 la_data_out[84]
+port 402 nsew signal tristate
+flabel metal2 s 214204 -400 214260 240 0 FreeSans 560 90 0 0 la_data_out[85]
+port 403 nsew signal tristate
+flabel metal2 s 215977 -400 216033 240 0 FreeSans 560 90 0 0 la_data_out[86]
+port 404 nsew signal tristate
+flabel metal2 s 217750 -400 217806 240 0 FreeSans 560 90 0 0 la_data_out[87]
+port 405 nsew signal tristate
+flabel metal2 s 219523 -400 219579 240 0 FreeSans 560 90 0 0 la_data_out[88]
+port 406 nsew signal tristate
+flabel metal2 s 221296 -400 221352 240 0 FreeSans 560 90 0 0 la_data_out[89]
+port 407 nsew signal tristate
+flabel metal2 s 77683 -400 77739 240 0 FreeSans 560 90 0 0 la_data_out[8]
+port 408 nsew signal tristate
+flabel metal2 s 223069 -400 223125 240 0 FreeSans 560 90 0 0 la_data_out[90]
+port 409 nsew signal tristate
+flabel metal2 s 224842 -400 224898 240 0 FreeSans 560 90 0 0 la_data_out[91]
+port 410 nsew signal tristate
+flabel metal2 s 226615 -400 226671 240 0 FreeSans 560 90 0 0 la_data_out[92]
+port 411 nsew signal tristate
+flabel metal2 s 228388 -400 228444 240 0 FreeSans 560 90 0 0 la_data_out[93]
+port 412 nsew signal tristate
+flabel metal2 s 230161 -400 230217 240 0 FreeSans 560 90 0 0 la_data_out[94]
+port 413 nsew signal tristate
+flabel metal2 s 231934 -400 231990 240 0 FreeSans 560 90 0 0 la_data_out[95]
+port 414 nsew signal tristate
+flabel metal2 s 233707 -400 233763 240 0 FreeSans 560 90 0 0 la_data_out[96]
+port 415 nsew signal tristate
+flabel metal2 s 235480 -400 235536 240 0 FreeSans 560 90 0 0 la_data_out[97]
+port 416 nsew signal tristate
+flabel metal2 s 237253 -400 237309 240 0 FreeSans 560 90 0 0 la_data_out[98]
+port 417 nsew signal tristate
+flabel metal2 s 239026 -400 239082 240 0 FreeSans 560 90 0 0 la_data_out[99]
+port 418 nsew signal tristate
+flabel metal2 s 79456 -400 79512 240 0 FreeSans 560 90 0 0 la_data_out[9]
+port 419 nsew signal tristate
+flabel metal2 s 64090 -400 64146 240 0 FreeSans 560 90 0 0 la_oenb[0]
+port 420 nsew signal input
+flabel metal2 s 241390 -400 241446 240 0 FreeSans 560 90 0 0 la_oenb[100]
+port 421 nsew signal input
+flabel metal2 s 243163 -400 243219 240 0 FreeSans 560 90 0 0 la_oenb[101]
+port 422 nsew signal input
+flabel metal2 s 244936 -400 244992 240 0 FreeSans 560 90 0 0 la_oenb[102]
+port 423 nsew signal input
+flabel metal2 s 246709 -400 246765 240 0 FreeSans 560 90 0 0 la_oenb[103]
+port 424 nsew signal input
+flabel metal2 s 248482 -400 248538 240 0 FreeSans 560 90 0 0 la_oenb[104]
+port 425 nsew signal input
+flabel metal2 s 250255 -400 250311 240 0 FreeSans 560 90 0 0 la_oenb[105]
+port 426 nsew signal input
+flabel metal2 s 252028 -400 252084 240 0 FreeSans 560 90 0 0 la_oenb[106]
+port 427 nsew signal input
+flabel metal2 s 253801 -400 253857 240 0 FreeSans 560 90 0 0 la_oenb[107]
+port 428 nsew signal input
+flabel metal2 s 255574 -400 255630 240 0 FreeSans 560 90 0 0 la_oenb[108]
+port 429 nsew signal input
+flabel metal2 s 257347 -400 257403 240 0 FreeSans 560 90 0 0 la_oenb[109]
+port 430 nsew signal input
+flabel metal2 s 81820 -400 81876 240 0 FreeSans 560 90 0 0 la_oenb[10]
+port 431 nsew signal input
+flabel metal2 s 259120 -400 259176 240 0 FreeSans 560 90 0 0 la_oenb[110]
+port 432 nsew signal input
+flabel metal2 s 260893 -400 260949 240 0 FreeSans 560 90 0 0 la_oenb[111]
+port 433 nsew signal input
+flabel metal2 s 262666 -400 262722 240 0 FreeSans 560 90 0 0 la_oenb[112]
+port 434 nsew signal input
+flabel metal2 s 264439 -400 264495 240 0 FreeSans 560 90 0 0 la_oenb[113]
+port 435 nsew signal input
+flabel metal2 s 266212 -400 266268 240 0 FreeSans 560 90 0 0 la_oenb[114]
+port 436 nsew signal input
+flabel metal2 s 267985 -400 268041 240 0 FreeSans 560 90 0 0 la_oenb[115]
+port 437 nsew signal input
+flabel metal2 s 269758 -400 269814 240 0 FreeSans 560 90 0 0 la_oenb[116]
+port 438 nsew signal input
+flabel metal2 s 271531 -400 271587 240 0 FreeSans 560 90 0 0 la_oenb[117]
+port 439 nsew signal input
+flabel metal2 s 273304 -400 273360 240 0 FreeSans 560 90 0 0 la_oenb[118]
+port 440 nsew signal input
+flabel metal2 s 275077 -400 275133 240 0 FreeSans 560 90 0 0 la_oenb[119]
+port 441 nsew signal input
+flabel metal2 s 83593 -400 83649 240 0 FreeSans 560 90 0 0 la_oenb[11]
+port 442 nsew signal input
+flabel metal2 s 276850 -400 276906 240 0 FreeSans 560 90 0 0 la_oenb[120]
+port 443 nsew signal input
+flabel metal2 s 278623 -400 278679 240 0 FreeSans 560 90 0 0 la_oenb[121]
+port 444 nsew signal input
+flabel metal2 s 280396 -400 280452 240 0 FreeSans 560 90 0 0 la_oenb[122]
+port 445 nsew signal input
+flabel metal2 s 282169 -400 282225 240 0 FreeSans 560 90 0 0 la_oenb[123]
+port 446 nsew signal input
+flabel metal2 s 283942 -400 283998 240 0 FreeSans 560 90 0 0 la_oenb[124]
+port 447 nsew signal input
+flabel metal2 s 285715 -400 285771 240 0 FreeSans 560 90 0 0 la_oenb[125]
+port 448 nsew signal input
+flabel metal2 s 287488 -400 287544 240 0 FreeSans 560 90 0 0 la_oenb[126]
+port 449 nsew signal input
+flabel metal2 s 289261 -400 289317 240 0 FreeSans 560 90 0 0 la_oenb[127]
+port 450 nsew signal input
+flabel metal2 s 85366 -400 85422 240 0 FreeSans 560 90 0 0 la_oenb[12]
+port 451 nsew signal input
+flabel metal2 s 87139 -400 87195 240 0 FreeSans 560 90 0 0 la_oenb[13]
+port 452 nsew signal input
+flabel metal2 s 88912 -400 88968 240 0 FreeSans 560 90 0 0 la_oenb[14]
+port 453 nsew signal input
+flabel metal2 s 90685 -400 90741 240 0 FreeSans 560 90 0 0 la_oenb[15]
+port 454 nsew signal input
+flabel metal2 s 92458 -400 92514 240 0 FreeSans 560 90 0 0 la_oenb[16]
+port 455 nsew signal input
+flabel metal2 s 94231 -400 94287 240 0 FreeSans 560 90 0 0 la_oenb[17]
+port 456 nsew signal input
+flabel metal2 s 96004 -400 96060 240 0 FreeSans 560 90 0 0 la_oenb[18]
+port 457 nsew signal input
+flabel metal2 s 97777 -400 97833 240 0 FreeSans 560 90 0 0 la_oenb[19]
+port 458 nsew signal input
+flabel metal2 s 65863 -400 65919 240 0 FreeSans 560 90 0 0 la_oenb[1]
+port 459 nsew signal input
+flabel metal2 s 99550 -400 99606 240 0 FreeSans 560 90 0 0 la_oenb[20]
+port 460 nsew signal input
+flabel metal2 s 101323 -400 101379 240 0 FreeSans 560 90 0 0 la_oenb[21]
+port 461 nsew signal input
+flabel metal2 s 103096 -400 103152 240 0 FreeSans 560 90 0 0 la_oenb[22]
+port 462 nsew signal input
+flabel metal2 s 104869 -400 104925 240 0 FreeSans 560 90 0 0 la_oenb[23]
+port 463 nsew signal input
+flabel metal2 s 106642 -400 106698 240 0 FreeSans 560 90 0 0 la_oenb[24]
+port 464 nsew signal input
+flabel metal2 s 108415 -400 108471 240 0 FreeSans 560 90 0 0 la_oenb[25]
+port 465 nsew signal input
+flabel metal2 s 110188 -400 110244 240 0 FreeSans 560 90 0 0 la_oenb[26]
+port 466 nsew signal input
+flabel metal2 s 111961 -400 112017 240 0 FreeSans 560 90 0 0 la_oenb[27]
+port 467 nsew signal input
+flabel metal2 s 113734 -400 113790 240 0 FreeSans 560 90 0 0 la_oenb[28]
+port 468 nsew signal input
+flabel metal2 s 115507 -400 115563 240 0 FreeSans 560 90 0 0 la_oenb[29]
+port 469 nsew signal input
+flabel metal2 s 67636 -400 67692 240 0 FreeSans 560 90 0 0 la_oenb[2]
+port 470 nsew signal input
+flabel metal2 s 117280 -400 117336 240 0 FreeSans 560 90 0 0 la_oenb[30]
+port 471 nsew signal input
+flabel metal2 s 119053 -400 119109 240 0 FreeSans 560 90 0 0 la_oenb[31]
+port 472 nsew signal input
+flabel metal2 s 120826 -400 120882 240 0 FreeSans 560 90 0 0 la_oenb[32]
+port 473 nsew signal input
+flabel metal2 s 122599 -400 122655 240 0 FreeSans 560 90 0 0 la_oenb[33]
+port 474 nsew signal input
+flabel metal2 s 124372 -400 124428 240 0 FreeSans 560 90 0 0 la_oenb[34]
+port 475 nsew signal input
+flabel metal2 s 126145 -400 126201 240 0 FreeSans 560 90 0 0 la_oenb[35]
+port 476 nsew signal input
+flabel metal2 s 127918 -400 127974 240 0 FreeSans 560 90 0 0 la_oenb[36]
+port 477 nsew signal input
+flabel metal2 s 129691 -400 129747 240 0 FreeSans 560 90 0 0 la_oenb[37]
+port 478 nsew signal input
+flabel metal2 s 131464 -400 131520 240 0 FreeSans 560 90 0 0 la_oenb[38]
+port 479 nsew signal input
+flabel metal2 s 133237 -400 133293 240 0 FreeSans 560 90 0 0 la_oenb[39]
+port 480 nsew signal input
+flabel metal2 s 69409 -400 69465 240 0 FreeSans 560 90 0 0 la_oenb[3]
+port 481 nsew signal input
+flabel metal2 s 135010 -400 135066 240 0 FreeSans 560 90 0 0 la_oenb[40]
+port 482 nsew signal input
+flabel metal2 s 136783 -400 136839 240 0 FreeSans 560 90 0 0 la_oenb[41]
+port 483 nsew signal input
+flabel metal2 s 138556 -400 138612 240 0 FreeSans 560 90 0 0 la_oenb[42]
+port 484 nsew signal input
+flabel metal2 s 140329 -400 140385 240 0 FreeSans 560 90 0 0 la_oenb[43]
+port 485 nsew signal input
+flabel metal2 s 142102 -400 142158 240 0 FreeSans 560 90 0 0 la_oenb[44]
+port 486 nsew signal input
+flabel metal2 s 143875 -400 143931 240 0 FreeSans 560 90 0 0 la_oenb[45]
+port 487 nsew signal input
+flabel metal2 s 145648 -400 145704 240 0 FreeSans 560 90 0 0 la_oenb[46]
+port 488 nsew signal input
+flabel metal2 s 147421 -400 147477 240 0 FreeSans 560 90 0 0 la_oenb[47]
+port 489 nsew signal input
+flabel metal2 s 149194 -400 149250 240 0 FreeSans 560 90 0 0 la_oenb[48]
+port 490 nsew signal input
+flabel metal2 s 150967 -400 151023 240 0 FreeSans 560 90 0 0 la_oenb[49]
+port 491 nsew signal input
+flabel metal2 s 71182 -400 71238 240 0 FreeSans 560 90 0 0 la_oenb[4]
+port 492 nsew signal input
+flabel metal2 s 152740 -400 152796 240 0 FreeSans 560 90 0 0 la_oenb[50]
+port 493 nsew signal input
+flabel metal2 s 154513 -400 154569 240 0 FreeSans 560 90 0 0 la_oenb[51]
+port 494 nsew signal input
+flabel metal2 s 156286 -400 156342 240 0 FreeSans 560 90 0 0 la_oenb[52]
+port 495 nsew signal input
+flabel metal2 s 158059 -400 158115 240 0 FreeSans 560 90 0 0 la_oenb[53]
+port 496 nsew signal input
+flabel metal2 s 159832 -400 159888 240 0 FreeSans 560 90 0 0 la_oenb[54]
+port 497 nsew signal input
+flabel metal2 s 161605 -400 161661 240 0 FreeSans 560 90 0 0 la_oenb[55]
+port 498 nsew signal input
+flabel metal2 s 163378 -400 163434 240 0 FreeSans 560 90 0 0 la_oenb[56]
+port 499 nsew signal input
+flabel metal2 s 165151 -400 165207 240 0 FreeSans 560 90 0 0 la_oenb[57]
+port 500 nsew signal input
+flabel metal2 s 166924 -400 166980 240 0 FreeSans 560 90 0 0 la_oenb[58]
+port 501 nsew signal input
+flabel metal2 s 168697 -400 168753 240 0 FreeSans 560 90 0 0 la_oenb[59]
+port 502 nsew signal input
+flabel metal2 s 72955 -400 73011 240 0 FreeSans 560 90 0 0 la_oenb[5]
+port 503 nsew signal input
+flabel metal2 s 170470 -400 170526 240 0 FreeSans 560 90 0 0 la_oenb[60]
+port 504 nsew signal input
+flabel metal2 s 172243 -400 172299 240 0 FreeSans 560 90 0 0 la_oenb[61]
+port 505 nsew signal input
+flabel metal2 s 174016 -400 174072 240 0 FreeSans 560 90 0 0 la_oenb[62]
+port 506 nsew signal input
+flabel metal2 s 175789 -400 175845 240 0 FreeSans 560 90 0 0 la_oenb[63]
+port 507 nsew signal input
+flabel metal2 s 177562 -400 177618 240 0 FreeSans 560 90 0 0 la_oenb[64]
+port 508 nsew signal input
+flabel metal2 s 179335 -400 179391 240 0 FreeSans 560 90 0 0 la_oenb[65]
+port 509 nsew signal input
+flabel metal2 s 181108 -400 181164 240 0 FreeSans 560 90 0 0 la_oenb[66]
+port 510 nsew signal input
+flabel metal2 s 182881 -400 182937 240 0 FreeSans 560 90 0 0 la_oenb[67]
+port 511 nsew signal input
+flabel metal2 s 184654 -400 184710 240 0 FreeSans 560 90 0 0 la_oenb[68]
+port 512 nsew signal input
+flabel metal2 s 186427 -400 186483 240 0 FreeSans 560 90 0 0 la_oenb[69]
+port 513 nsew signal input
+flabel metal2 s 74728 -400 74784 240 0 FreeSans 560 90 0 0 la_oenb[6]
+port 514 nsew signal input
+flabel metal2 s 188200 -400 188256 240 0 FreeSans 560 90 0 0 la_oenb[70]
+port 515 nsew signal input
+flabel metal2 s 189973 -400 190029 240 0 FreeSans 560 90 0 0 la_oenb[71]
+port 516 nsew signal input
+flabel metal2 s 191746 -400 191802 240 0 FreeSans 560 90 0 0 la_oenb[72]
+port 517 nsew signal input
+flabel metal2 s 193519 -400 193575 240 0 FreeSans 560 90 0 0 la_oenb[73]
+port 518 nsew signal input
+flabel metal2 s 195292 -400 195348 240 0 FreeSans 560 90 0 0 la_oenb[74]
+port 519 nsew signal input
+flabel metal2 s 197065 -400 197121 240 0 FreeSans 560 90 0 0 la_oenb[75]
+port 520 nsew signal input
+flabel metal2 s 198838 -400 198894 240 0 FreeSans 560 90 0 0 la_oenb[76]
+port 521 nsew signal input
+flabel metal2 s 200611 -400 200667 240 0 FreeSans 560 90 0 0 la_oenb[77]
+port 522 nsew signal input
+flabel metal2 s 202384 -400 202440 240 0 FreeSans 560 90 0 0 la_oenb[78]
+port 523 nsew signal input
+flabel metal2 s 204157 -400 204213 240 0 FreeSans 560 90 0 0 la_oenb[79]
+port 524 nsew signal input
+flabel metal2 s 76501 -400 76557 240 0 FreeSans 560 90 0 0 la_oenb[7]
+port 525 nsew signal input
+flabel metal2 s 205930 -400 205986 240 0 FreeSans 560 90 0 0 la_oenb[80]
+port 526 nsew signal input
+flabel metal2 s 207703 -400 207759 240 0 FreeSans 560 90 0 0 la_oenb[81]
+port 527 nsew signal input
+flabel metal2 s 209476 -400 209532 240 0 FreeSans 560 90 0 0 la_oenb[82]
+port 528 nsew signal input
+flabel metal2 s 211249 -400 211305 240 0 FreeSans 560 90 0 0 la_oenb[83]
+port 529 nsew signal input
+flabel metal2 s 213022 -400 213078 240 0 FreeSans 560 90 0 0 la_oenb[84]
+port 530 nsew signal input
+flabel metal2 s 214795 -400 214851 240 0 FreeSans 560 90 0 0 la_oenb[85]
+port 531 nsew signal input
+flabel metal2 s 216568 -400 216624 240 0 FreeSans 560 90 0 0 la_oenb[86]
+port 532 nsew signal input
+flabel metal2 s 218341 -400 218397 240 0 FreeSans 560 90 0 0 la_oenb[87]
+port 533 nsew signal input
+flabel metal2 s 220114 -400 220170 240 0 FreeSans 560 90 0 0 la_oenb[88]
+port 534 nsew signal input
+flabel metal2 s 221887 -400 221943 240 0 FreeSans 560 90 0 0 la_oenb[89]
+port 535 nsew signal input
+flabel metal2 s 78274 -400 78330 240 0 FreeSans 560 90 0 0 la_oenb[8]
+port 536 nsew signal input
+flabel metal2 s 223660 -400 223716 240 0 FreeSans 560 90 0 0 la_oenb[90]
+port 537 nsew signal input
+flabel metal2 s 225433 -400 225489 240 0 FreeSans 560 90 0 0 la_oenb[91]
+port 538 nsew signal input
+flabel metal2 s 227206 -400 227262 240 0 FreeSans 560 90 0 0 la_oenb[92]
+port 539 nsew signal input
+flabel metal2 s 228979 -400 229035 240 0 FreeSans 560 90 0 0 la_oenb[93]
+port 540 nsew signal input
+flabel metal2 s 230752 -400 230808 240 0 FreeSans 560 90 0 0 la_oenb[94]
+port 541 nsew signal input
+flabel metal2 s 232525 -400 232581 240 0 FreeSans 560 90 0 0 la_oenb[95]
+port 542 nsew signal input
+flabel metal2 s 234298 -400 234354 240 0 FreeSans 560 90 0 0 la_oenb[96]
+port 543 nsew signal input
+flabel metal2 s 236071 -400 236127 240 0 FreeSans 560 90 0 0 la_oenb[97]
+port 544 nsew signal input
+flabel metal2 s 237844 -400 237900 240 0 FreeSans 560 90 0 0 la_oenb[98]
+port 545 nsew signal input
+flabel metal2 s 239617 -400 239673 240 0 FreeSans 560 90 0 0 la_oenb[99]
+port 546 nsew signal input
+flabel metal2 s 80047 -400 80103 240 0 FreeSans 560 90 0 0 la_oenb[9]
+port 547 nsew signal input
+flabel metal2 s 289852 -400 289908 240 0 FreeSans 560 90 0 0 user_clock2
+port 548 nsew signal input
+flabel metal2 s 290443 -400 290499 240 0 FreeSans 560 90 0 0 user_irq[0]
+port 549 nsew signal tristate
+flabel metal2 s 291034 -400 291090 240 0 FreeSans 560 90 0 0 user_irq[1]
+port 550 nsew signal tristate
+flabel metal2 s 291625 -400 291681 240 0 FreeSans 560 90 0 0 user_irq[2]
+port 551 nsew signal tristate
+flabel metal3 s 291170 319892 292400 322292 0 FreeSans 560 0 0 0 vccd1
+port 552 nsew signal bidirectional
+flabel metal3 s 291170 314892 292400 317292 0 FreeSans 560 0 0 0 vccd1
+port 553 nsew signal bidirectional
+flabel metal3 s 0 321921 830 324321 0 FreeSans 560 0 0 0 vccd2
+port 554 nsew signal bidirectional
+flabel metal3 s 0 316921 830 319321 0 FreeSans 560 0 0 0 vccd2
+port 555 nsew signal bidirectional
+flabel metal3 s 291170 270281 292400 272681 0 FreeSans 560 0 0 0 vdda1
+port 556 nsew signal bidirectional
+flabel metal3 s 291170 275281 292400 277681 0 FreeSans 560 0 0 0 vdda1
+port 557 nsew signal bidirectional
+flabel metal3 s 291170 117615 292400 120015 0 FreeSans 560 0 0 0 vdda1
+port 558 nsew signal bidirectional
+flabel metal3 s 291170 112615 292400 115015 0 FreeSans 560 0 0 0 vdda1
+port 559 nsew signal bidirectional
+flabel metal3 s 0 102444 830 104844 0 FreeSans 560 0 0 0 vdda2
+port 560 nsew signal bidirectional
+flabel metal3 s 0 107444 830 109844 0 FreeSans 560 0 0 0 vdda2
+port 561 nsew signal bidirectional
+flabel metal3 s 260297 351170 262697 352400 0 FreeSans 960 180 0 0 vssa1
+port 562 nsew signal bidirectional
+flabel metal3 s 255297 351170 257697 352400 0 FreeSans 960 180 0 0 vssa1
+port 563 nsew signal bidirectional
+flabel metal3 s 291170 73415 292400 75815 0 FreeSans 560 0 0 0 vssa1
+port 564 nsew signal bidirectional
+flabel metal3 s 291170 68415 292400 70815 0 FreeSans 560 0 0 0 vssa1
+port 565 nsew signal bidirectional
+flabel metal3 s 0 279721 830 282121 0 FreeSans 560 0 0 0 vssa2
+port 566 nsew signal bidirectional
+flabel metal3 s 0 274721 830 277121 0 FreeSans 560 0 0 0 vssa2
+port 567 nsew signal bidirectional
+flabel metal3 s 291170 95715 292400 98115 0 FreeSans 560 0 0 0 vssd1
+port 568 nsew signal bidirectional
+flabel metal3 s 291170 90715 292400 93115 0 FreeSans 560 0 0 0 vssd1
+port 569 nsew signal bidirectional
+flabel metal3 s 0 86444 830 88844 0 FreeSans 560 0 0 0 vssd2
+port 570 nsew signal bidirectional
+flabel metal3 s 0 81444 830 83844 0 FreeSans 560 0 0 0 vssd2
+port 571 nsew signal bidirectional
+flabel metal2 s 262 -400 318 240 0 FreeSans 560 90 0 0 wb_clk_i
+port 572 nsew signal input
+flabel metal2 s 853 -400 909 240 0 FreeSans 560 90 0 0 wb_rst_i
+port 573 nsew signal input
+flabel metal2 s 1444 -400 1500 240 0 FreeSans 560 90 0 0 wbs_ack_o
+port 574 nsew signal tristate
+flabel metal2 s 3808 -400 3864 240 0 FreeSans 560 90 0 0 wbs_adr_i[0]
+port 575 nsew signal input
+flabel metal2 s 23902 -400 23958 240 0 FreeSans 560 90 0 0 wbs_adr_i[10]
+port 576 nsew signal input
+flabel metal2 s 25675 -400 25731 240 0 FreeSans 560 90 0 0 wbs_adr_i[11]
+port 577 nsew signal input
+flabel metal2 s 27448 -400 27504 240 0 FreeSans 560 90 0 0 wbs_adr_i[12]
+port 578 nsew signal input
+flabel metal2 s 29221 -400 29277 240 0 FreeSans 560 90 0 0 wbs_adr_i[13]
+port 579 nsew signal input
+flabel metal2 s 30994 -400 31050 240 0 FreeSans 560 90 0 0 wbs_adr_i[14]
+port 580 nsew signal input
+flabel metal2 s 32767 -400 32823 240 0 FreeSans 560 90 0 0 wbs_adr_i[15]
+port 581 nsew signal input
+flabel metal2 s 34540 -400 34596 240 0 FreeSans 560 90 0 0 wbs_adr_i[16]
+port 582 nsew signal input
+flabel metal2 s 36313 -400 36369 240 0 FreeSans 560 90 0 0 wbs_adr_i[17]
+port 583 nsew signal input
+flabel metal2 s 38086 -400 38142 240 0 FreeSans 560 90 0 0 wbs_adr_i[18]
+port 584 nsew signal input
+flabel metal2 s 39859 -400 39915 240 0 FreeSans 560 90 0 0 wbs_adr_i[19]
+port 585 nsew signal input
+flabel metal2 s 6172 -400 6228 240 0 FreeSans 560 90 0 0 wbs_adr_i[1]
+port 586 nsew signal input
+flabel metal2 s 41632 -400 41688 240 0 FreeSans 560 90 0 0 wbs_adr_i[20]
+port 587 nsew signal input
+flabel metal2 s 43405 -400 43461 240 0 FreeSans 560 90 0 0 wbs_adr_i[21]
+port 588 nsew signal input
+flabel metal2 s 45178 -400 45234 240 0 FreeSans 560 90 0 0 wbs_adr_i[22]
+port 589 nsew signal input
+flabel metal2 s 46951 -400 47007 240 0 FreeSans 560 90 0 0 wbs_adr_i[23]
+port 590 nsew signal input
+flabel metal2 s 48724 -400 48780 240 0 FreeSans 560 90 0 0 wbs_adr_i[24]
+port 591 nsew signal input
+flabel metal2 s 50497 -400 50553 240 0 FreeSans 560 90 0 0 wbs_adr_i[25]
+port 592 nsew signal input
+flabel metal2 s 52270 -400 52326 240 0 FreeSans 560 90 0 0 wbs_adr_i[26]
+port 593 nsew signal input
+flabel metal2 s 54043 -400 54099 240 0 FreeSans 560 90 0 0 wbs_adr_i[27]
+port 594 nsew signal input
+flabel metal2 s 55816 -400 55872 240 0 FreeSans 560 90 0 0 wbs_adr_i[28]
+port 595 nsew signal input
+flabel metal2 s 57589 -400 57645 240 0 FreeSans 560 90 0 0 wbs_adr_i[29]
+port 596 nsew signal input
+flabel metal2 s 8536 -400 8592 240 0 FreeSans 560 90 0 0 wbs_adr_i[2]
+port 597 nsew signal input
+flabel metal2 s 59362 -400 59418 240 0 FreeSans 560 90 0 0 wbs_adr_i[30]
+port 598 nsew signal input
+flabel metal2 s 61135 -400 61191 240 0 FreeSans 560 90 0 0 wbs_adr_i[31]
+port 599 nsew signal input
+flabel metal2 s 10900 -400 10956 240 0 FreeSans 560 90 0 0 wbs_adr_i[3]
+port 600 nsew signal input
+flabel metal2 s 13264 -400 13320 240 0 FreeSans 560 90 0 0 wbs_adr_i[4]
+port 601 nsew signal input
+flabel metal2 s 15037 -400 15093 240 0 FreeSans 560 90 0 0 wbs_adr_i[5]
+port 602 nsew signal input
+flabel metal2 s 16810 -400 16866 240 0 FreeSans 560 90 0 0 wbs_adr_i[6]
+port 603 nsew signal input
+flabel metal2 s 18583 -400 18639 240 0 FreeSans 560 90 0 0 wbs_adr_i[7]
+port 604 nsew signal input
+flabel metal2 s 20356 -400 20412 240 0 FreeSans 560 90 0 0 wbs_adr_i[8]
+port 605 nsew signal input
+flabel metal2 s 22129 -400 22185 240 0 FreeSans 560 90 0 0 wbs_adr_i[9]
+port 606 nsew signal input
+flabel metal2 s 2035 -400 2091 240 0 FreeSans 560 90 0 0 wbs_cyc_i
+port 607 nsew signal input
+flabel metal2 s 4399 -400 4455 240 0 FreeSans 560 90 0 0 wbs_dat_i[0]
+port 608 nsew signal input
+flabel metal2 s 24493 -400 24549 240 0 FreeSans 560 90 0 0 wbs_dat_i[10]
+port 609 nsew signal input
+flabel metal2 s 26266 -400 26322 240 0 FreeSans 560 90 0 0 wbs_dat_i[11]
+port 610 nsew signal input
+flabel metal2 s 28039 -400 28095 240 0 FreeSans 560 90 0 0 wbs_dat_i[12]
+port 611 nsew signal input
+flabel metal2 s 29812 -400 29868 240 0 FreeSans 560 90 0 0 wbs_dat_i[13]
+port 612 nsew signal input
+flabel metal2 s 31585 -400 31641 240 0 FreeSans 560 90 0 0 wbs_dat_i[14]
+port 613 nsew signal input
+flabel metal2 s 33358 -400 33414 240 0 FreeSans 560 90 0 0 wbs_dat_i[15]
+port 614 nsew signal input
+flabel metal2 s 35131 -400 35187 240 0 FreeSans 560 90 0 0 wbs_dat_i[16]
+port 615 nsew signal input
+flabel metal2 s 36904 -400 36960 240 0 FreeSans 560 90 0 0 wbs_dat_i[17]
+port 616 nsew signal input
+flabel metal2 s 38677 -400 38733 240 0 FreeSans 560 90 0 0 wbs_dat_i[18]
+port 617 nsew signal input
+flabel metal2 s 40450 -400 40506 240 0 FreeSans 560 90 0 0 wbs_dat_i[19]
+port 618 nsew signal input
+flabel metal2 s 6763 -400 6819 240 0 FreeSans 560 90 0 0 wbs_dat_i[1]
+port 619 nsew signal input
+flabel metal2 s 42223 -400 42279 240 0 FreeSans 560 90 0 0 wbs_dat_i[20]
+port 620 nsew signal input
+flabel metal2 s 43996 -400 44052 240 0 FreeSans 560 90 0 0 wbs_dat_i[21]
+port 621 nsew signal input
+flabel metal2 s 45769 -400 45825 240 0 FreeSans 560 90 0 0 wbs_dat_i[22]
+port 622 nsew signal input
+flabel metal2 s 47542 -400 47598 240 0 FreeSans 560 90 0 0 wbs_dat_i[23]
+port 623 nsew signal input
+flabel metal2 s 49315 -400 49371 240 0 FreeSans 560 90 0 0 wbs_dat_i[24]
+port 624 nsew signal input
+flabel metal2 s 51088 -400 51144 240 0 FreeSans 560 90 0 0 wbs_dat_i[25]
+port 625 nsew signal input
+flabel metal2 s 52861 -400 52917 240 0 FreeSans 560 90 0 0 wbs_dat_i[26]
+port 626 nsew signal input
+flabel metal2 s 54634 -400 54690 240 0 FreeSans 560 90 0 0 wbs_dat_i[27]
+port 627 nsew signal input
+flabel metal2 s 56407 -400 56463 240 0 FreeSans 560 90 0 0 wbs_dat_i[28]
+port 628 nsew signal input
+flabel metal2 s 58180 -400 58236 240 0 FreeSans 560 90 0 0 wbs_dat_i[29]
+port 629 nsew signal input
+flabel metal2 s 9127 -400 9183 240 0 FreeSans 560 90 0 0 wbs_dat_i[2]
+port 630 nsew signal input
+flabel metal2 s 59953 -400 60009 240 0 FreeSans 560 90 0 0 wbs_dat_i[30]
+port 631 nsew signal input
+flabel metal2 s 61726 -400 61782 240 0 FreeSans 560 90 0 0 wbs_dat_i[31]
+port 632 nsew signal input
+flabel metal2 s 11491 -400 11547 240 0 FreeSans 560 90 0 0 wbs_dat_i[3]
+port 633 nsew signal input
+flabel metal2 s 13855 -400 13911 240 0 FreeSans 560 90 0 0 wbs_dat_i[4]
+port 634 nsew signal input
+flabel metal2 s 15628 -400 15684 240 0 FreeSans 560 90 0 0 wbs_dat_i[5]
+port 635 nsew signal input
+flabel metal2 s 17401 -400 17457 240 0 FreeSans 560 90 0 0 wbs_dat_i[6]
+port 636 nsew signal input
+flabel metal2 s 19174 -400 19230 240 0 FreeSans 560 90 0 0 wbs_dat_i[7]
+port 637 nsew signal input
+flabel metal2 s 20947 -400 21003 240 0 FreeSans 560 90 0 0 wbs_dat_i[8]
+port 638 nsew signal input
+flabel metal2 s 22720 -400 22776 240 0 FreeSans 560 90 0 0 wbs_dat_i[9]
+port 639 nsew signal input
+flabel metal2 s 4990 -400 5046 240 0 FreeSans 560 90 0 0 wbs_dat_o[0]
+port 640 nsew signal tristate
+flabel metal2 s 25084 -400 25140 240 0 FreeSans 560 90 0 0 wbs_dat_o[10]
+port 641 nsew signal tristate
+flabel metal2 s 26857 -400 26913 240 0 FreeSans 560 90 0 0 wbs_dat_o[11]
+port 642 nsew signal tristate
+flabel metal2 s 28630 -400 28686 240 0 FreeSans 560 90 0 0 wbs_dat_o[12]
+port 643 nsew signal tristate
+flabel metal2 s 30403 -400 30459 240 0 FreeSans 560 90 0 0 wbs_dat_o[13]
+port 644 nsew signal tristate
+flabel metal2 s 32176 -400 32232 240 0 FreeSans 560 90 0 0 wbs_dat_o[14]
+port 645 nsew signal tristate
+flabel metal2 s 33949 -400 34005 240 0 FreeSans 560 90 0 0 wbs_dat_o[15]
+port 646 nsew signal tristate
+flabel metal2 s 35722 -400 35778 240 0 FreeSans 560 90 0 0 wbs_dat_o[16]
+port 647 nsew signal tristate
+flabel metal2 s 37495 -400 37551 240 0 FreeSans 560 90 0 0 wbs_dat_o[17]
+port 648 nsew signal tristate
+flabel metal2 s 39268 -400 39324 240 0 FreeSans 560 90 0 0 wbs_dat_o[18]
+port 649 nsew signal tristate
+flabel metal2 s 41041 -400 41097 240 0 FreeSans 560 90 0 0 wbs_dat_o[19]
+port 650 nsew signal tristate
+flabel metal2 s 7354 -400 7410 240 0 FreeSans 560 90 0 0 wbs_dat_o[1]
+port 651 nsew signal tristate
+flabel metal2 s 42814 -400 42870 240 0 FreeSans 560 90 0 0 wbs_dat_o[20]
+port 652 nsew signal tristate
+flabel metal2 s 44587 -400 44643 240 0 FreeSans 560 90 0 0 wbs_dat_o[21]
+port 653 nsew signal tristate
+flabel metal2 s 46360 -400 46416 240 0 FreeSans 560 90 0 0 wbs_dat_o[22]
+port 654 nsew signal tristate
+flabel metal2 s 48133 -400 48189 240 0 FreeSans 560 90 0 0 wbs_dat_o[23]
+port 655 nsew signal tristate
+flabel metal2 s 49906 -400 49962 240 0 FreeSans 560 90 0 0 wbs_dat_o[24]
+port 656 nsew signal tristate
+flabel metal2 s 51679 -400 51735 240 0 FreeSans 560 90 0 0 wbs_dat_o[25]
+port 657 nsew signal tristate
+flabel metal2 s 53452 -400 53508 240 0 FreeSans 560 90 0 0 wbs_dat_o[26]
+port 658 nsew signal tristate
+flabel metal2 s 55225 -400 55281 240 0 FreeSans 560 90 0 0 wbs_dat_o[27]
+port 659 nsew signal tristate
+flabel metal2 s 56998 -400 57054 240 0 FreeSans 560 90 0 0 wbs_dat_o[28]
+port 660 nsew signal tristate
+flabel metal2 s 58771 -400 58827 240 0 FreeSans 560 90 0 0 wbs_dat_o[29]
+port 661 nsew signal tristate
+flabel metal2 s 9718 -400 9774 240 0 FreeSans 560 90 0 0 wbs_dat_o[2]
+port 662 nsew signal tristate
+flabel metal2 s 60544 -400 60600 240 0 FreeSans 560 90 0 0 wbs_dat_o[30]
+port 663 nsew signal tristate
+flabel metal2 s 62317 -400 62373 240 0 FreeSans 560 90 0 0 wbs_dat_o[31]
+port 664 nsew signal tristate
+flabel metal2 s 12082 -400 12138 240 0 FreeSans 560 90 0 0 wbs_dat_o[3]
+port 665 nsew signal tristate
+flabel metal2 s 14446 -400 14502 240 0 FreeSans 560 90 0 0 wbs_dat_o[4]
+port 666 nsew signal tristate
+flabel metal2 s 16219 -400 16275 240 0 FreeSans 560 90 0 0 wbs_dat_o[5]
+port 667 nsew signal tristate
+flabel metal2 s 17992 -400 18048 240 0 FreeSans 560 90 0 0 wbs_dat_o[6]
+port 668 nsew signal tristate
+flabel metal2 s 19765 -400 19821 240 0 FreeSans 560 90 0 0 wbs_dat_o[7]
+port 669 nsew signal tristate
+flabel metal2 s 21538 -400 21594 240 0 FreeSans 560 90 0 0 wbs_dat_o[8]
+port 670 nsew signal tristate
+flabel metal2 s 23311 -400 23367 240 0 FreeSans 560 90 0 0 wbs_dat_o[9]
+port 671 nsew signal tristate
+flabel metal2 s 5581 -400 5637 240 0 FreeSans 560 90 0 0 wbs_sel_i[0]
+port 672 nsew signal input
+flabel metal2 s 7945 -400 8001 240 0 FreeSans 560 90 0 0 wbs_sel_i[1]
+port 673 nsew signal input
+flabel metal2 s 10309 -400 10365 240 0 FreeSans 560 90 0 0 wbs_sel_i[2]
+port 674 nsew signal input
+flabel metal2 s 12673 -400 12729 240 0 FreeSans 560 90 0 0 wbs_sel_i[3]
+port 675 nsew signal input
+flabel metal2 s 2626 -400 2682 240 0 FreeSans 560 90 0 0 wbs_stb_i
+port 676 nsew signal input
+flabel metal2 s 3217 -400 3273 240 0 FreeSans 560 90 0 0 wbs_we_i
+port 677 nsew signal input
+<< properties >>
+string FIXED_BBOX 0 0 292000 352000
+<< end >>
diff --git a/netgen/comp.out b/netgen/comp.out
new file mode 100644
index 0000000..3c9d10a
--- /dev/null
+++ b/netgen/comp.out
@@ -0,0 +1,3349 @@
+Equate elements: no current cell.
+Equate elements: no current cell.
+Flattening unmatched subcell buffer_1#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5Z8B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_XJTKXQ in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell nmos_1u in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_7RYEVP in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell pmos_2uf2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell buffer_12 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell buffer_1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5Z8B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_XJTKXQ in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell nmos_1u in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_7RYEVP in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell pmos_2uf2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell buffer_2 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W8 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KZU588 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RL4NCG in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell inv_W16 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_VJWT33 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_3M44SC in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell compaartor_v4 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell preamp_part2 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RFM3CD in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_F5U58G#0 in circuit user_analog_project_wrapper (0)(3 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_XJTKXQ#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell SR_latch in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_F5U58G in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5E9B in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell preamp_part1 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_G6PLX8 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RFM3CD in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_F5U58G#1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_8FHE5N in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell latch_2 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W2#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_AC5Z8B#0 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_XJTKXQ#1 in circuit user_analog_project_wrapper (0)(2 instances)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_5SVZDE in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell buffer_2#0 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W8 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KZU588 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RL4NCG in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W16 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_VJWT33 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_3M44SC in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell buffer_2#1 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W8 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_KZU588 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_RL4NCG in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell inv_W16 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__nfet_01v8_VJWT33 in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell sky130_fd_pr__pfet_01v8_3M44SC in circuit user_analog_project_wrapper (0)(1 instance)
+Flattening unmatched subcell comparator_schv5 in circuit user_analog_project_wrapper (1)(1 instance)
+
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[11]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[12]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[13]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[14]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[15]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[16]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[17]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[18]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[19]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[1]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[20]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[21]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[22]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[23]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[24]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[25]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[26]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[2]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[3]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[4]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[5]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[6]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[7]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[8]
+Cell user_analog_project_wrapper (0) disconnected node: io_in[9]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[0]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[10]
+Cell user_analog_project_wrapper (0) disconnected node: io_in_3v3[11]
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+Cell user_analog_project_wrapper (1) disconnected node: la_data_out[10]
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+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[12]
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+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[5]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[4]
+Cell user_analog_project_wrapper (1) disconnected node: la_oenb[3]
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+Cell user_analog_project_wrapper (1) disconnected node: io_in_3v3[17]
+Cell user_analog_project_wrapper (1) disconnected node: io_in_3v3[16]
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+Cell user_analog_project_wrapper (1) disconnected node: io_in_3v3[14]
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+Cell user_analog_project_wrapper (1) disconnected node: io_in_3v3[8]
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+Cell user_analog_project_wrapper (1) disconnected node: io_out[22]
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+Cell user_analog_project_wrapper (1) disconnected node: io_out[8]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[7]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[6]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[5]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[4]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[3]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[2]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_out[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[26]
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+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[20]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[19]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[18]
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+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[8]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[7]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[6]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[5]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[4]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[3]
+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[2]
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+Cell user_analog_project_wrapper (1) disconnected node: io_oeb[0]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[9]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (1) disconnected node: user_clock2
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[0]
+Class user_analog_project_wrapper (0): Merged 313 parallel devices.
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[10]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[11]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[12]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[13]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[14]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[15]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[16]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[17]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[4]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[5]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[6]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[7]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[8]
+Cell user_analog_project_wrapper (0) disconnected node: gpio_analog[9]
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+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[3]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[17]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[16]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[15]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[14]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[13]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[12]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[11]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[10]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[9]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[8]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[7]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[6]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[5]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[4]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[3]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[2]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[1]
+Cell user_analog_project_wrapper (1) disconnected node: gpio_noesd[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[10]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[9]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[4]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[1]
+Cell user_analog_project_wrapper (1) disconnected node: io_analog[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_high[0]
+Cell user_analog_project_wrapper (1) disconnected node: io_clamp_low[0]
+Cell user_analog_project_wrapper (1) disconnected node: user_clock2
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[2]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[1]
+Cell user_analog_project_wrapper (1) disconnected node: user_irq[0]
+Subcircuit summary:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+sky130_fd_pr__pfet_01v8 (235->25) |sky130_fd_pr__pfet_01v8 (25)
+sky130_fd_pr__nfet_01v8 (133->30) |sky130_fd_pr__nfet_01v8 (30)
+vsrc (4) |vsrc (4)
+Number of devices: 59 |Number of devices: 59
+Number of nets: 37 |Number of nets: 37
+---------------------------------------------------------------------------------------
+Resolving automorphisms by property value.
+Resolving automorphisms by pin name.
+Netlists match uniquely.
+Circuits match correctly.
+
+Subcircuit pins:
+Circuit 1: user_analog_project_wrapper |Circuit 2: user_analog_project_wrapper
+-------------------------------------------|-------------------------------------------
+io_analog[5] |io_analog[5]
+io_analog[6] |io_analog[6]
+io_clamp_low[1] |io_clamp_low[1]
+io_clamp_low[2] |io_clamp_low[2]
+io_clamp_high[2] |io_clamp_high[2]
+io_clamp_high[1] |io_clamp_high[1]
+io_analog[3] |io_analog[3]
+io_analog[2] |io_analog[2]
+io_analog[7] |io_analog[7]
+io_analog[8] |io_analog[8]
+vssa1 |vssa1
+vccd1 |vccd1
+gpio_analog[0] |gpio_analog[0]
+gpio_analog[10] |gpio_analog[10]
+gpio_analog[11] |gpio_analog[11]
+gpio_analog[12] |gpio_analog[12]
+gpio_analog[13] |gpio_analog[13]
+gpio_analog[14] |gpio_analog[14]
+gpio_analog[15] |gpio_analog[15]
+gpio_analog[16] |gpio_analog[16]
+gpio_analog[17] |gpio_analog[17]
+gpio_analog[1] |gpio_analog[1]
+gpio_analog[2] |gpio_analog[2]
+gpio_analog[3] |gpio_analog[3]
+gpio_analog[4] |gpio_analog[4]
+gpio_analog[5] |gpio_analog[5]
+gpio_analog[6] |gpio_analog[6]
+gpio_analog[7] |gpio_analog[7]
+gpio_analog[8] |gpio_analog[8]
+gpio_analog[9] |gpio_analog[9]
+gpio_noesd[0] |gpio_noesd[0]
+gpio_noesd[10] |gpio_noesd[10]
+gpio_noesd[11] |gpio_noesd[11]
+gpio_noesd[12] |gpio_noesd[12]
+gpio_noesd[13] |gpio_noesd[13]
+gpio_noesd[14] |gpio_noesd[14]
+gpio_noesd[15] |gpio_noesd[15]
+gpio_noesd[16] |gpio_noesd[16]
+gpio_noesd[17] |gpio_noesd[17]
+gpio_noesd[1] |gpio_noesd[1]
+gpio_noesd[2] |gpio_noesd[2]
+gpio_noesd[3] |gpio_noesd[3]
+gpio_noesd[4] |gpio_noesd[4]
+gpio_noesd[5] |gpio_noesd[5]
+gpio_noesd[6] |gpio_noesd[6]
+gpio_noesd[7] |gpio_noesd[7]
+gpio_noesd[8] |gpio_noesd[8]
+gpio_noesd[9] |gpio_noesd[9]
+io_analog[0] |io_analog[0]
+io_analog[10] |io_analog[10]
+io_analog[1] |io_analog[1]
+io_analog[9] |io_analog[9]
+io_analog[4] |io_analog[4]
+io_clamp_high[0] |io_clamp_high[0]
+io_clamp_low[0] |io_clamp_low[0]
+io_in[0] |io_in[0]
+io_in[10] |io_in[10]
+io_in[11] |io_in[11]
+io_in[12] |io_in[12]
+io_in[13] |io_in[13]
+io_in[14] |io_in[14]
+io_in[15] |io_in[15]
+io_in[16] |io_in[16]
+io_in[17] |io_in[17]
+io_in[18] |io_in[18]
+io_in[19] |io_in[19]
+io_in[1] |io_in[1]
+io_in[20] |io_in[20]
+io_in[21] |io_in[21]
+io_in[22] |io_in[22]
+io_in[23] |io_in[23]
+io_in[24] |io_in[24]
+io_in[25] |io_in[25]
+io_in[26] |io_in[26]
+io_in[2] |io_in[2]
+io_in[3] |io_in[3]
+io_in[4] |io_in[4]
+io_in[5] |io_in[5]
+io_in[6] |io_in[6]
+io_in[7] |io_in[7]
+io_in[8] |io_in[8]
+io_in[9] |io_in[9]
+io_in_3v3[0] |io_in_3v3[0]
+io_in_3v3[10] |io_in_3v3[10]
+io_in_3v3[11] |io_in_3v3[11]
+io_in_3v3[12] |io_in_3v3[12]
+io_in_3v3[13] |io_in_3v3[13]
+io_in_3v3[14] |io_in_3v3[14]
+io_in_3v3[15] |io_in_3v3[15]
+io_in_3v3[16] |io_in_3v3[16]
+io_in_3v3[17] |io_in_3v3[17]
+io_in_3v3[18] |io_in_3v3[18]
+io_in_3v3[19] |io_in_3v3[19]
+io_in_3v3[1] |io_in_3v3[1]
+io_in_3v3[20] |io_in_3v3[20]
+io_in_3v3[21] |io_in_3v3[21]
+io_in_3v3[22] |io_in_3v3[22]
+io_in_3v3[23] |io_in_3v3[23]
+io_in_3v3[24] |io_in_3v3[24]
+io_in_3v3[25] |io_in_3v3[25]
+io_in_3v3[26] |io_in_3v3[26]
+io_in_3v3[2] |io_in_3v3[2]
+io_in_3v3[3] |io_in_3v3[3]
+io_in_3v3[4] |io_in_3v3[4]
+io_in_3v3[5] |io_in_3v3[5]
+io_in_3v3[6] |io_in_3v3[6]
+io_in_3v3[7] |io_in_3v3[7]
+io_in_3v3[8] |io_in_3v3[8]
+io_in_3v3[9] |io_in_3v3[9]
+io_oeb[0] |io_oeb[0]
+io_oeb[10] |io_oeb[10]
+io_oeb[11] |io_oeb[11]
+io_oeb[12] |io_oeb[12]
+io_oeb[13] |io_oeb[13]
+io_oeb[14] |io_oeb[14]
+io_oeb[15] |io_oeb[15]
+io_oeb[16] |io_oeb[16]
+io_oeb[17] |io_oeb[17]
+io_oeb[18] |io_oeb[18]
+io_oeb[19] |io_oeb[19]
+io_oeb[1] |io_oeb[1]
+io_oeb[20] |io_oeb[20]
+io_oeb[21] |io_oeb[21]
+io_oeb[22] |io_oeb[22]
+io_oeb[23] |io_oeb[23]
+io_oeb[24] |io_oeb[24]
+io_oeb[25] |io_oeb[25]
+io_oeb[26] |io_oeb[26]
+io_oeb[2] |io_oeb[2]
+io_oeb[3] |io_oeb[3]
+io_oeb[4] |io_oeb[4]
+io_oeb[5] |io_oeb[5]
+io_oeb[6] |io_oeb[6]
+io_oeb[7] |io_oeb[7]
+io_oeb[8] |io_oeb[8]
+io_oeb[9] |io_oeb[9]
+io_out[0] |io_out[0]
+io_out[10] |io_out[10]
+io_out[11] |io_out[11]
+io_out[12] |io_out[12]
+io_out[13] |io_out[13]
+io_out[14] |io_out[14]
+io_out[15] |io_out[15]
+io_out[16] |io_out[16]
+io_out[17] |io_out[17]
+io_out[18] |io_out[18]
+io_out[19] |io_out[19]
+io_out[1] |io_out[1]
+io_out[20] |io_out[20]
+io_out[21] |io_out[21]
+io_out[22] |io_out[22]
+io_out[23] |io_out[23]
+io_out[24] |io_out[24]
+io_out[25] |io_out[25]
+io_out[26] |io_out[26]
+io_out[2] |io_out[2]
+io_out[3] |io_out[3]
+io_out[4] |io_out[4]
+io_out[5] |io_out[5]
+io_out[6] |io_out[6]
+io_out[7] |io_out[7]
+io_out[8] |io_out[8]
+io_out[9] |io_out[9]
+la_data_in[0] |la_data_in[0]
+la_data_in[100] |la_data_in[100]
+la_data_in[101] |la_data_in[101]
+la_data_in[102] |la_data_in[102]
+la_data_in[103] |la_data_in[103]
+la_data_in[104] |la_data_in[104]
+la_data_in[105] |la_data_in[105]
+la_data_in[106] |la_data_in[106]
+la_data_in[107] |la_data_in[107]
+la_data_in[108] |la_data_in[108]
+la_data_in[109] |la_data_in[109]
+la_data_in[10] |la_data_in[10]
+la_data_in[110] |la_data_in[110]
+la_data_in[111] |la_data_in[111]
+la_data_in[112] |la_data_in[112]
+la_data_in[113] |la_data_in[113]
+la_data_in[114] |la_data_in[114]
+la_data_in[115] |la_data_in[115]
+la_data_in[116] |la_data_in[116]
+la_data_in[117] |la_data_in[117]
+la_data_in[118] |la_data_in[118]
+la_data_in[119] |la_data_in[119]
+la_data_in[11] |la_data_in[11]
+la_data_in[120] |la_data_in[120]
+la_data_in[121] |la_data_in[121]
+la_data_in[122] |la_data_in[122]
+la_data_in[123] |la_data_in[123]
+la_data_in[124] |la_data_in[124]
+la_data_in[125] |la_data_in[125]
+la_data_in[126] |la_data_in[126]
+la_data_in[127] |la_data_in[127]
+la_data_in[12] |la_data_in[12]
+la_data_in[13] |la_data_in[13]
+la_data_in[14] |la_data_in[14]
+la_data_in[15] |la_data_in[15]
+la_data_in[16] |la_data_in[16]
+la_data_in[17] |la_data_in[17]
+la_data_in[18] |la_data_in[18]
+la_data_in[19] |la_data_in[19]
+la_data_in[1] |la_data_in[1]
+la_data_in[20] |la_data_in[20]
+la_data_in[21] |la_data_in[21]
+la_data_in[22] |la_data_in[22]
+la_data_in[23] |la_data_in[23]
+la_data_in[24] |la_data_in[24]
+la_data_in[25] |la_data_in[25]
+la_data_in[26] |la_data_in[26]
+la_data_in[27] |la_data_in[27]
+la_data_in[28] |la_data_in[28]
+la_data_in[29] |la_data_in[29]
+la_data_in[2] |la_data_in[2]
+la_data_in[30] |la_data_in[30]
+la_data_in[31] |la_data_in[31]
+la_data_in[32] |la_data_in[32]
+la_data_in[33] |la_data_in[33]
+la_data_in[34] |la_data_in[34]
+la_data_in[35] |la_data_in[35]
+la_data_in[36] |la_data_in[36]
+la_data_in[37] |la_data_in[37]
+la_data_in[38] |la_data_in[38]
+la_data_in[39] |la_data_in[39]
+la_data_in[3] |la_data_in[3]
+la_data_in[40] |la_data_in[40]
+la_data_in[41] |la_data_in[41]
+la_data_in[42] |la_data_in[42]
+la_data_in[43] |la_data_in[43]
+la_data_in[44] |la_data_in[44]
+la_data_in[45] |la_data_in[45]
+la_data_in[46] |la_data_in[46]
+la_data_in[47] |la_data_in[47]
+la_data_in[48] |la_data_in[48]
+la_data_in[49] |la_data_in[49]
+la_data_in[4] |la_data_in[4]
+la_data_in[50] |la_data_in[50]
+la_data_in[51] |la_data_in[51]
+la_data_in[52] |la_data_in[52]
+la_data_in[53] |la_data_in[53]
+la_data_in[54] |la_data_in[54]
+la_data_in[55] |la_data_in[55]
+la_data_in[56] |la_data_in[56]
+la_data_in[57] |la_data_in[57]
+la_data_in[58] |la_data_in[58]
+la_data_in[59] |la_data_in[59]
+la_data_in[5] |la_data_in[5]
+la_data_in[60] |la_data_in[60]
+la_data_in[61] |la_data_in[61]
+la_data_in[62] |la_data_in[62]
+la_data_in[63] |la_data_in[63]
+la_data_in[64] |la_data_in[64]
+la_data_in[65] |la_data_in[65]
+la_data_in[66] |la_data_in[66]
+la_data_in[67] |la_data_in[67]
+la_data_in[68] |la_data_in[68]
+la_data_in[69] |la_data_in[69]
+la_data_in[6] |la_data_in[6]
+la_data_in[70] |la_data_in[70]
+la_data_in[71] |la_data_in[71]
+la_data_in[72] |la_data_in[72]
+la_data_in[73] |la_data_in[73]
+la_data_in[74] |la_data_in[74]
+la_data_in[75] |la_data_in[75]
+la_data_in[76] |la_data_in[76]
+la_data_in[77] |la_data_in[77]
+la_data_in[78] |la_data_in[78]
+la_data_in[79] |la_data_in[79]
+la_data_in[7] |la_data_in[7]
+la_data_in[80] |la_data_in[80]
+la_data_in[81] |la_data_in[81]
+la_data_in[82] |la_data_in[82]
+la_data_in[83] |la_data_in[83]
+la_data_in[84] |la_data_in[84]
+la_data_in[85] |la_data_in[85]
+la_data_in[86] |la_data_in[86]
+la_data_in[87] |la_data_in[87]
+la_data_in[88] |la_data_in[88]
+la_data_in[89] |la_data_in[89]
+la_data_in[8] |la_data_in[8]
+la_data_in[90] |la_data_in[90]
+la_data_in[91] |la_data_in[91]
+la_data_in[92] |la_data_in[92]
+la_data_in[93] |la_data_in[93]
+la_data_in[94] |la_data_in[94]
+la_data_in[95] |la_data_in[95]
+la_data_in[96] |la_data_in[96]
+la_data_in[97] |la_data_in[97]
+la_data_in[98] |la_data_in[98]
+la_data_in[99] |la_data_in[99]
+la_data_in[9] |la_data_in[9]
+la_data_out[0] |la_data_out[0]
+la_data_out[100] |la_data_out[100]
+la_data_out[101] |la_data_out[101]
+la_data_out[102] |la_data_out[102]
+la_data_out[103] |la_data_out[103]
+la_data_out[104] |la_data_out[104]
+la_data_out[105] |la_data_out[105]
+la_data_out[106] |la_data_out[106]
+la_data_out[107] |la_data_out[107]
+la_data_out[108] |la_data_out[108]
+la_data_out[109] |la_data_out[109]
+la_data_out[10] |la_data_out[10]
+la_data_out[110] |la_data_out[110]
+la_data_out[111] |la_data_out[111]
+la_data_out[112] |la_data_out[112]
+la_data_out[113] |la_data_out[113]
+la_data_out[114] |la_data_out[114]
+la_data_out[115] |la_data_out[115]
+la_data_out[116] |la_data_out[116]
+la_data_out[117] |la_data_out[117]
+la_data_out[118] |la_data_out[118]
+la_data_out[119] |la_data_out[119]
+la_data_out[11] |la_data_out[11]
+la_data_out[120] |la_data_out[120]
+la_data_out[121] |la_data_out[121]
+la_data_out[122] |la_data_out[122]
+la_data_out[123] |la_data_out[123]
+la_data_out[124] |la_data_out[124]
+la_data_out[125] |la_data_out[125]
+la_data_out[126] |la_data_out[126]
+la_data_out[127] |la_data_out[127]
+la_data_out[12] |la_data_out[12]
+la_data_out[13] |la_data_out[13]
+la_data_out[14] |la_data_out[14]
+la_data_out[15] |la_data_out[15]
+la_data_out[16] |la_data_out[16]
+la_data_out[17] |la_data_out[17]
+la_data_out[18] |la_data_out[18]
+la_data_out[19] |la_data_out[19]
+la_data_out[1] |la_data_out[1]
+la_data_out[20] |la_data_out[20]
+la_data_out[21] |la_data_out[21]
+la_data_out[22] |la_data_out[22]
+la_data_out[23] |la_data_out[23]
+la_data_out[24] |la_data_out[24]
+la_data_out[25] |la_data_out[25]
+la_data_out[26] |la_data_out[26]
+la_data_out[27] |la_data_out[27]
+la_data_out[28] |la_data_out[28]
+la_data_out[29] |la_data_out[29]
+la_data_out[2] |la_data_out[2]
+la_data_out[30] |la_data_out[30]
+la_data_out[31] |la_data_out[31]
+la_data_out[32] |la_data_out[32]
+la_data_out[33] |la_data_out[33]
+la_data_out[34] |la_data_out[34]
+la_data_out[35] |la_data_out[35]
+la_data_out[36] |la_data_out[36]
+la_data_out[37] |la_data_out[37]
+la_data_out[38] |la_data_out[38]
+la_data_out[39] |la_data_out[39]
+la_data_out[3] |la_data_out[3]
+la_data_out[40] |la_data_out[40]
+la_data_out[41] |la_data_out[41]
+la_data_out[42] |la_data_out[42]
+la_data_out[43] |la_data_out[43]
+la_data_out[44] |la_data_out[44]
+la_data_out[45] |la_data_out[45]
+la_data_out[46] |la_data_out[46]
+la_data_out[47] |la_data_out[47]
+la_data_out[48] |la_data_out[48]
+la_data_out[49] |la_data_out[49]
+la_data_out[4] |la_data_out[4]
+la_data_out[50] |la_data_out[50]
+la_data_out[51] |la_data_out[51]
+la_data_out[52] |la_data_out[52]
+la_data_out[53] |la_data_out[53]
+la_data_out[54] |la_data_out[54]
+la_data_out[55] |la_data_out[55]
+la_data_out[56] |la_data_out[56]
+la_data_out[57] |la_data_out[57]
+la_data_out[58] |la_data_out[58]
+la_data_out[59] |la_data_out[59]
+la_data_out[5] |la_data_out[5]
+la_data_out[60] |la_data_out[60]
+la_data_out[61] |la_data_out[61]
+la_data_out[62] |la_data_out[62]
+la_data_out[63] |la_data_out[63]
+la_data_out[64] |la_data_out[64]
+la_data_out[65] |la_data_out[65]
+la_data_out[66] |la_data_out[66]
+la_data_out[67] |la_data_out[67]
+la_data_out[68] |la_data_out[68]
+la_data_out[69] |la_data_out[69]
+la_data_out[6] |la_data_out[6]
+la_data_out[70] |la_data_out[70]
+la_data_out[71] |la_data_out[71]
+la_data_out[72] |la_data_out[72]
+la_data_out[73] |la_data_out[73]
+la_data_out[74] |la_data_out[74]
+la_data_out[75] |la_data_out[75]
+la_data_out[76] |la_data_out[76]
+la_data_out[77] |la_data_out[77]
+la_data_out[78] |la_data_out[78]
+la_data_out[79] |la_data_out[79]
+la_data_out[7] |la_data_out[7]
+la_data_out[80] |la_data_out[80]
+la_data_out[81] |la_data_out[81]
+la_data_out[82] |la_data_out[82]
+la_data_out[83] |la_data_out[83]
+la_data_out[84] |la_data_out[84]
+la_data_out[85] |la_data_out[85]
+la_data_out[86] |la_data_out[86]
+la_data_out[87] |la_data_out[87]
+la_data_out[88] |la_data_out[88]
+la_data_out[89] |la_data_out[89]
+la_data_out[8] |la_data_out[8]
+la_data_out[90] |la_data_out[90]
+la_data_out[91] |la_data_out[91]
+la_data_out[92] |la_data_out[92]
+la_data_out[93] |la_data_out[93]
+la_data_out[94] |la_data_out[94]
+la_data_out[95] |la_data_out[95]
+la_data_out[96] |la_data_out[96]
+la_data_out[97] |la_data_out[97]
+la_data_out[98] |la_data_out[98]
+la_data_out[99] |la_data_out[99]
+la_data_out[9] |la_data_out[9]
+la_oenb[0] |la_oenb[0]
+la_oenb[100] |la_oenb[100]
+la_oenb[101] |la_oenb[101]
+la_oenb[102] |la_oenb[102]
+la_oenb[103] |la_oenb[103]
+la_oenb[104] |la_oenb[104]
+la_oenb[105] |la_oenb[105]
+la_oenb[106] |la_oenb[106]
+la_oenb[107] |la_oenb[107]
+la_oenb[108] |la_oenb[108]
+la_oenb[109] |la_oenb[109]
+la_oenb[10] |la_oenb[10]
+la_oenb[110] |la_oenb[110]
+la_oenb[111] |la_oenb[111]
+la_oenb[112] |la_oenb[112]
+la_oenb[113] |la_oenb[113]
+la_oenb[114] |la_oenb[114]
+la_oenb[115] |la_oenb[115]
+la_oenb[116] |la_oenb[116]
+la_oenb[117] |la_oenb[117]
+la_oenb[118] |la_oenb[118]
+la_oenb[119] |la_oenb[119]
+la_oenb[11] |la_oenb[11]
+la_oenb[120] |la_oenb[120]
+la_oenb[121] |la_oenb[121]
+la_oenb[122] |la_oenb[122]
+la_oenb[123] |la_oenb[123]
+la_oenb[124] |la_oenb[124]
+la_oenb[125] |la_oenb[125]
+la_oenb[126] |la_oenb[126]
+la_oenb[127] |la_oenb[127]
+la_oenb[12] |la_oenb[12]
+la_oenb[13] |la_oenb[13]
+la_oenb[14] |la_oenb[14]
+la_oenb[15] |la_oenb[15]
+la_oenb[16] |la_oenb[16]
+la_oenb[17] |la_oenb[17]
+la_oenb[18] |la_oenb[18]
+la_oenb[19] |la_oenb[19]
+la_oenb[1] |la_oenb[1]
+la_oenb[20] |la_oenb[20]
+la_oenb[21] |la_oenb[21]
+la_oenb[22] |la_oenb[22]
+la_oenb[23] |la_oenb[23]
+la_oenb[24] |la_oenb[24]
+la_oenb[25] |la_oenb[25]
+la_oenb[26] |la_oenb[26]
+la_oenb[27] |la_oenb[27]
+la_oenb[28] |la_oenb[28]
+la_oenb[29] |la_oenb[29]
+la_oenb[2] |la_oenb[2]
+la_oenb[30] |la_oenb[30]
+la_oenb[31] |la_oenb[31]
+la_oenb[32] |la_oenb[32]
+la_oenb[33] |la_oenb[33]
+la_oenb[34] |la_oenb[34]
+la_oenb[35] |la_oenb[35]
+la_oenb[36] |la_oenb[36]
+la_oenb[37] |la_oenb[37]
+la_oenb[38] |la_oenb[38]
+la_oenb[39] |la_oenb[39]
+la_oenb[3] |la_oenb[3]
+la_oenb[40] |la_oenb[40]
+la_oenb[41] |la_oenb[41]
+la_oenb[42] |la_oenb[42]
+la_oenb[43] |la_oenb[43]
+la_oenb[44] |la_oenb[44]
+la_oenb[45] |la_oenb[45]
+la_oenb[46] |la_oenb[46]
+la_oenb[47] |la_oenb[47]
+la_oenb[48] |la_oenb[48]
+la_oenb[49] |la_oenb[49]
+la_oenb[4] |la_oenb[4]
+la_oenb[50] |la_oenb[50]
+la_oenb[51] |la_oenb[51]
+la_oenb[52] |la_oenb[52]
+la_oenb[53] |la_oenb[53]
+la_oenb[54] |la_oenb[54]
+la_oenb[55] |la_oenb[55]
+la_oenb[56] |la_oenb[56]
+la_oenb[57] |la_oenb[57]
+la_oenb[58] |la_oenb[58]
+la_oenb[59] |la_oenb[59]
+la_oenb[5] |la_oenb[5]
+la_oenb[60] |la_oenb[60]
+la_oenb[61] |la_oenb[61]
+la_oenb[62] |la_oenb[62]
+la_oenb[63] |la_oenb[63]
+la_oenb[64] |la_oenb[64]
+la_oenb[65] |la_oenb[65]
+la_oenb[66] |la_oenb[66]
+la_oenb[67] |la_oenb[67]
+la_oenb[68] |la_oenb[68]
+la_oenb[69] |la_oenb[69]
+la_oenb[6] |la_oenb[6]
+la_oenb[70] |la_oenb[70]
+la_oenb[71] |la_oenb[71]
+la_oenb[72] |la_oenb[72]
+la_oenb[73] |la_oenb[73]
+la_oenb[74] |la_oenb[74]
+la_oenb[75] |la_oenb[75]
+la_oenb[76] |la_oenb[76]
+la_oenb[77] |la_oenb[77]
+la_oenb[78] |la_oenb[78]
+la_oenb[79] |la_oenb[79]
+la_oenb[7] |la_oenb[7]
+la_oenb[80] |la_oenb[80]
+la_oenb[81] |la_oenb[81]
+la_oenb[82] |la_oenb[82]
+la_oenb[83] |la_oenb[83]
+la_oenb[84] |la_oenb[84]
+la_oenb[85] |la_oenb[85]
+la_oenb[86] |la_oenb[86]
+la_oenb[87] |la_oenb[87]
+la_oenb[88] |la_oenb[88]
+la_oenb[89] |la_oenb[89]
+la_oenb[8] |la_oenb[8]
+la_oenb[90] |la_oenb[90]
+la_oenb[91] |la_oenb[91]
+la_oenb[92] |la_oenb[92]
+la_oenb[93] |la_oenb[93]
+la_oenb[94] |la_oenb[94]
+la_oenb[95] |la_oenb[95]
+la_oenb[96] |la_oenb[96]
+la_oenb[97] |la_oenb[97]
+la_oenb[98] |la_oenb[98]
+la_oenb[99] |la_oenb[99]
+la_oenb[9] |la_oenb[9]
+user_clock2 |user_clock2
+user_irq[0] |user_irq[0]
+user_irq[1] |user_irq[1]
+user_irq[2] |user_irq[2]
+vccd2 |vccd2
+vdda1 |vdda1
+vdda2 |vdda2
+vssa2 |vssa2
+vssd1 |vssd1
+vssd2 |vssd2
+wb_clk_i |wb_clk_i
+wb_rst_i |wb_rst_i
+wbs_ack_o |wbs_ack_o
+wbs_adr_i[0] |wbs_adr_i[0]
+wbs_adr_i[10] |wbs_adr_i[10]
+wbs_adr_i[11] |wbs_adr_i[11]
+wbs_adr_i[12] |wbs_adr_i[12]
+wbs_adr_i[13] |wbs_adr_i[13]
+wbs_adr_i[14] |wbs_adr_i[14]
+wbs_adr_i[15] |wbs_adr_i[15]
+wbs_adr_i[16] |wbs_adr_i[16]
+wbs_adr_i[17] |wbs_adr_i[17]
+wbs_adr_i[18] |wbs_adr_i[18]
+wbs_adr_i[19] |wbs_adr_i[19]
+wbs_adr_i[1] |wbs_adr_i[1]
+wbs_adr_i[20] |wbs_adr_i[20]
+wbs_adr_i[21] |wbs_adr_i[21]
+wbs_adr_i[22] |wbs_adr_i[22]
+wbs_adr_i[23] |wbs_adr_i[23]
+wbs_adr_i[24] |wbs_adr_i[24]
+wbs_adr_i[25] |wbs_adr_i[25]
+wbs_adr_i[26] |wbs_adr_i[26]
+wbs_adr_i[27] |wbs_adr_i[27]
+wbs_adr_i[28] |wbs_adr_i[28]
+wbs_adr_i[29] |wbs_adr_i[29]
+wbs_adr_i[2] |wbs_adr_i[2]
+wbs_adr_i[30] |wbs_adr_i[30]
+wbs_adr_i[31] |wbs_adr_i[31]
+wbs_adr_i[3] |wbs_adr_i[3]
+wbs_adr_i[4] |wbs_adr_i[4]
+wbs_adr_i[5] |wbs_adr_i[5]
+wbs_adr_i[6] |wbs_adr_i[6]
+wbs_adr_i[7] |wbs_adr_i[7]
+wbs_adr_i[8] |wbs_adr_i[8]
+wbs_adr_i[9] |wbs_adr_i[9]
+wbs_cyc_i |wbs_cyc_i
+wbs_dat_i[0] |wbs_dat_i[0]
+wbs_dat_i[10] |wbs_dat_i[10]
+wbs_dat_i[11] |wbs_dat_i[11]
+wbs_dat_i[12] |wbs_dat_i[12]
+wbs_dat_i[13] |wbs_dat_i[13]
+wbs_dat_i[14] |wbs_dat_i[14]
+wbs_dat_i[15] |wbs_dat_i[15]
+wbs_dat_i[16] |wbs_dat_i[16]
+wbs_dat_i[17] |wbs_dat_i[17]
+wbs_dat_i[18] |wbs_dat_i[18]
+wbs_dat_i[19] |wbs_dat_i[19]
+wbs_dat_i[1] |wbs_dat_i[1]
+wbs_dat_i[20] |wbs_dat_i[20]
+wbs_dat_i[21] |wbs_dat_i[21]
+wbs_dat_i[22] |wbs_dat_i[22]
+wbs_dat_i[23] |wbs_dat_i[23]
+wbs_dat_i[24] |wbs_dat_i[24]
+wbs_dat_i[25] |wbs_dat_i[25]
+wbs_dat_i[26] |wbs_dat_i[26]
+wbs_dat_i[27] |wbs_dat_i[27]
+wbs_dat_i[28] |wbs_dat_i[28]
+wbs_dat_i[29] |wbs_dat_i[29]
+wbs_dat_i[2] |wbs_dat_i[2]
+wbs_dat_i[30] |wbs_dat_i[30]
+wbs_dat_i[31] |wbs_dat_i[31]
+wbs_dat_i[3] |wbs_dat_i[3]
+wbs_dat_i[4] |wbs_dat_i[4]
+wbs_dat_i[5] |wbs_dat_i[5]
+wbs_dat_i[6] |wbs_dat_i[6]
+wbs_dat_i[7] |wbs_dat_i[7]
+wbs_dat_i[8] |wbs_dat_i[8]
+wbs_dat_i[9] |wbs_dat_i[9]
+wbs_dat_o[0] |wbs_dat_o[0]
+wbs_dat_o[10] |wbs_dat_o[10]
+wbs_dat_o[11] |wbs_dat_o[11]
+wbs_dat_o[12] |wbs_dat_o[12]
+wbs_dat_o[13] |wbs_dat_o[13]
+wbs_dat_o[14] |wbs_dat_o[14]
+wbs_dat_o[15] |wbs_dat_o[15]
+wbs_dat_o[16] |wbs_dat_o[16]
+wbs_dat_o[17] |wbs_dat_o[17]
+wbs_dat_o[18] |wbs_dat_o[18]
+wbs_dat_o[19] |wbs_dat_o[19]
+wbs_dat_o[1] |wbs_dat_o[1]
+wbs_dat_o[20] |wbs_dat_o[20]
+wbs_dat_o[21] |wbs_dat_o[21]
+wbs_dat_o[22] |wbs_dat_o[22]
+wbs_dat_o[23] |wbs_dat_o[23]
+wbs_dat_o[24] |wbs_dat_o[24]
+wbs_dat_o[25] |wbs_dat_o[25]
+wbs_dat_o[26] |wbs_dat_o[26]
+wbs_dat_o[27] |wbs_dat_o[27]
+wbs_dat_o[28] |wbs_dat_o[28]
+wbs_dat_o[29] |wbs_dat_o[29]
+wbs_dat_o[2] |wbs_dat_o[2]
+wbs_dat_o[30] |wbs_dat_o[30]
+wbs_dat_o[31] |wbs_dat_o[31]
+wbs_dat_o[3] |wbs_dat_o[3]
+wbs_dat_o[4] |wbs_dat_o[4]
+wbs_dat_o[5] |wbs_dat_o[5]
+wbs_dat_o[6] |wbs_dat_o[6]
+wbs_dat_o[7] |wbs_dat_o[7]
+wbs_dat_o[8] |wbs_dat_o[8]
+wbs_dat_o[9] |wbs_dat_o[9]
+wbs_sel_i[0] |wbs_sel_i[0]
+wbs_sel_i[1] |wbs_sel_i[1]
+wbs_sel_i[2] |wbs_sel_i[2]
+wbs_sel_i[3] |wbs_sel_i[3]
+wbs_stb_i |wbs_stb_i
+wbs_we_i |wbs_we_i
+---------------------------------------------------------------------------------------
+Cell pin lists are equivalent.
+Device classes user_analog_project_wrapper and user_analog_project_wrapper are equivalent.
+Circuits match uniquely.
diff --git a/netgen/example_por.spice b/netgen/example_por.spice
new file mode 100644
index 0000000..d0cc93c
--- /dev/null
+++ b/netgen/example_por.spice
@@ -0,0 +1,681 @@
+* SPICE3 file created from user_analog_project_wrapper_1.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout VDD Vin GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1#0 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt buffer_1 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 w_n1601_n200# VSUBS 3.82fF
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+C0 a_82_816# VSUBS 2.90fF
+C1 w_82_814# VSUBS 3.92fF
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W8_0/li_354_902# VSUBS -3.18fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.10fF
+.ends
+
+.subckt buffer_12 buf_out buf_in VDD GND
+Xbuffer_1_0 VDD buffer_1_0/inv_W2_0/Vout buf_in GND buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+C0 VDD 0 3.98fF
+C1 GND 0 2.58fF
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B#0 a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#1 a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ#1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/Vin inv_W2_1/GND sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_0/Vin inv_W2_1/Vout VSUBS
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vin inv_W2_0/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vout inv_W2_1/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_1/VDD
++ inv_W2_1/VDD m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+**C0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# VSUBS 2.01fF
+.ends
+
+.subckt compaartor_v4 Outn Vp Vn CLK VDD GND Outp CLKBAR
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin Outn VDD VDD GND GND
++ SR_latch
+Xpreamp_part1_0 latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin m1_n58_544# CLK CLK
++ VDD Vn CLK m1_1202_1938# VDD Vp GND GND preamp_part1
+Xlatch_2_0 VDD latch_2_0/inv_W2_1/Vin GND VDD CLKBAR latch_2_0/inv_W2_0/Vin latch_2_0/inv_W2_0/Vin
++ GND latch_2
+**C0 latch_2_0/inv_W2_1/Vin GND 2.84fF
+**C1 latch_2_0/inv_W2_0/Vin GND 4.28fF
+**C2 CLK GND 17.54fF
+**C3 VDD GND 22.81fF
+**C4 m1_n58_544# GND 2.08fF
+.GLOBAL GND
+.GLOBAL VDD
+.ends
+
+.subckt buffer_2#0 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+C0 inv_W8_0/li_354_902# VSUBS -3.18fF
+C1 w_1666_500# VSUBS 6.52fF
+C2 inv_W8_0/li_354_0# VSUBS 2.10fF
+.ends
+
+.subckt user_analog_project_wrapper_1 gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_low[0] io_in[0] io_in[10] io_in[11]
++ io_in[12] io_in[13] io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19]
++ io_in[1] io_in[20] io_in[21] io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2]
++ io_in[3] io_in[4] io_in[5] io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10]
++ io_in_3v3[11] io_in_3v3[12] io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16]
++ io_in_3v3[17] io_in_3v3[18] io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21]
++ io_in_3v3[22] io_in_3v3[23] io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2]
++ io_in_3v3[3] io_in_3v3[4] io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9]
++ io_oeb[0] io_oeb[10] io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16]
++ io_oeb[17] io_oeb[18] io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23]
++ io_oeb[24] io_oeb[25] io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6]
++ io_oeb[7] io_oeb[8] io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13]
++ io_out[14] io_out[15] io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20]
++ io_out[21] io_out[22] io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3]
++ io_out[4] io_out[5] io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100]
++ la_data_in[101] la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105]
++ la_data_in[106] la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110]
++ la_data_in[111] la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115]
++ la_data_in[116] la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120]
++ la_data_in[121] la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125]
++ la_data_in[126] la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15]
++ la_data_in[16] la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20]
++ la_data_in[21] la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26]
++ la_data_in[27] la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31]
++ la_data_in[32] la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37]
++ la_data_in[38] la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42]
++ la_data_in[43] la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48]
++ la_data_in[49] la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53]
++ la_data_in[54] la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59]
++ la_data_in[5] la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64]
++ la_data_in[65] la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6]
++ la_data_in[70] la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75]
++ la_data_in[76] la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80]
++ la_data_in[81] la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86]
++ la_data_in[87] la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91]
++ la_data_in[92] la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97]
++ la_data_in[98] la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101]
++ la_data_out[102] la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106]
++ la_data_out[107] la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110]
++ la_data_out[111] la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115]
++ la_data_out[116] la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11]
++ la_data_out[120] la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124]
++ la_data_out[125] la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13]
++ la_data_out[14] la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18]
++ la_data_out[19] la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23]
++ la_data_out[24] la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28]
++ la_data_out[29] la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33]
++ la_data_out[34] la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38]
++ la_data_out[39] la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43]
++ la_data_out[44] la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48]
++ la_data_out[49] la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53]
++ la_data_out[54] la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58]
++ la_data_out[59] la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63]
++ la_data_out[64] la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68]
++ la_data_out[69] la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73]
++ la_data_out[74] la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78]
++ la_data_out[79] la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83]
++ la_data_out[84] la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88]
++ la_data_out[89] la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93]
++ la_data_out[94] la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98]
++ la_data_out[99] la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102]
++ la_oenb[103] la_oenb[104] la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109]
++ la_oenb[10] la_oenb[110] la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115]
++ la_oenb[116] la_oenb[117] la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121]
++ la_oenb[122] la_oenb[123] la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12]
++ la_oenb[13] la_oenb[14] la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19]
++ la_oenb[1] la_oenb[20] la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25]
++ la_oenb[26] la_oenb[27] la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31]
++ la_oenb[32] la_oenb[33] la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38]
++ la_oenb[39] la_oenb[3] la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44]
++ la_oenb[45] la_oenb[46] la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50]
++ la_oenb[51] la_oenb[52] la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57]
++ la_oenb[58] la_oenb[59] la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63]
++ la_oenb[64] la_oenb[65] la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6]
++ la_oenb[70] la_oenb[71] la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76]
++ la_oenb[77] la_oenb[78] la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82]
++ la_oenb[83] la_oenb[84] la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89]
++ la_oenb[8] la_oenb[90] la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95]
++ la_oenb[96] la_oenb[97] la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0]
++ user_irq[1] user_irq[2] vccd2 vdda1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o
++ wbs_adr_i[0] wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14]
++ wbs_adr_i[15] wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1]
++ wbs_adr_i[20] wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25]
++ wbs_adr_i[26] wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30]
++ wbs_adr_i[31] wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8]
++ wbs_adr_i[9] wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13]
++ wbs_dat_i[14] wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19]
++ wbs_dat_i[1] wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24]
++ wbs_dat_i[25] wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2]
++ wbs_dat_i[30] wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6]
++ wbs_dat_i[7] wbs_dat_i[8] wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11]
++ wbs_dat_o[12] wbs_dat_o[13] wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17]
++ wbs_dat_o[18] wbs_dat_o[19] wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22]
++ wbs_dat_o[23] wbs_dat_o[24] wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28]
++ wbs_dat_o[29] wbs_dat_o[2] wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4]
++ wbs_dat_o[5] wbs_dat_o[6] wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1]
++ wbs_sel_i[2] wbs_sel_i[3] wbs_stb_i wbs_we_i vccd1 vssa1
+Xbuffer_1_0 vccd1 buffer_1_0/inv_W2_0/Vout compaartor_v4_0/Outn vssa1 buffer_1#0
+Xbuffer_1_1 vccd1 buffer_1_1/inv_W2_0/Vout compaartor_v4_0/Outp vssa1 buffer_1#0
+Xbuffer_12_0 compaartor_v4_0/CLK io_analog[8] vccd1 vssa1 buffer_12
+Xcompaartor_v4_0 compaartor_v4_0/Outn io_analog[5] io_analog[6] compaartor_v4_0/CLK
++ vccd1 vssa1 compaartor_v4_0/Outp io_analog[2] compaartor_v4
+Xbuffer_2_0 io_analog[3] vccd1 vccd1 li_415416_685126# vssa1 vssa1 buffer_2#0
+X0 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=2.64e+12p pd=2.128e+07u as=4.18092e+13p ps=3.41925e+08u w=1e+06u l=150000u
+X1 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=5.9e+12p pd=4.78e+07u as=2.469e+13p ps=2.06315e+08u w=1e+06u l=150000u
+X2 vssa1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.32e+12p ps=1.064e+07u w=1e+06u l=150000u
+X3 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=1.056e+13p pd=8.5125e+07u as=0p ps=0u w=1e+06u l=150000u
+X4 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 vssa1 io_analog[2] a_406380_587752# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=1.32e+12p ps=1.064e+07u w=1e+06u l=150000u
+X6 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X8 vssa1 io_analog[2] a_406380_587752# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X10 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X11 io_analog[2] io_analog[2] vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X13 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X16 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X18 a_406380_587752# io_analog[2] vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X19 vssa1 io_analog[2] io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X20 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X22 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X24 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X25 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X26 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=2.64e+12p pd=2.128e+07u as=0p ps=0u w=1e+06u l=150000u
+X27 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X29 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X32 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X33 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X34 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X35 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X36 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X37 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X38 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X39 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X40 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X41 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X42 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X43 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X44 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X45 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X46 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X47 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X48 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X49 a_467110_687654# buffer_1_1/inv_W2_0/Vout vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X50 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X51 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X52 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X53 a_467110_687654# buffer_1_1/inv_W2_0/Vout vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X54 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X55 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X56 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X57 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X58 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X59 vccd1 io_analog[2] io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X60 vssa1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X61 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X62 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X63 vccd1 io_analog[2] io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X64 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X65 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X66 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X67 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X68 io_analog[2] io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X69 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X70 io_analog[2] io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X71 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X72 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X73 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X74 vssa1 io_analog[2] a_406380_587752# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X75 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X76 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X77 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X78 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X79 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X80 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X81 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X82 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X83 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X84 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X85 a_406380_587752# io_analog[2] vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X86 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X87 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X88 vccd1 io_analog[7] io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X89 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X90 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X91 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X92 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X93 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X94 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X95 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X96 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X97 vssa1 io_analog[2] a_406380_587752# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X98 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X99 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X100 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X101 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X102 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X103 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X104 vccd1 io_analog[2] a_406380_587752# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X105 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X106 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X107 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X108 vssa1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X109 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X110 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X111 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X112 a_467110_687654# buffer_1_1/inv_W2_0/Vout vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X113 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X114 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X115 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X116 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X117 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X118 a_467110_687654# buffer_1_1/inv_W2_0/Vout vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X119 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X120 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X121 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X122 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X123 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X124 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X125 vssa1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X126 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X127 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X128 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X129 io_analog[2] io_analog[7] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X130 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X131 io_analog[2] io_analog[7] vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X132 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X133 io_analog[2] a_467110_687654# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X134 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X135 a_467110_687654# buffer_1_1/inv_W2_0/Vout vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X136 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X137 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X138 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X139 io_analog[2] a_467110_687654# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X140 vssa1 a_406380_587752# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X141 vccd1 a_467110_687654# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X142 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X143 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X144 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X145 io_analog[2] a_406380_587752# vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X146 vssa1 a_467110_687654# io_analog[2] vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X147 a_406380_587752# io_analog[2] vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X148 io_analog[2] a_406380_587752# vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X149 vccd1 a_406380_587752# io_analog[2] vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X150 vccd1 buffer_1_1/inv_W2_0/Vout a_467110_687654# vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X151 a_406380_587752# io_analog[2] vssa1 vssa1 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X152 a_406380_587752# io_analog[2] vccd1 vccd1 sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+C0 io_analog[5] vccd1 43.13fF
+C1 m4_204098_586508# vccd1 119.00fF
+C2 io_analog[5] m4_204098_586508# 518.20fF
+C3 vccd1 buffer_1_1/inv_W2_0/Vout 2.02fF
+C4 a_406380_587752# vccd1 9.74fF
+C5 io_analog[3] vccd1 35.18fF
+C6 vccd1 m4_186716_584374# 104.50fF
+C7 io_analog[6] m4_186716_584374# 469.66fF
+C8 a_467110_687654# vccd1 9.63fF
+C9 compaartor_v4_0/CLK io_analog[2] 3.22fF
+C10 vccd1 io_analog[2] 66.00fF
+C11 io_analog[8] m4_186716_584374# 4.20fF
+C12 compaartor_v4_0/Outp vccd1 66.83fF
+C13 io_analog[5] io_analog[7] 75.56fF
+C14 m4_204098_586508# io_analog[7] 4.77fF
+C15 m3_417434_589490# vccd1 7.13fF
+C16 io_analog[5] io_analog[2] 4.99fF
+C17 compaartor_v4_0/CLK io_analog[6] 2.02fF
+C18 vccd1 io_analog[6] 40.88fF
+C19 compaartor_v4_0/Outn vccd1 67.00fF
+C20 io_analog[7] m4_186716_584374# 4.20fF
+C21 io_analog[4] vssa1 25.05fF
+C22 vssd2 vssa1 13.04fF
+C23 vssd1 vssa1 13.62fF
+C24 vdda2 vssa1 13.04fF
+C25 vdda1 vssa1 26.08fF
+C26 vssa2 vssa1 13.04fF
+C27 io_analog[0] vssa1 6.83fF
+C28 io_analog[1] vssa1 6.83fF
+C29 io_clamp_high[0] vssa1 3.58fF
+C30 io_clamp_low[0] vssa1 3.58fF
+C31 vccd2 vssa1 13.04fF
+C32 io_analog[10] vssa1 6.83fF
+C33 io_analog[9] vssa1 6.83fF
+C34 m4_204098_586508# vssa1 67.88fF **FLOATING
+C35 m4_186716_584374# vssa1 63.83fF **FLOATING
+C36 m3_417434_589490# vssa1 3.42fF **FLOATING
+C37 a_406380_587752# vssa1 4.07fF
+C38 io_analog[7] vssa1 362.68fF
+C39 a_467110_687654# vssa1 4.05fF
+C40 io_analog[3] vssa1 20.99fF
+C41 li_415416_685126# vssa1 109.41fF
+C42 io_analog[2] vssa1 37.40fF
+C43 compaartor_v4_0/latch_2_0/inv_W2_1/Vin vssa1 2.76fF
+C44 compaartor_v4_0/latch_2_0/inv_W2_0/Vin vssa1 3.67fF
+C45 compaartor_v4_0/m1_n58_544# vssa1 2.02fF
+C46 io_analog[5] vssa1 319.46fF
+C47 io_analog[6] vssa1 338.49fF
+C48 compaartor_v4_0/Outp vssa1 111.06fF
+C49 compaartor_v4_0/Outn vssa1 104.23fF
+C50 compaartor_v4_0/CLK vssa1 17.42fF
+C51 vccd1 vssa1 1924.67fF
+C52 io_analog[8] vssa1 383.53fF
+C53 buffer_1_1/inv_W2_0/Vout vssa1 103.94fF
+.ends
+
diff --git a/netgen/run_lvs_por.sh b/netgen/run_lvs_por.sh
new file mode 100755
index 0000000..7f45836
--- /dev/null
+++ b/netgen/run_lvs_por.sh
@@ -0,0 +1,24 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the example_por layout
+#
+# NOTE: By specifying the testbench for the schematic-side netlist, the proper
+# includes used by the testbench simulation are picked up. Otherwise, the LVS
+# itself compares just the simple_por subcircuit from the testbench.
+#--------------------------------------------------------------------------------
+netgen -batch lvs "example_por.spice compaartor_v4" "../xschem/comparator_lvs.spice comparator_lvs" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_verilog.sh b/netgen/run_lvs_wrapper_verilog.sh
new file mode 100755
index 0000000..f093ac3
--- /dev/null
+++ b/netgen/run_lvs_wrapper_verilog.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level verilog module.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_project_wrapper.v user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/run_lvs_wrapper_xschem.sh b/netgen/run_lvs_wrapper_xschem.sh
new file mode 100755
index 0000000..c741050
--- /dev/null
+++ b/netgen/run_lvs_wrapper_xschem.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level xschem subcircuit from the wrapper testbench.
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../xschem/analog_wrapper_tb.spice user_analog_project_wrapper" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..2a76767
--- /dev/null
+++ b/netgen/user_analog_project_wrapper.spice
@@ -0,0 +1,481 @@
+* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130A
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_7RYEVP a_n73_n69# a_n33_n157# a_15_n69# VSUBS
+X0 a_15_n69# a_n33_n157# a_n73_n69# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt nmos_1u sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69#
++ m1_n86_2#
+Xsky130_fd_pr__nfet_01v8_7RYEVP_0 sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS m1_n86_2#
++ sky130_fd_pr__nfet_01v8_7RYEVP_0/a_15_n69# sky130_fd_pr__nfet_01v8_7RYEVP_0/VSUBS
++ sky130_fd_pr__nfet_01v8_7RYEVP
+.ends
+
+.subckt pmos_2uf2 a_63_n100# a_33_n130# w_n317_n202# a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n130# a_n33_n100# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# w_n317_n202# w_n317_n202# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.8e+11p ps=2.76e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W1 Vout VDD Vin GND
+Xnmos_1u_0 GND Vout Vin nmos_1u
+Xpmos_2uf2_0 VDD Vin VDD Vout Vin GND pmos_2uf2
+.ends
+
+.subckt buffer_1#0 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt buffer_1 inv_W2_0/VDD inv_W2_0/Vout inv_W1_0/Vin inv_W2_0/Vin VSUBS
+Xinv_W2_0 inv_W2_0/VDD inv_W2_0/Vout inv_W2_0/Vin inv_W2_0/VDD VSUBS VSUBS inv_W2
+Xinv_W1_0 inv_W2_0/Vin inv_W2_0/VDD inv_W1_0/Vin VSUBS inv_W1
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_KZU588 a_159_n100# a_255_n100# a_351_n100# a_n129_n100#
++ a_63_n100# li_321_116# a_n353_n162# a_n225_n100# a_n413_n74# a_n321_n100# a_n33_n100#
++ VSUBS
+X0 a_n321_n100# a_n353_n162# a_n413_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_n225_n100# a_n353_n162# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n129_n100# a_n353_n162# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_63_n100# a_n353_n162# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_n33_n100# a_n353_n162# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_351_n100# a_n353_n162# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X6 a_159_n100# a_n353_n162# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_255_n100# a_n353_n162# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RL4NCG a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128# a_n255_n126# a_351_n100# a_n417_n100#
++ a_33_n128# a_n129_n100# a_n513_n100# a_n351_n128# a_63_n100# w_n833_n200# a_n225_n100#
++ a_609_n128# a_n63_n126# a_n797_n74# a_705_n126# a_n321_n100# a_639_n100# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_447_n100# a_n735_n128#
++ a_n447_n126# a_225_n128# VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n126# a_n129_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_255_n100# a_225_n128# a_159_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X3 a_351_n100# a_321_n126# a_255_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X4 a_543_n100# a_513_n126# a_447_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X5 a_159_n100# a_129_n126# a_63_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_447_n100# a_417_n128# a_351_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X7 a_639_n100# a_609_n128# a_543_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_735_n100# a_705_n126# a_639_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X9 a_n513_n100# a_n543_n128# a_n609_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_n321_n100# a_n351_n128# a_n417_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X11 a_n225_n100# a_n255_n126# a_n321_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X12 a_n705_n100# a_n735_n128# a_n797_n74# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X13 a_n609_n100# a_n639_n126# a_n705_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_n417_n100# a_n447_n126# a_n513_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_n129_n100# a_n159_n128# a_n225_n100# w_n833_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W8 li_354_902# w_354_500# li_354_0# li_512_546# a_804_430# VSUBS
+Xsky130_fd_pr__nfet_01v8_KZU588_0 li_354_0# li_512_546# li_354_0# li_512_546# li_512_546#
++ li_512_546# a_804_430# li_354_0# li_354_0# li_512_546# li_354_0# VSUBS sky130_fd_pr__nfet_01v8_KZU588
+Xsky130_fd_pr__pfet_01v8_RL4NCG_0 li_354_902# li_354_902# li_354_902# a_804_430# li_512_546#
++ li_512_546# a_804_430# a_804_430# a_804_430# li_354_902# li_354_902# a_804_430#
++ li_512_546# li_512_546# a_804_430# li_512_546# w_354_500# li_354_902# a_804_430#
++ a_804_430# li_354_902# a_804_430# li_512_546# li_512_546# a_804_430# a_804_430#
++ li_354_902# li_354_902# a_804_430# a_804_430# li_512_546# a_804_430# a_804_430#
++ a_804_430# VSUBS sky130_fd_pr__pfet_01v8_RL4NCG
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_VJWT33 a_543_n100# a_159_n100# a_n609_n100# a_n705_n100#
++ a_255_n100# a_351_n100# a_n417_n100# a_n129_n100# a_n513_n100# a_63_n100# a_n225_n100#
++ a_n797_n74# a_n735_n176# a_n321_n100# a_639_n100# a_735_n100# a_n33_n100# a_447_n100#
++ VSUBS
+X0 a_n513_n100# a_n735_n176# a_n609_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n321_n100# a_n735_n176# a_n417_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n225_n100# a_n735_n176# a_n321_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n705_n100# a_n735_n176# a_n797_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X4 a_n609_n100# a_n735_n176# a_n705_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X5 a_n417_n100# a_n735_n176# a_n513_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_n129_n100# a_n735_n176# a_n225_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_63_n100# a_n735_n176# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X8 a_n33_n100# a_n735_n176# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X9 a_351_n100# a_n735_n176# a_255_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_159_n100# a_n735_n176# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_255_n100# a_n735_n176# a_159_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X12 a_447_n100# a_n735_n176# a_351_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X13 a_543_n100# a_n735_n176# a_447_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X14 a_639_n100# a_n735_n176# a_543_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X15 a_735_n100# a_n735_n176# a_639_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_3M44SC a_543_n100# a_159_n100# a_n609_n100# a_321_n126#
++ a_1473_n126# a_1089_n126# a_n1407_n126# a_n705_n100# a_255_n100# a_n159_n128# a_n543_n128#
++ a_1407_n100# a_1185_n128# a_n255_n126# a_351_n100# a_n417_n100# a_n801_n100# a_n1119_n128#
++ a_n1503_n128# a_1281_n126# a_897_n126# a_33_n128# w_n1601_n200# a_1503_n100# a_1119_n100#
++ a_n1377_n100# a_n1215_n126# a_n129_n100# a_n513_n100# a_n351_n128# a_n1565_n74#
++ a_1215_n100# a_63_n100# a_n1089_n100# a_n1473_n100# a_993_n128# a_n225_n100# a_609_n128#
++ a_n63_n126# a_n1311_n128# a_1311_n100# a_927_n100# a_n1185_n100# a_705_n126# a_n1023_n126#
++ a_n321_n100# a_1023_n100# a_639_n100# a_n1281_n100# a_n927_n128# a_801_n128# a_417_n128#
++ a_n639_n126# a_735_n100# a_n33_n100# a_513_n126# a_129_n126# a_n897_n100# a_831_n100#
++ a_447_n100# a_n735_n128# a_n993_n100# a_n447_n126# a_n831_n126# a_1377_n128# a_225_n128#
++ VSUBS
+X0 a_63_n100# a_33_n128# a_n33_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_927_n100# a_897_n126# a_831_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_1023_n100# a_993_n128# a_927_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_1311_n100# a_1281_n126# a_1215_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X4 a_1119_n100# a_1089_n126# a_1023_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X5 a_1215_n100# a_1185_n128# a_1119_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X6 a_1407_n100# a_1377_n128# a_1311_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X7 a_1503_n100# a_1473_n126# a_1407_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X8 a_n33_n100# a_n63_n126# a_n129_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X9 a_255_n100# a_225_n128# a_159_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X10 a_351_n100# a_321_n126# a_255_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X11 a_543_n100# a_513_n126# a_447_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X12 a_831_n100# a_801_n128# a_735_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X13 a_159_n100# a_129_n126# a_63_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X14 a_447_n100# a_417_n128# a_351_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X15 a_639_n100# a_609_n128# a_543_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X16 a_735_n100# a_705_n126# a_639_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X17 a_n1281_n100# a_n1311_n128# a_n1377_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X18 a_n993_n100# a_n1023_n126# a_n1089_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X19 a_n1473_n100# a_n1503_n128# a_n1565_n74# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X20 a_n1377_n100# a_n1407_n126# a_n1473_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X21 a_n1185_n100# a_n1215_n126# a_n1281_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X22 a_n1089_n100# a_n1119_n128# a_n1185_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X23 a_n801_n100# a_n831_n126# a_n897_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X24 a_n513_n100# a_n543_n128# a_n609_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X25 a_n321_n100# a_n351_n128# a_n417_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X26 a_n225_n100# a_n255_n126# a_n321_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X27 a_n897_n100# a_n927_n128# a_n993_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X28 a_n705_n100# a_n735_n128# a_n801_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=0p ps=0u w=1e+06u l=150000u
+X29 a_n609_n100# a_n639_n126# a_n705_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X30 a_n417_n100# a_n447_n126# a_n513_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X31 a_n129_n100# a_n159_n128# a_n225_n100# w_n1601_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+
+.ends
+
+.subckt inv_W16 li_128_546# li_n14_902# a_82_816# w_82_814# li_n14_0# VSUBS
+Xsky130_fd_pr__nfet_01v8_VJWT33_0 li_n14_0# li_n14_0# li_n14_0# li_128_546# li_128_546#
++ li_n14_0# li_n14_0# li_128_546# li_128_546# li_128_546# li_n14_0# li_n14_0# a_82_816#
++ li_128_546# li_128_546# li_n14_0# li_n14_0# li_128_546# VSUBS sky130_fd_pr__nfet_01v8_VJWT33
+Xsky130_fd_pr__pfet_01v8_3M44SC_0 li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816#
++ a_82_816# a_82_816# li_128_546# li_128_546# a_82_816# a_82_816# li_128_546# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816#
++ a_82_816# w_82_814# li_n14_902# li_n14_902# li_n14_902# a_82_816# li_128_546# li_128_546#
++ a_82_816# li_n14_902# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816#
++ li_n14_902# a_82_816# a_82_816# a_82_816# li_n14_902# li_n14_902# li_n14_902# a_82_816#
++ a_82_816# li_128_546# li_128_546# li_128_546# li_128_546# a_82_816# a_82_816# a_82_816#
++ a_82_816# li_n14_902# li_n14_902# a_82_816# a_82_816# li_128_546# li_128_546# li_128_546#
++ a_82_816# li_n14_902# a_82_816# a_82_816# a_82_816# a_82_816# VSUBS sky130_fd_pr__pfet_01v8_3M44SC
+
+.ends
+
+.subckt buffer_2 Vout inv_W8_0/li_354_902# w_1666_500# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt buffer_12 buffer_1_0/inv_W2_0/Vout buf_in buffer_1_0/inv_W2_0/Vin VDD buf_out
++ GND
+Xbuffer_1_0 VDD buffer_1_0/inv_W2_0/Vout buf_in buffer_1_0/inv_W2_0/Vin GND buffer_1
+Xbuffer_2_0 buf_out VDD VDD buffer_1_0/inv_W2_0/Vout GND GND buffer_2
+
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_RFM3CD a_n73_n100# w_n109_n162# a_15_n100# a_n15_n126#
++ VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# w_n109_n162# sky130_fd_pr__pfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#0 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#0 a_n63_n152# a_63_n100# a_n125_n74# a_n33_n100#
++ VSUBS
+X0 a_63_n100# a_n63_n152# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n152# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt preamp_part2 a_148_644# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126# a_380_480#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126#
++ sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# a_1170_652# sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ VDD GND a_792_2# VSUBS
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD sky130_fd_pr__pfet_01v8_RFM3CD_0/w_n109_n162#
++ li_210_488# sky130_fd_pr__pfet_01v8_RFM3CD_0/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 li_928_394# sky130_fd_pr__pfet_01v8_RFM3CD_1/w_n109_n162#
++ VDD sky130_fd_pr__pfet_01v8_RFM3CD_1/a_n15_n126# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 m1_322_206# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 a_792_2# li_210_488# a_148_644# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_F5U58G_2 li_928_394# a_380_480# a_1170_652# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 a_380_480# m1_322_206# m1_322_206# li_210_488# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_1 a_792_2# m1_322_206# m1_322_206# li_928_394# VSUBS
++ sky130_fd_pr__nfet_01v8_XJTKXQ#0
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5E9B w_n161_n200# a_33_n126# a_63_n100# a_n125_n74#
++ a_n33_n100# a_n63_n130# VSUBS
+X0 a_63_n100# a_33_n126# a_n33_n100# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n130# a_n125_n74# w_n161_n200# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt SR_latch a_648_848# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126# sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ a_262_508# VDD w_0_524# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 a_648_848# GND sky130_fd_pr__nfet_01v8_F5U58G_0/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND a_262_508# sky130_fd_pr__nfet_01v8_F5U58G_1/a_n15_n126#
++ VSUBS sky130_fd_pr__nfet_01v8_F5U58G
+Xsky130_fd_pr__pfet_01v8_AC5E9B_0 w_0_524# a_262_508# VDD VDD a_648_848# a_262_508#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+Xsky130_fd_pr__pfet_01v8_AC5E9B_1 w_0_524# a_648_848# VDD VDD a_262_508# a_648_848#
++ VSUBS sky130_fd_pr__pfet_01v8_AC5E9B
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_G6PLX8 a_159_n100# a_n221_n74# a_n129_n100# a_63_n100#
++ a_n33_n100# a_n159_n122# VSUBS
+X0 a_n129_n100# a_n159_n122# a_n221_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+X1 a_63_n100# a_n159_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X2 a_n33_n100# a_n159_n122# a_n129_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X3 a_159_n100# a_n159_n122# a_63_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_F5U58G#1 a_n73_n100# a_15_n100# a_n15_n126# VSUBS
+X0 a_15_n100# a_n15_n126# a_n73_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=2.9e+11p pd=2.58e+06u as=2.9e+11p ps=2.58e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_8FHE5N a_n33_n50# a_63_n50# a_n63_n76# a_33_n76# a_n125_n39#
++ VSUBS
+X0 a_n33_n50# a_n63_n76# a_n125_n39# VSUBS sky130_fd_pr__nfet_01v8 ad=1.65e+11p pd=1.66e+06u as=1.528e+11p ps=1.62e+06u w=500000u l=150000u
+X1 a_63_n50# a_33_n76# a_n33_n50# VSUBS sky130_fd_pr__nfet_01v8 ad=1.528e+11p pd=1.62e+06u as=0p ps=0u w=500000u l=150000u
+.ends
+
+.subckt preamp_part1 li_954_42# li_n718_44# a_n656_268# a_80_n258# a_n302_940# w_n720_482#
++ a_n434_n260# a_506_940# a_864_270# VDD a_388_n260# GND VSUBS
+Xsky130_fd_pr__nfet_01v8_G6PLX8_0 li_n484_188# li_n484_188# a_n656_268# a_n656_268#
++ li_n484_188# a_n434_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__nfet_01v8_G6PLX8_1 li_n484_188# li_n484_188# a_864_270# a_864_270#
++ li_n484_188# a_388_n260# VSUBS sky130_fd_pr__nfet_01v8_G6PLX8
+Xsky130_fd_pr__pfet_01v8_RFM3CD_0 VDD w_n720_482# a_n656_268# a_n302_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__pfet_01v8_RFM3CD_1 a_864_270# w_n720_482# VDD a_506_940# VSUBS sky130_fd_pr__pfet_01v8_RFM3CD
+Xsky130_fd_pr__nfet_01v8_F5U58G_0 li_n718_44# GND a_n656_268# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_F5U58G_1 GND li_954_42# a_864_270# VSUBS sky130_fd_pr__nfet_01v8_F5U58G#1
+Xsky130_fd_pr__nfet_01v8_8FHE5N_0 li_n484_188# GND a_80_n258# a_80_n258# GND VSUBS
++ sky130_fd_pr__nfet_01v8_8FHE5N
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_AC5Z8B#0 a_159_n100# li_217_n290# li_n261_n290# li_229_174#
++ a_n221_n74# a_n129_n100# a_n159_n152# li_225_n726# a_n33_n100# w_n261_n210# li_n261_174#
++ li_n261_n726# VSUBS
+X0 a_n129_n100# a_n159_n152# a_n33_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=6.6e+11p pd=5.32e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=0p ps=0u w=1e+06u l=150000u
+X2 a_159_n100# a_n159_n152# a_n129_n100# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=3.048e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X3 a_n129_n100# a_n159_n152# a_n221_n74# w_n261_n210# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt sky130_fd_pr__nfet_01v8_XJTKXQ#1 a_33_n122# a_n63_n122# a_63_n100# a_n125_n74#
++ a_n33_n100# VSUBS
+X0 a_63_n100# a_33_n122# a_n33_n100# VSUBS sky130_fd_pr__nfet_01v8 ad=3.048e+11p pd=2.62e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_n33_n100# a_n63_n122# a_n125_n74# VSUBS sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=3.048e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt inv_W2#0 sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210# Vout Vin VDD GND VSUBS
+Xsky130_fd_pr__pfet_01v8_AC5Z8B_0 VDD Vout Vin VDD VDD Vout Vin GND VDD sky130_fd_pr__pfet_01v8_AC5Z8B_0/w_n261_n210#
++ VDD GND VSUBS sky130_fd_pr__pfet_01v8_AC5Z8B#0
+Xsky130_fd_pr__nfet_01v8_XJTKXQ_0 Vin Vin GND GND Vout VSUBS sky130_fd_pr__nfet_01v8_XJTKXQ#1
+.ends
+
+.subckt sky130_fd_pr__pfet_01v8_5SVZDE a_n111_n158# a_n173_n100# a_15_n100# a_111_n100#
++ a_n81_n100# w_n789_n196# VSUBS
+X0 a_15_n100# a_n111_n158# a_n81_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.3e+11p pd=2.66e+06u as=3.3e+11p ps=2.66e+06u w=1e+06u l=150000u
+X1 a_111_n100# a_n111_n158# a_15_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=3.1e+11p pd=2.62e+06u as=0p ps=0u w=1e+06u l=150000u
+X2 a_n81_n100# a_n111_n158# a_n173_n100# w_n789_n196# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=3.1e+11p ps=2.62e+06u w=1e+06u l=150000u
+.ends
+
+.subckt latch_2 m1_718_782# inv_W2_1/Vin inv_W2_1/GND sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_0/Vin inv_W2_1/Vout VSUBS
+Xinv_W2_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vin inv_W2_0/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xinv_W2_1 sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196# inv_W2_1/Vout inv_W2_1/Vin
++ inv_W2_1/VDD inv_W2_1/GND VSUBS inv_W2#0
+Xsky130_fd_pr__pfet_01v8_5SVZDE_0 sky130_fd_pr__pfet_01v8_5SVZDE_0/a_n111_n158# inv_W2_1/VDD
++ inv_W2_1/VDD m1_718_782# m1_718_782# sky130_fd_pr__pfet_01v8_5SVZDE_0/w_n789_n196#
++ VSUBS sky130_fd_pr__pfet_01v8_5SVZDE
+
+.ends
+
+.subckt compaartor_v4 Outn Vp Vn CLK VDD GND Outp CLKBAR
+Xpreamp_part2_0 CLK CLK m1_1202_1938# VDD CLK CLK CLK VDD VDD GND m1_n58_544# GND
++ preamp_part2
+XSR_latch_0 Outp latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin Outn VDD VDD GND GND
++ SR_latch
+Xpreamp_part1_0 latch_2_0/inv_W2_1/Vin latch_2_0/inv_W2_0/Vin m1_n58_544# CLK CLK
++ VDD Vn CLK m1_1202_1938# VDD Vp GND GND preamp_part1
+Xlatch_2_0 VDD latch_2_0/inv_W2_1/Vin GND VDD CLKBAR latch_2_0/inv_W2_0/Vin latch_2_0/inv_W2_0/Vin
++ GND latch_2
+
+.ends
+
+.subckt buffer_2#0 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt buffer_2#1 Vout w_1666_500# inv_W8_0/li_354_902# inv_W8_0/a_804_430# inv_W8_0/li_354_0#
++ VSUBS
+Xinv_W8_0 inv_W8_0/li_354_902# w_1666_500# inv_W8_0/li_354_0# inv_W16_0/a_82_816#
++ inv_W8_0/a_804_430# VSUBS inv_W8
+Xinv_W16_0 Vout inv_W8_0/li_354_902# inv_W16_0/a_82_816# w_1666_500# inv_W8_0/li_354_0#
++ VSUBS inv_W16
+
+.ends
+
+.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
++ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
++ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
++ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
++ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
++ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
++ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
++ io_analog[1] io_analog[2] io_analog[3] io_analog[5] io_analog[6] io_analog[7] io_analog[8]
++ io_analog[9] io_analog[4] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
++ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
++ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
++ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
++ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
++ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
++ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
++ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
++ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
++ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
++ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
++ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
++ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
++ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
++ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
++ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
++ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
++ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
++ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
++ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
++ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
++ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
++ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
++ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
++ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
++ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
++ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
++ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
++ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
++ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
++ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
++ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
++ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
++ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
++ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
++ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
++ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
++ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
++ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
++ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
++ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
++ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
++ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
++ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
++ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
++ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
++ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
++ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
++ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
++ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
++ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
++ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
++ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
++ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
++ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
++ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
++ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
++ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
++ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
++ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
++ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
++ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
++ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
++ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
++ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
++ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
++ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
++ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
++ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
++ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
++ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
++ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
++ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
++ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
++ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
++ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
++ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
++ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
++ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
++ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
++ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
++ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
++ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
++ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
++ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
++ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
++ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
++ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
++ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
++ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
++ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
++ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
++ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
++ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
++ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
++ wbs_stb_i wbs_we_i
+Xbuffer_1_0 vccd1 L1 compaartor_v4_0/Outn vssa1 buffer_1#0
+Xbuffer_1_1 vccd1 L2 compaartor_v4_0/Outp vssa1 buffer_1#0
+Xbuffer_12_0 L4 io_analog[8] L3 vccd1 compaartor_v4_0/CLK vssa1 buffer_12
+Xbuffer_12_1 buffer_12_1/buffer_1_0/inv_W2_0/Vout io_analog[7] buffer_12_1/buffer_1_0/inv_W2_0/Vin
++ vccd1 CB vssa1 buffer_12
+Xcompaartor_v4_0 compaartor_v4_0/Outn io_analog[5] io_analog[6] compaartor_v4_0/CLK
++ vccd1 vssa1 compaartor_v4_0/Outp CB compaartor_v4
+Xbuffer_2_0 io_analog[3] vccd1 vccd1 L1 vssa1 vssa1 buffer_2#0
+Xbuffer_2_1 io_analog[2] vccd1 vccd1 L2 vssa1 vssa1 buffer_2#1
+V0 vssa1 io_clamp_low[1] 0.0
+V1 vssa1 io_clamp_low[2] 0.0
+V2 vccd1 io_clamp_high[2] 0.0
+V3 vccd1 io_clamp_high[1] 0.0
+
+.ends
+
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 120000
index 0000000..48e5b4a
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1 @@
+../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/gds.info b/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
new file mode 100644
index 0000000..b3e16ea
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 9638beca690114cad7d9cedb9242848cc9179b60
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.log
new file mode 100644
index 0000000..0dd882b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 137 (flat) 46 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 23 (flat) 11 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 106 (flat) 38 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:117
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:118
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:119
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:120
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:121
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:122
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:123
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:124
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:125
+ Polygons (raw): 519 (flat) 185 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:126
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:127
+ Polygons (raw): 112 (flat) 57 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:128
+ Polygons (raw): 100 (flat) 40 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:129
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:130
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:131
+ Polygons (raw): 41 (flat) 25 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:132
+ Polygons (raw): 933 (flat) 302 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:134
+ Polygons (raw): 1220 (flat) 495 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:135
+ Polygons (raw): 2078 (flat) 1487 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:137
+ Polygons (raw): 586 (flat) 283 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:138
+ Polygons (raw): 1711 (flat) 1711 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:140
+ Polygons (raw): 569 (flat) 569 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:141
+ Polygons (raw): 1195 (flat) 1195 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:143
+ Polygons (raw): 366 (flat) 366 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:144
+ Polygons (raw): 25602 (flat) 25602 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:146
+ Polygons (raw): 111 (flat) 111 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:147
+ Polygons (raw): 546 (flat) 546 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:149
+ Polygons (raw): 101 (flat) 101 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:151
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:152
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+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:154
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:155
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:156
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:157
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:158
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:159
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:174
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:176
+ Polygons (raw): 1 (flat) 1 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
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+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:180
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:181
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:182
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:183
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:184
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:185
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:186
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:187
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:188
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:189
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:190
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:191
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:192
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:193
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:194
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:195
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:196
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:197
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:198
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:199
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:200
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:201
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:202
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:203
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+DRC section
+BEOL section
+START: 67/20 (li)
+"not" in: sky130A_mr.drc:381
+ Polygons (raw): 1220 (flat) 495 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"width" in: sky130A_mr.drc:382
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"output" in: sky130A_mr.drc:382
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"edges" in: sky130A_mr.drc:384
+ Edges: 3958 (flat) 1686 (hierarchical)
+ Elapsed: 0.040s Memory: 1067.00M
+"space" in: sky130A_mr.drc:384
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.020s Memory: 1067.00M
+"output" in: sky130A_mr.drc:384
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 1067.00M
+"not" in: sky130A_mr.drc:385
+ Polygons (raw): 933 (flat) 302 (hierarchical)
+ Elapsed: 0.010s Memory: 1067.00M
+"enclosing" in: sky130A_mr.drc:386
+ Edge pairs: 1715 (flat) 1635 (hierarchical)
+ Elapsed: 0.040s Memory: 1067.00M
+"second_edges" in: sky130A_mr.drc:386
+ Edges: 1715 (flat) 1635 (hierarchical)
+ Elapsed: 0.000s Memory: 1067.00M
+"width" in: sky130A_mr.drc:387
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.020s Memory: 1068.00M
+"polygons" in: sky130A_mr.drc:388
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 1068.00M
+"interacting" in: sky130A_mr.drc:388
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1068.00M
+"output" in: sky130A_mr.drc:389
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1068.00M
+"with_area" in: sky130A_mr.drc:390
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 1068.00M
+"output" in: sky130A_mr.drc:390
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1068.00M
+END: 67/20 (li)
+START: 67/44 (mcon)
+"not" in: sky130A_mr.drc:395
+ Polygons (raw): 2078 (flat) 1487 (hierarchical)
+ Elapsed: 0.000s Memory: 1068.00M
+"not" in: sky130A_mr.drc:402
+ Polygons (raw): 2078 (flat) 1487 (hierarchical)
+ Elapsed: 0.010s Memory: 1068.00M
+"non_rectangles" in: sky130A_mr.drc:403
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1068.00M
+"output" in: sky130A_mr.drc:403
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 3.730s Memory: 1105.00M
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.log
new file mode 100644
index 0000000..455114a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"output" in: sky130A_mr.drc:372
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+END: 97/44 (cap2m)
+FEOL section
+START: 75/20 (hvi)
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+END: 75/20 (hvi)
+START: 125/20 (hvntm)
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+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 1067.00M
+END: 125/20 (hvntm)
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 1.400s Memory: 1067.00M
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..88e95ed
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+ Elapsed: 0.000s Memory: 522.00M
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+ Elapsed: 0.000s Memory: 522.00M
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+"area" in: met_min_ca_density.lydrc:69
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+"area" in: met_min_ca_density.lydrc:109
+ Elapsed: 0.010s Memory: 522.00M
+m5_ca_density is 0.9846086288332815
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.180s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..c9470c0
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.500s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..c021651
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2305100 kB
+VmHWM: 258936 kB
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..885d85d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541956 kB
+VmHWM: 261948 kB
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.log
new file mode 100644
index 0000000..4515f24
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/pdks.info b/precheck_results/18_MAR_2022___04_22_51/logs/pdks.info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/pdks.info
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/precheck.log b/precheck_results/18_MAR_2022___04_22_51/logs/precheck.log
new file mode 100644
index 0000000..a3848a8
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 04:22:51 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 04:22:51 - [INFO] - {{Project Type Info}} analog
+2022-03-18 04:22:51 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 9638beca690114cad7d9cedb9242848cc9179b60
+2022-03-18 04:22:52 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 04:22:52 - [ERROR] - MPW Precheck failed to get Open PDKs & Skywater PDK versions: Command '['git', '-C', '/usr/local/share/pdk/sky130A/skywater-pdk', 'rev-parse', '--verify', 'HEAD']' returned non-zero exit status 128.
+2022-03-18 04:22:52 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs'
+2022-03-18 04:22:52 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 04:22:52 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 04:22:53 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 04:22:53 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 04:22:53 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 04:22:53 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 04:22:53 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 04:22:53 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 80 non-compliant file(s) with the SPDX Standard.
+2022-03-18 04:22:53 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile_1', '/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info', '/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext', '/home/krishna/Z_submit/mag/compaartor_v4.ext']
+2022-03-18 04:22:53 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/spdx_compliance_report.log
+2022-03-18 04:22:53 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 04:22:53 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 04:22:53 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 04:22:53 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 04:22:53 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 04:22:53 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 04:22:53 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 04:22:53 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 04:22:55 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 04:22:55 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 04:22:55 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 04:22:55 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 04:22:55 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 04:22:55 - [WARNING] - PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['io_clamp_high[1]', 'io_clamp_high[2]', 'io_clamp_low[1]', 'io_clamp_low[2]']
+2022-03-18 04:22:55 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (7 instances).
+2022-03-18 04:22:55 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 04:22:55 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['buffer_2#1']
+2022-03-18 04:22:55 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 2 consistency check(s): ['PORTS', 'LAYOUT'].
+2022-03-18 04:22:55 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
+2022-03-18 04:22:55 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 04:22:56 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/xor_check.total
+2022-03-18 04:22:56 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 04:22:56 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 04:22:57 - [INFO] - 0 DRC violations
+2022-03-18 04:22:57 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:22:57 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 04:22:59 - [INFO] - No DRC Violations found
+2022-03-18 04:22:59 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:22:59 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 04:23:03 - [INFO] - No DRC Violations found
+2022-03-18 04:23:03 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:23:03 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 04:23:05 - [INFO] - No DRC Violations found
+2022-03-18 04:23:05 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:23:05 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 04:23:06 - [INFO] - No DRC Violations found
+2022-03-18 04:23:06 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:23:06 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 04:23:07 - [INFO] - No DRC Violations found
+2022-03-18 04:23:07 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:23:07 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 04:23:08 - [INFO] - No DRC Violations found
+2022-03-18 04:23:08 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:23:08 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs'
+2022-03-18 04:23:08 - [CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['Consistency', 'XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___04_22_51/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..b99e55e
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/spdx_compliance_report.log
@@ -0,0 +1,80 @@
+/home/krishna/Z_submit/Makefile_1
+/home/krishna/Z_submit/Makefile
+/home/krishna/Z_submit/verilog/dv/Makefile
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile
+/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Z_submit/verilog/rtl/example_por.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Z_submit/verilog/rtl/comparator.v
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Z_submit/mag/compaartor_v4.ext
+/home/krishna/Z_submit/mag/inv_W2.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Z_submit/mag/inv_W2#0.ext
+/home/krishna/Z_submit/mag/.magicrc
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Z_submit/mag/comparator_v5.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/buffer_1#0.ext
+/home/krishna/Z_submit/mag/user_analog_project_wrapper.ext
+/home/krishna/Z_submit/mag/comparator_v2.ext
+/home/krishna/Z_submit/mag/comparator_v3.ext
+/home/krishna/Z_submit/mag/buffer_2#0.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Z_submit/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/.spiceinit
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Z_submit/mag/latch/SR_latch.ext
+/home/krishna/Z_submit/mag/latch/sky130A.magicrc
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Z_submit/mag/latch/latch_2.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part1.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part2.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ#0.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#1.ext
+/home/krishna/Z_submit/mag/preamp/.magicrc
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#0.ext
+/home/krishna/Z_submit/xschem/xschemrc
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sym
+/home/krishna/Z_submit/xschem/comparator.sch
+/home/krishna/Z_submit/xschem/comparator.sym
+/home/krishna/Z_submit/xschem/analog_wrapper_tb.sch
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sch
+/home/krishna/Z_submit/xschem/comparator_tb.sch
+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Z_submit/netgen/run_lvs_por.sh
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/tools.info b/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_22_51/logs/xor_check.log b/precheck_results/18_MAR_2022___04_22_51/logs/xor_check.log
new file mode 100644
index 0000000..7df96a5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..672878d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_22_51/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/gds.info b/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
new file mode 100644
index 0000000..b3e16ea
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 9638beca690114cad7d9cedb9242848cc9179b60
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.log
new file mode 100644
index 0000000..3fbbdea
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 137 (flat) 46 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 23 (flat) 11 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 106 (flat) 38 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:117
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:118
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+"polygons" in: sky130A_mr.drc:119
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+"polygons" in: sky130A_mr.drc:120
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+"polygons" in: sky130A_mr.drc:121
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+"polygons" in: sky130A_mr.drc:122
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+"polygons" in: sky130A_mr.drc:123
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+"polygons" in: sky130A_mr.drc:124
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+"polygons" in: sky130A_mr.drc:125
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+"polygons" in: sky130A_mr.drc:126
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:127
+ Polygons (raw): 112 (flat) 57 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:128
+ Polygons (raw): 100 (flat) 40 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:129
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+"polygons" in: sky130A_mr.drc:130
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+"polygons" in: sky130A_mr.drc:131
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+"polygons" in: sky130A_mr.drc:132
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+"polygons" in: sky130A_mr.drc:134
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:137
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:138
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:140
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:141
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:143
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:144
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+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:146
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+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:147
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+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:149
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+"polygons" in: sky130A_mr.drc:156
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+"polygons" in: sky130A_mr.drc:157
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+"polygons" in: sky130A_mr.drc:159
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+"polygons" in: sky130A_mr.drc:163
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+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:164
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+"polygons" in: sky130A_mr.drc:176
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+"polygons" in: sky130A_mr.drc:177
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+"polygons" in: sky130A_mr.drc:178
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+"polygons" in: sky130A_mr.drc:179
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+"polygons" in: sky130A_mr.drc:180
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+"polygons" in: sky130A_mr.drc:181
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+"polygons" in: sky130A_mr.drc:182
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+ Elapsed: 0.000s Memory: 523.00M
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diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.log
new file mode 100644
index 0000000..85eb2c1
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+END: 125/20 (hvntm)
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 1.450s Memory: 1067.00M
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
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\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..e2d0bad
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.log
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+m5_ca_density is 0.9846086288332815
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.170s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
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diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..73e040e
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.log
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+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"ongrid" in: sky130A_mr.drc:738
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"output" in: sky130A_mr.drc:738
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"with_angle" in: sky130A_mr.drc:739
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+ Elapsed: 0.000s Memory: 523.00M
+"output" in: sky130A_mr.drc:739
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+ Elapsed: 0.000s Memory: 523.00M
+"ongrid" in: sky130A_mr.drc:740
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"output" in: sky130A_mr.drc:740
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"with_angle" in: sky130A_mr.drc:741
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"output" in: sky130A_mr.drc:741
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"ongrid" in: sky130A_mr.drc:742
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.130s Memory: 530.00M
+"output" in: sky130A_mr.drc:742
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:743
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+ Elapsed: 0.020s Memory: 530.00M
+"output" in: sky130A_mr.drc:743
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:744
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:744
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:745
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:745
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:746
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:746
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:747
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:747
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:748
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:748
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:749
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:749
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:750
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:750
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:751
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+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:751
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+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:752
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+"output" in: sky130A_mr.drc:753
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+"output" in: sky130A_mr.drc:754
+ Edge pairs: 0 (flat) 0 (hierarchical)
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+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:755
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+ Elapsed: 0.000s Memory: 530.00M
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+ Elapsed: 0.010s Memory: 530.00M
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+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:758
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+ Elapsed: 0.010s Memory: 530.00M
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+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:760
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+"output" in: sky130A_mr.drc:761
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+"ongrid" in: sky130A_mr.drc:762
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+"output" in: sky130A_mr.drc:762
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+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:763
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+"output" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.500s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..35d8b57
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2369824 kB
+VmHWM: 258236 kB
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..6929910
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541952 kB
+VmHWM: 262444 kB
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.log
new file mode 100644
index 0000000..b24444a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info b/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/precheck.log b/precheck_results/18_MAR_2022___04_34_25/logs/precheck.log
new file mode 100644
index 0000000..17805b7
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 04:34:25 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 04:34:25 - [INFO] - {{Project Type Info}} analog
+2022-03-18 04:34:25 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 9638beca690114cad7d9cedb9242848cc9179b60
+2022-03-18 04:34:26 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 04:34:26 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 04:34:26 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs'
+2022-03-18 04:34:26 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 04:34:26 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 04:34:27 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 04:34:27 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 04:34:27 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 04:34:27 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 04:34:27 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 04:34:27 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 90 non-compliant file(s) with the SPDX Standard.
+2022-03-18 04:34:27 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/gds.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total']
+2022-03-18 04:34:27 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/spdx_compliance_report.log
+2022-03-18 04:34:27 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 04:34:27 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 04:34:27 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 04:34:27 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 04:34:27 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 04:34:27 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 04:34:27 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 04:34:27 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 04:34:29 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 04:34:29 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 04:34:29 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 04:34:29 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 04:34:29 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 04:34:29 - [WARNING] - PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['io_clamp_high[1]', 'io_clamp_high[2]', 'io_clamp_low[1]', 'io_clamp_low[2]']
+2022-03-18 04:34:29 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (7 instances).
+2022-03-18 04:34:29 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 04:34:29 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['buffer_2#1']
+2022-03-18 04:34:29 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 2 consistency check(s): ['PORTS', 'LAYOUT'].
+2022-03-18 04:34:29 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
+2022-03-18 04:34:29 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 04:34:30 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/xor_check.total
+2022-03-18 04:34:30 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 04:34:30 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 04:34:31 - [INFO] - 0 DRC violations
+2022-03-18 04:34:31 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:31 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 04:34:33 - [INFO] - No DRC Violations found
+2022-03-18 04:34:33 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:33 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 04:34:37 - [INFO] - No DRC Violations found
+2022-03-18 04:34:37 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:37 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 04:34:39 - [INFO] - No DRC Violations found
+2022-03-18 04:34:39 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:39 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 04:34:40 - [INFO] - No DRC Violations found
+2022-03-18 04:34:40 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:40 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 04:34:41 - [INFO] - No DRC Violations found
+2022-03-18 04:34:41 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:41 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 04:34:42 - [INFO] - No DRC Violations found
+2022-03-18 04:34:42 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:34:42 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs'
+2022-03-18 04:34:42 - [CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['Consistency', 'XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___04_34_25/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..433db78
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/spdx_compliance_report.log
@@ -0,0 +1,90 @@
+/home/krishna/Z_submit/Makefile
+/home/krishna/Z_submit/verilog/dv/Makefile
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile
+/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Z_submit/verilog/rtl/example_por.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Z_submit/verilog/rtl/comparator.v
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Z_submit/mag/compaartor_v4.ext
+/home/krishna/Z_submit/mag/inv_W2.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Z_submit/mag/inv_W2#0.ext
+/home/krishna/Z_submit/mag/.magicrc
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Z_submit/mag/comparator_v5.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/buffer_1#0.ext
+/home/krishna/Z_submit/mag/user_analog_project_wrapper.ext
+/home/krishna/Z_submit/mag/comparator_v2.ext
+/home/krishna/Z_submit/mag/comparator_v3.ext
+/home/krishna/Z_submit/mag/buffer_2#0.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Z_submit/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/.spiceinit
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Z_submit/mag/latch/SR_latch.ext
+/home/krishna/Z_submit/mag/latch/sky130A.magicrc
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Z_submit/mag/latch/latch_2.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part1.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part2.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ#0.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#1.ext
+/home/krishna/Z_submit/mag/preamp/.magicrc
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#0.ext
+/home/krishna/Z_submit/xschem/xschemrc
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sym
+/home/krishna/Z_submit/xschem/comparator.sch
+/home/krishna/Z_submit/xschem/comparator.sym
+/home/krishna/Z_submit/xschem/analog_wrapper_tb.sch
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sch
+/home/krishna/Z_submit/xschem/comparator_tb.sch
+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Z_submit/netgen/run_lvs_por.sh
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/tools.info b/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_34_25/logs/xor_check.log b/precheck_results/18_MAR_2022___04_34_25/logs/xor_check.log
new file mode 100644
index 0000000..56cd02a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..bbc84e7
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_34_25/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/gds.info b/precheck_results/18_MAR_2022___04_53_15/logs/gds.info
new file mode 100644
index 0000000..57d18b0
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: a523d1ac8d968bb504f0cc4b70c3c4b5742c0474
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.log
new file mode 100644
index 0000000..36bae0a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 137 (flat) 46 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 23 (flat) 11 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 106 (flat) 38 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:117
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:118
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:119
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:120
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:121
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:122
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:123
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:124
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:125
+ Polygons (raw): 519 (flat) 185 (hierarchical)
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+END: 72/20 (m5)
+START: 76/20 (pad)
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+END: 76/20 (pad)
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 3.720s Memory: 1105.00M
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.log
new file mode 100644
index 0000000..405a038
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+ Elapsed: 0.010s Memory: 522.00M
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diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..e218d1a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.log
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+ Elapsed: 0.010s Memory: 522.00M
+"area" in: met_min_ca_density.lydrc:109
+ Elapsed: 0.000s Memory: 522.00M
+m5_ca_density is 0.9846086288332815
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.180s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..be22c8e
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.490s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..b9408f0
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2369824 kB
+VmHWM: 258540 kB
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..8a553ea
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541956 kB
+VmHWM: 262584 kB
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.log
new file mode 100644
index 0000000..700333a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/pdks.info b/precheck_results/18_MAR_2022___04_53_15/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/precheck.log b/precheck_results/18_MAR_2022___04_53_15/logs/precheck.log
new file mode 100644
index 0000000..cc4837c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 04:53:15 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 04:53:15 - [INFO] - {{Project Type Info}} analog
+2022-03-18 04:53:15 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: a523d1ac8d968bb504f0cc4b70c3c4b5742c0474
+2022-03-18 04:53:15 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 04:53:15 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 04:53:15 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs'
+2022-03-18 04:53:15 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 04:53:15 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 04:53:16 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 04:53:16 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 04:53:16 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 04:53:16 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 04:53:16 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 04:53:16 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 102 non-compliant file(s) with the SPDX Standard.
+2022-03-18 04:53:16 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total']
+2022-03-18 04:53:16 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/spdx_compliance_report.log
+2022-03-18 04:53:16 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 04:53:16 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 04:53:16 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 04:53:16 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 04:53:16 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 04:53:16 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 04:53:16 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 04:53:16 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 04:53:18 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 04:53:18 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 04:53:18 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 04:53:18 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 04:53:18 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 04:53:18 - [WARNING] - PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['io_clamp_high[1]', 'io_clamp_high[2]', 'io_clamp_low[1]', 'io_clamp_low[2]']
+2022-03-18 04:53:18 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (7 instances).
+2022-03-18 04:53:18 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 04:53:18 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['buffer_2#1']
+2022-03-18 04:53:18 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 2 consistency check(s): ['PORTS', 'LAYOUT'].
+2022-03-18 04:53:18 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
+2022-03-18 04:53:18 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 04:53:19 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/xor_check.total
+2022-03-18 04:53:19 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 04:53:19 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 04:53:19 - [INFO] - 0 DRC violations
+2022-03-18 04:53:19 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:19 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 04:53:22 - [INFO] - No DRC Violations found
+2022-03-18 04:53:22 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:22 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 04:53:26 - [INFO] - No DRC Violations found
+2022-03-18 04:53:26 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:26 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 04:53:28 - [INFO] - No DRC Violations found
+2022-03-18 04:53:28 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:28 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 04:53:29 - [INFO] - No DRC Violations found
+2022-03-18 04:53:29 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:29 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 04:53:31 - [INFO] - No DRC Violations found
+2022-03-18 04:53:31 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:31 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 04:53:31 - [INFO] - No DRC Violations found
+2022-03-18 04:53:31 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 04:53:31 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs'
+2022-03-18 04:53:31 - [CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['Consistency', 'XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___04_53_15/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..b5cdb4a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/spdx_compliance_report.log
@@ -0,0 +1,102 @@
+/home/krishna/Z_submit/Makefile
+/home/krishna/Z_submit/verilog/dv/Makefile
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile
+/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Z_submit/verilog/rtl/example_por.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Z_submit/verilog/rtl/comparator.v
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/pdks.info
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Z_submit/mag/compaartor_v4.ext
+/home/krishna/Z_submit/mag/inv_W2.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Z_submit/mag/inv_W2#0.ext
+/home/krishna/Z_submit/mag/.magicrc
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Z_submit/mag/comparator_v5.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/buffer_2#1.ext
+/home/krishna/Z_submit/mag/buffer_1#0.ext
+/home/krishna/Z_submit/mag/user_analog_project_wrapper.ext
+/home/krishna/Z_submit/mag/comparator_v2.ext
+/home/krishna/Z_submit/mag/comparator_v3.ext
+/home/krishna/Z_submit/mag/buffer_2#0.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Z_submit/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/.spiceinit
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Z_submit/mag/latch/SR_latch.ext
+/home/krishna/Z_submit/mag/latch/sky130A.magicrc
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Z_submit/mag/latch/latch_2.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part1.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part2.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ#0.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#1.ext
+/home/krishna/Z_submit/mag/preamp/.magicrc
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#0.ext
+/home/krishna/Z_submit/xschem/xschemrc
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sym
+/home/krishna/Z_submit/xschem/comparator.sch
+/home/krishna/Z_submit/xschem/comparator.sym
+/home/krishna/Z_submit/xschem/analog_wrapper_tb.sch
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sch
+/home/krishna/Z_submit/xschem/comparator_tb.sch
+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Z_submit/netgen/run_lvs_por.sh
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/tools.info b/precheck_results/18_MAR_2022___04_53_15/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___04_53_15/logs/xor_check.log b/precheck_results/18_MAR_2022___04_53_15/logs/xor_check.log
new file mode 100644
index 0000000..112a6c9
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..dd72660
--- /dev/null
+++ b/precheck_results/18_MAR_2022___04_53_15/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/gds.info b/precheck_results/18_MAR_2022___05_01_55/logs/gds.info
new file mode 100644
index 0000000..57d18b0
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: a523d1ac8d968bb504f0cc4b70c3c4b5742c0474
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.log
new file mode 100644
index 0000000..0794420
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
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+"polygons" in: sky130A_mr.drc:115
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+"polygons" in: sky130A_mr.drc:116
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+"polygons" in: sky130A_mr.drc:117
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+"polygons" in: sky130A_mr.drc:128
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+"polygons" in: sky130A_mr.drc:131
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+"polygons" in: sky130A_mr.drc:203
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+DRC section
+BEOL section
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+"second_edges" in: sky130A_mr.drc:386
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+"output" in: sky130A_mr.drc:390
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+END: 67/20 (li)
+START: 67/44 (mcon)
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_beol_check.xml ..
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diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.log
new file mode 100644
index 0000000..504647d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+FEOL section
+START: 75/20 (hvi)
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+END: 75/20 (hvi)
+START: 125/20 (hvntm)
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+ Elapsed: 0.000s Memory: 1067.00M
+END: 125/20 (hvntm)
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 1.420s Memory: 1067.00M
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..bc8a027
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+"area" in: met_min_ca_density.lydrc:109
+ Elapsed: 0.000s Memory: 522.00M
+m5_ca_density is 0.9846086288332815
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.160s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..f91827d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:758
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:758
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:759
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:759
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.440s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..fb3700d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2369824 kB
+VmHWM: 258896 kB
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..7916392
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541952 kB
+VmHWM: 262408 kB
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.log
new file mode 100644
index 0000000..fd86154
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info b/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/precheck.log b/precheck_results/18_MAR_2022___05_01_55/logs/precheck.log
new file mode 100644
index 0000000..d58591d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 05:01:55 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 05:01:55 - [INFO] - {{Project Type Info}} analog
+2022-03-18 05:01:55 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: a523d1ac8d968bb504f0cc4b70c3c4b5742c0474
+2022-03-18 05:01:55 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 05:01:55 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 05:01:55 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs'
+2022-03-18 05:01:55 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 05:01:55 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 05:01:56 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 05:01:56 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 05:01:56 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 05:01:56 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 05:01:56 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 05:01:56 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 113 non-compliant file(s) with the SPDX Standard.
+2022-03-18 05:01:56 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/gds.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total']
+2022-03-18 05:01:56 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/spdx_compliance_report.log
+2022-03-18 05:01:56 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 05:01:56 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 05:01:56 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 05:01:56 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 05:01:57 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 05:01:57 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 05:01:57 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 05:01:57 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 05:01:58 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 05:01:58 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 05:01:58 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 05:01:58 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 05:01:58 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 05:01:58 - [WARNING] - PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['io_clamp_high[1]', 'io_clamp_high[2]', 'io_clamp_low[1]', 'io_clamp_low[2]']
+2022-03-18 05:01:58 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (7 instances).
+2022-03-18 05:01:58 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 05:01:58 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['buffer_2#1']
+2022-03-18 05:01:58 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 2 consistency check(s): ['PORTS', 'LAYOUT'].
+2022-03-18 05:01:58 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
+2022-03-18 05:01:58 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 05:02:00 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/xor_check.total
+2022-03-18 05:02:00 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 05:02:00 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 05:02:00 - [INFO] - 0 DRC violations
+2022-03-18 05:02:00 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:00 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 05:02:02 - [INFO] - No DRC Violations found
+2022-03-18 05:02:02 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:02 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 05:02:06 - [INFO] - No DRC Violations found
+2022-03-18 05:02:06 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:06 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 05:02:08 - [INFO] - No DRC Violations found
+2022-03-18 05:02:08 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:08 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 05:02:09 - [INFO] - No DRC Violations found
+2022-03-18 05:02:09 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:09 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 05:02:11 - [INFO] - No DRC Violations found
+2022-03-18 05:02:11 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:11 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 05:02:11 - [INFO] - No DRC Violations found
+2022-03-18 05:02:11 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:02:11 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs'
+2022-03-18 05:02:11 - [CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['Consistency', 'XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___05_01_55/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..0644d76
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/spdx_compliance_report.log
@@ -0,0 +1,113 @@
+/home/krishna/Z_submit/Makefile
+/home/krishna/Z_submit/verilog/dv/Makefile
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile
+/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Z_submit/verilog/rtl/example_por.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Z_submit/verilog/rtl/comparator.v
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Z_submit/mag/compaartor_v4.ext
+/home/krishna/Z_submit/mag/inv_W2.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Z_submit/mag/inv_W2#0.ext
+/home/krishna/Z_submit/mag/.magicrc
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Z_submit/mag/comparator_v5.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/buffer_2#1.ext
+/home/krishna/Z_submit/mag/buffer_1#0.ext
+/home/krishna/Z_submit/mag/user_analog_project_wrapper.ext
+/home/krishna/Z_submit/mag/comparator_v2.ext
+/home/krishna/Z_submit/mag/comparator_v3.ext
+/home/krishna/Z_submit/mag/buffer_2#0.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Z_submit/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/.spiceinit
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Z_submit/mag/latch/SR_latch.ext
+/home/krishna/Z_submit/mag/latch/sky130A.magicrc
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Z_submit/mag/latch/latch_2.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part1.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part2.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ#0.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#1.ext
+/home/krishna/Z_submit/mag/preamp/.magicrc
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#0.ext
+/home/krishna/Z_submit/xschem/xschemrc
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sym
+/home/krishna/Z_submit/xschem/comparator.sch
+/home/krishna/Z_submit/xschem/comparator.sym
+/home/krishna/Z_submit/xschem/analog_wrapper_tb.sch
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sch
+/home/krishna/Z_submit/xschem/comparator_tb.sch
+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Z_submit/netgen/run_lvs_por.sh
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/tools.info b/precheck_results/18_MAR_2022___05_01_55/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_01_55/logs/xor_check.log b/precheck_results/18_MAR_2022___05_01_55/logs/xor_check.log
new file mode 100644
index 0000000..ba56321
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..3ecb377
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_01_55/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/gds.info b/precheck_results/18_MAR_2022___05_10_50/logs/gds.info
new file mode 100644
index 0000000..8d5d096
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 0c0393da709b73f5b9958dda6dd844be3fc5bd03
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.log
new file mode 100644
index 0000000..50022af
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 137 (flat) 46 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 23 (flat) 11 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 106 (flat) 38 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:117
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:118
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:119
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:120
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:121
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:122
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:123
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:124
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:125
+ Polygons (raw): 519 (flat) 185 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:126
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:127
+ Polygons (raw): 112 (flat) 57 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:128
+ Polygons (raw): 100 (flat) 40 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:129
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:130
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:131
+ Polygons (raw): 41 (flat) 25 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:132
+ Polygons (raw): 933 (flat) 302 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:134
+ Polygons (raw): 1220 (flat) 495 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:135
+ Polygons (raw): 2078 (flat) 1487 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:137
+ Polygons (raw): 586 (flat) 283 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:138
+ Polygons (raw): 1711 (flat) 1711 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:140
+ Polygons (raw): 569 (flat) 569 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:141
+ Polygons (raw): 1195 (flat) 1195 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:143
+ Polygons (raw): 366 (flat) 366 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:144
+ Polygons (raw): 25602 (flat) 25602 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:146
+ Polygons (raw): 111 (flat) 111 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:147
+ Polygons (raw): 546 (flat) 546 (hierarchical)
+ Elapsed: 0.000s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:149
+ Polygons (raw): 101 (flat) 101 (hierarchical)
+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:151
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diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.total
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index 0000000..c227083
--- /dev/null
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\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_feol_check.log
new file mode 100644
index 0000000..2030a7a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_feol_check.log
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+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 1.400s Memory: 1067.00M
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
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\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..ba7f300
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_met_min_ca_density_check.log
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+m5_ca_density is 0.9846086288332815
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.170s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
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\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..f6f2c99
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.log
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+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
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+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.480s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..23f8be4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2305096 kB
+VmHWM: 258528 kB
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..b830823
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541952 kB
+VmHWM: 262376 kB
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.log
new file mode 100644
index 0000000..6ba9982
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/pdks.info b/precheck_results/18_MAR_2022___05_10_50/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/precheck.log b/precheck_results/18_MAR_2022___05_10_50/logs/precheck.log
new file mode 100644
index 0000000..a8a2084
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 05:10:50 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 05:10:50 - [INFO] - {{Project Type Info}} analog
+2022-03-18 05:10:50 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 0c0393da709b73f5b9958dda6dd844be3fc5bd03
+2022-03-18 05:10:50 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 05:10:50 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 05:10:50 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs'
+2022-03-18 05:10:50 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 05:10:50 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 05:10:51 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 05:10:51 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 05:10:51 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 05:10:51 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 05:10:51 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 05:10:51 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 124 non-compliant file(s) with the SPDX Standard.
+2022-03-18 05:10:51 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/gds.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/pdks.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.total']
+2022-03-18 05:10:51 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/spdx_compliance_report.log
+2022-03-18 05:10:51 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 05:10:51 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 05:10:51 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 05:10:51 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 05:10:51 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 05:10:51 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 05:10:51 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 05:10:51 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 05:10:53 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 05:10:53 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 05:10:53 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 05:10:53 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 05:10:53 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 05:10:53 - [WARNING] - PORTS CHECK FAILED: user_analog_project_wrapper ports do not match the golden wrapper ports. Mismatching ports are : ['io_clamp_high[1]', 'io_clamp_high[2]', 'io_clamp_low[1]', 'io_clamp_low[2]']
+2022-03-18 05:10:53 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (7 instances).
+2022-03-18 05:10:53 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 05:10:53 - [WARNING] - LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['buffer_2#1']
+2022-03-18 05:10:53 - [WARNING] - {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 2 consistency check(s): ['PORTS', 'LAYOUT'].
+2022-03-18 05:10:53 - [WARNING] - {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
+2022-03-18 05:10:53 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 05:10:55 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/xor_check.total
+2022-03-18 05:10:55 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 05:10:55 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 05:10:55 - [INFO] - 0 DRC violations
+2022-03-18 05:10:55 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:10:55 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 05:10:57 - [INFO] - No DRC Violations found
+2022-03-18 05:10:57 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:10:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 05:11:01 - [INFO] - No DRC Violations found
+2022-03-18 05:11:01 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:11:01 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 05:11:03 - [INFO] - No DRC Violations found
+2022-03-18 05:11:03 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:11:03 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 05:11:04 - [INFO] - No DRC Violations found
+2022-03-18 05:11:04 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:11:04 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 05:11:05 - [INFO] - No DRC Violations found
+2022-03-18 05:11:05 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:11:05 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 05:11:06 - [INFO] - No DRC Violations found
+2022-03-18 05:11:06 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 05:11:06 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs'
+2022-03-18 05:11:06 - [CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['Consistency', 'XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___05_10_50/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..2bcacca
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/spdx_compliance_report.log
@@ -0,0 +1,124 @@
+/home/krishna/Z_submit/Makefile
+/home/krishna/Z_submit/verilog/dv/Makefile
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile
+/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Z_submit/verilog/rtl/example_por.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Z_submit/verilog/rtl/comparator.v
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.total
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+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/gds.info
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+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
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+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/buffer_2#1.ext
+/home/krishna/Z_submit/mag/buffer_1#0.ext
+/home/krishna/Z_submit/mag/user_analog_project_wrapper.ext
+/home/krishna/Z_submit/mag/comparator_v2.ext
+/home/krishna/Z_submit/mag/comparator_v3.ext
+/home/krishna/Z_submit/mag/buffer_2#0.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv.ext
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+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
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diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/tools.info b/precheck_results/18_MAR_2022___05_10_50/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___05_10_50/logs/xor_check.log b/precheck_results/18_MAR_2022___05_10_50/logs/xor_check.log
new file mode 100644
index 0000000..641a7f4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..94f0cd1
--- /dev/null
+++ b/precheck_results/18_MAR_2022___05_10_50/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/gds.info b/precheck_results/18_MAR_2022___11_35_41/logs/gds.info
new file mode 100644
index 0000000..8d5d096
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 0c0393da709b73f5b9958dda6dd844be3fc5bd03
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_beol_check.log
new file mode 100644
index 0000000..08782c2
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
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+"polygons" in: sky130A_mr.drc:115
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+"polygons" in: sky130A_mr.drc:116
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+"polygons" in: sky130A_mr.drc:117
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+DRC section
+BEOL section
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+"second_edges" in: sky130A_mr.drc:386
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+"output" in: sky130A_mr.drc:390
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+START: 67/44 (mcon)
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 3.700s Memory: 1105.00M
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_feol_check.log
new file mode 100644
index 0000000..f6a61c1
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+FEOL section
+START: 75/20 (hvi)
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+END: 75/20 (hvi)
+START: 125/20 (hvntm)
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+ Elapsed: 0.000s Memory: 1067.00M
+END: 125/20 (hvntm)
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_feol_check.xml ..
+Total elapsed: 1.400s Memory: 1067.00M
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_feol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..439ca75
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_met_min_ca_density_check.log
@@ -0,0 +1,79 @@
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+"area" in: met_min_ca_density.lydrc:109
+ Elapsed: 0.000s Memory: 522.00M
+m5_ca_density is 0.9846086288332815
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.170s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..e5eb595
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"output" in: sky130A_mr.drc:758
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:759
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:759
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.430s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..bfa43de
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2369824 kB
+VmHWM: 259140 kB
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..2e5a6e2
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541952 kB
+VmHWM: 262532 kB
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/magic_drc_check.log
new file mode 100644
index 0000000..34d391d
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___11_35_41/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/pdks.info b/precheck_results/18_MAR_2022___11_35_41/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/precheck.log b/precheck_results/18_MAR_2022___11_35_41/logs/precheck.log
new file mode 100644
index 0000000..f50a7c1
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 11:35:41 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 11:35:41 - [INFO] - {{Project Type Info}} analog
+2022-03-18 11:35:41 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 0c0393da709b73f5b9958dda6dd844be3fc5bd03
+2022-03-18 11:35:42 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 11:35:42 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 11:35:42 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs'
+2022-03-18 11:35:42 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 11:35:42 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 11:35:43 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 11:35:43 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 11:35:43 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 11:35:43 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 11:35:43 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 11:35:43 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 135 non-compliant file(s) with the SPDX Standard.
+2022-03-18 11:35:43 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total']
+2022-03-18 11:35:43 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs/spdx_compliance_report.log
+2022-03-18 11:35:43 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 11:35:43 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 11:35:43 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 11:35:43 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 11:35:43 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 11:35:43 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 11:35:43 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 11:35:43 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 11:35:45 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 11:35:45 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 11:35:45 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 11:35:45 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 11:35:45 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 11:35:45 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
+2022-03-18 11:35:45 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (11 instances).
+2022-03-18 11:35:45 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 11:35:45 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
+2022-03-18 11:35:45 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
+2022-03-18 11:35:45 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-03-18 11:35:45 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 11:35:47 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs/xor_check.total
+2022-03-18 11:35:47 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 11:35:47 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 11:35:47 - [INFO] - 0 DRC violations
+2022-03-18 11:35:47 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:47 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 11:35:49 - [INFO] - No DRC Violations found
+2022-03-18 11:35:49 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:49 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 11:35:53 - [INFO] - No DRC Violations found
+2022-03-18 11:35:53 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:53 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 11:35:55 - [INFO] - No DRC Violations found
+2022-03-18 11:35:55 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:55 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 11:35:56 - [INFO] - No DRC Violations found
+2022-03-18 11:35:56 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:56 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 11:35:57 - [INFO] - No DRC Violations found
+2022-03-18 11:35:57 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:57 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 11:35:58 - [INFO] - No DRC Violations found
+2022-03-18 11:35:58 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:35:58 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs'
+2022-03-18 11:35:58 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___11_35_41/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..f08f98a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/spdx_compliance_report.log
@@ -0,0 +1,135 @@
+/home/krishna/Z_submit/Makefile
+/home/krishna/Z_submit/verilog/dv/Makefile
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c
+/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v
+/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile
+/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v
+/home/krishna/Z_submit/verilog/rtl/example_por.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v
+/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v
+/home/krishna/Z_submit/verilog/rtl/comparator.v
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_01_55/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_34_25/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_22_51/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/outputs/reports/magic_drc_check.drc.report
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_zeroarea_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/tools.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_beol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_feol_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/gds.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/pdks.info
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/magic_drc_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_offgrid_check.total
+/home/krishna/Z_submit/precheck_results/18_MAR_2022___04_53_15/logs/klayout_met_min_ca_density_check.total
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B#0.ext
+/home/krishna/Z_submit/mag/compaartor_v4.ext
+/home/krishna/Z_submit/mag/inv_W2.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_KLAK3C.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__diode_pw2nd_05v5_FT7GK8.ext
+/home/krishna/Z_submit/mag/inv_W2#0.ext
+/home/krishna/Z_submit/mag/.magicrc
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ#1.ext
+/home/krishna/Z_submit/mag/comparator_v5.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/buffer_2#1.ext
+/home/krishna/Z_submit/mag/buffer_1#0.ext
+/home/krishna/Z_submit/mag/user_analog_project_wrapper.ext
+/home/krishna/Z_submit/mag/comparator_v2.ext
+/home/krishna/Z_submit/mag/comparator_v3.ext
+/home/krishna/Z_submit/mag/buffer_2#0.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_VJWT33.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_7RYEVP.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_RL4NCG.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_KZU588.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/nmos_1u.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_5YYKDE.ext
+/home/krishna/Z_submit/mag/myinv_layout2/pmos_2uf2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130A.magicrc
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_3M44SC.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_2.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W8.ext
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_sample_lay.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_XJTKXQ.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__nfet_01v8_QQ4XG9.ext
+/home/krishna/Z_submit/mag/myinv_layout2/sky130_fd_pr__pfet_01v8_AC5Z8B.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W1.ext
+/home/krishna/Z_submit/mag/myinv_layout2/.spiceinit
+/home/krishna/Z_submit/mag/myinv_layout2/buffer_12.ext
+/home/krishna/Z_submit/mag/myinv_layout2/inv_W16.ext
+/home/krishna/Z_submit/mag/latch/SR_latch.ext
+/home/krishna/Z_submit/mag/latch/sky130A.magicrc
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_AC5E9B.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__nfet_01v8_F5U58G.ext
+/home/krishna/Z_submit/mag/latch/latch_2.ext
+/home/krishna/Z_submit/mag/latch/sky130_fd_pr__pfet_01v8_5SVZDE.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_G6PLX8.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part1.ext
+/home/krishna/Z_submit/mag/preamp/preamp_part2.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ#0.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#1.ext
+/home/krishna/Z_submit/mag/preamp/.magicrc
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#0.ext
+/home/krishna/Z_submit/xschem/xschemrc
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sym
+/home/krishna/Z_submit/xschem/comparator.sch
+/home/krishna/Z_submit/xschem/comparator.sym
+/home/krishna/Z_submit/xschem/analog_wrapper_tb.sch
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sch
+/home/krishna/Z_submit/xschem/comparator_tb.sch
+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Z_submit/netgen/run_lvs_por.sh
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/tools.info b/precheck_results/18_MAR_2022___11_35_41/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_35_41/logs/xor_check.log b/precheck_results/18_MAR_2022___11_35_41/logs/xor_check.log
new file mode 100644
index 0000000..659b325
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..aaeb6c9
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_35_41/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/gds.info b/precheck_results/18_MAR_2022___11_37_48/logs/gds.info
new file mode 100644
index 0000000..6434b3c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 57aa46bb81024d8cdd5c1162c116443cb18a3ee9
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_beol_check.log
new file mode 100644
index 0000000..eb1abd7
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 137 (flat) 46 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 23 (flat) 11 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 106 (flat) 38 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:117
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:118
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:119
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:120
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:121
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:122
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:123
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:124
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:125
+ Polygons (raw): 519 (flat) 185 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:126
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:127
+ Polygons (raw): 112 (flat) 57 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:128
+ Polygons (raw): 100 (flat) 40 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:129
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_beol_check.xml ..
+Total elapsed: 3.680s Memory: 1105.00M
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_feol_check.log
new file mode 100644
index 0000000..e889789
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
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+"polygons" in: sky130A_mr.drc:117
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diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_feol_check.total
new file mode 100644
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diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..a30b623
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_met_min_ca_density_check.xml ..
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diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_met_min_ca_density_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_met_min_ca_density_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..a929727
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_offgrid_check.log
@@ -0,0 +1,755 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.460s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..4dc4630
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2369828 kB
+VmHWM: 259300 kB
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..a336428
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541956 kB
+VmHWM: 262092 kB
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/magic_drc_check.log
new file mode 100644
index 0000000..71674b1
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___11_37_48/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/pdks.info b/precheck_results/18_MAR_2022___11_37_48/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/precheck.log b/precheck_results/18_MAR_2022___11_37_48/logs/precheck.log
new file mode 100644
index 0000000..330c0d0
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 11:37:48 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 11:37:48 - [INFO] - {{Project Type Info}} analog
+2022-03-18 11:37:48 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 57aa46bb81024d8cdd5c1162c116443cb18a3ee9
+2022-03-18 11:37:48 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 11:37:48 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 11:37:48 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/logs'
+2022-03-18 11:37:48 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 11:37:48 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 11:37:49 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 11:37:49 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 11:37:49 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 11:37:49 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 11:37:49 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 11:37:49 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 146 non-compliant file(s) with the SPDX Standard.
+2022-03-18 11:37:49 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total']
+2022-03-18 11:37:49 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/logs/spdx_compliance_report.log
+2022-03-18 11:37:49 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 11:37:49 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 11:37:49 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 11:37:49 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 11:37:49 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 11:37:49 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 11:37:49 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 11:37:49 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 11:37:51 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 11:37:51 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 11:37:51 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 11:37:51 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 11:37:51 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 11:37:51 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
+2022-03-18 11:37:51 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (11 instances).
+2022-03-18 11:37:51 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 11:37:51 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
+2022-03-18 11:37:51 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
+2022-03-18 11:37:51 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-03-18 11:37:51 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 11:37:52 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/logs/xor_check.total
+2022-03-18 11:37:52 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 11:37:52 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 11:37:52 - [INFO] - 0 DRC violations
+2022-03-18 11:37:52 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:37:52 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 11:37:54 - [INFO] - No DRC Violations found
+2022-03-18 11:37:54 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:37:54 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 11:37:59 - [INFO] - No DRC Violations found
+2022-03-18 11:37:59 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:37:59 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 11:38:01 - [INFO] - No DRC Violations found
+2022-03-18 11:38:01 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:38:01 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 11:38:02 - [INFO] - No DRC Violations found
+2022-03-18 11:38:02 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:38:02 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 11:38:03 - [INFO] - No DRC Violations found
+2022-03-18 11:38:03 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:38:03 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 11:38:04 - [INFO] - No DRC Violations found
+2022-03-18 11:38:04 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:38:04 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/logs'
+2022-03-18 11:38:04 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___11_37_48/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..02cc362
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/spdx_compliance_report.log
@@ -0,0 +1,146 @@
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+/home/krishna/Z_submit/mag/preamp/preamp_part2.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_XJTKXQ#0.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#1.ext
+/home/krishna/Z_submit/mag/preamp/.magicrc
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__pfet_01v8_RFM3CD.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_8FHE5N.ext
+/home/krishna/Z_submit/mag/preamp/sky130_fd_pr__nfet_01v8_F5U58G#0.ext
+/home/krishna/Z_submit/xschem/xschemrc
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sym
+/home/krishna/Z_submit/xschem/comparator.sch
+/home/krishna/Z_submit/xschem/comparator.sym
+/home/krishna/Z_submit/xschem/analog_wrapper_tb.sch
+/home/krishna/Z_submit/xschem/user_analog_project_wrapper.sch
+/home/krishna/Z_submit/xschem/comparator_tb.sch
+/home/krishna/Z_submit/docs/Makefile
+/home/krishna/Z_submit/docs/environment.yml
+/home/krishna/Z_submit/docs/source/conf.py
+/home/krishna/Z_submit/docs/source/index.rst
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_verilog.sh
+/home/krishna/Z_submit/netgen/run_lvs_por.sh
+/home/krishna/Z_submit/netgen/run_lvs_wrapper_xschem.sh
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/tools.info b/precheck_results/18_MAR_2022___11_37_48/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_37_48/logs/xor_check.log b/precheck_results/18_MAR_2022___11_37_48/logs/xor_check.log
new file mode 100644
index 0000000..f99a301
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..d217da2
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_37_48/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/gds.info b/precheck_results/18_MAR_2022___11_45_48/logs/gds.info
new file mode 100644
index 0000000..1866c38
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/gds.info
@@ -0,0 +1 @@
+user_analog_project_wrapper.gds: 4a44d55b7e75babda3cf15c027ff7cf2441ccf99
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_beol_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_beol_check.log
new file mode 100644
index 0000000..dd3a5ae
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_beol_check.log
@@ -0,0 +1,992 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:38: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:42: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
+"input" in: sky130A_mr.drc:112
+ Polygons (raw): 137 (flat) 46 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:113
+ Polygons (raw): 23 (flat) 11 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:114
+ Polygons (raw): 106 (flat) 38 (hierarchical)
+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:115
+ Polygons (raw): 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:116
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+ Elapsed: 0.010s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:117
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+"polygons" in: sky130A_mr.drc:118
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+"polygons" in: sky130A_mr.drc:120
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+"polygons" in: sky130A_mr.drc:127
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+ Elapsed: 0.000s Memory: 522.00M
+"polygons" in: sky130A_mr.drc:128
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+"polygons" in: sky130A_mr.drc:131
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+ Elapsed: 0.010s Memory: 522.00M
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+"polygons" in: sky130A_mr.drc:189
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+"polygons" in: sky130A_mr.drc:190
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+"polygons" in: sky130A_mr.drc:191
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+ Elapsed: 0.010s Memory: 523.00M
+"polygons" in: sky130A_mr.drc:192
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diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_beol_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_beol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_beol_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_feol_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_feol_check.log
new file mode 100644
index 0000000..230d117
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_feol_check.log
@@ -0,0 +1,789 @@
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:36: warning: already initialized constant DRC::DRCEngine::FEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:28: warning: previous definition of FEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:50: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+Total elapsed: 1.420s Memory: 1067.00M
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_feol_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_feol_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
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diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_met_min_ca_density_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_met_min_ca_density_check.log
new file mode 100644
index 0000000..f7c249e
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_met_min_ca_density_check.log
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+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_met_min_ca_density_check.xml ..
+Total elapsed: 0.160s Memory: 522.00M
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_met_min_ca_density_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_met_min_ca_density_check.total
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index 0000000..c227083
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diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_offgrid_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_offgrid_check.log
new file mode 100644
index 0000000..df44b0f
--- /dev/null
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+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:44: warning: already initialized constant DRC::DRCEngine::BEOL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:29: warning: previous definition of BEOL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:48: warning: already initialized constant DRC::DRCEngine::OFFGRID
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:30: warning: previous definition of OFFGRID was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:56: warning: already initialized constant DRC::DRCEngine::SEAL
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:31: warning: previous definition of SEAL was here
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:62: warning: already initialized constant DRC::DRCEngine::FLOATING_MET
+/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc:32: warning: previous definition of FLOATING_MET was here
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+"with_angle" in: sky130A_mr.drc:743
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.020s Memory: 530.00M
+"output" in: sky130A_mr.drc:743
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:744
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:744
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:745
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:745
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:746
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:746
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:747
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:747
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:748
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:748
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:749
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:749
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:750
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:750
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:751
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:751
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:752
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:752
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:753
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:753
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:754
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:754
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:755
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:755
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:756
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:756
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:757
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:757
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:758
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:758
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:759
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:759
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:760
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:761
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"output" in: sky130A_mr.drc:762
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:763
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:764
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"with_angle" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:765
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+"ongrid" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.000s Memory: 530.00M
+"output" in: sky130A_mr.drc:766
+ Edge pairs: 0 (flat) 0 (hierarchical)
+ Elapsed: 0.010s Memory: 530.00M
+Writing report database: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_offgrid_check.xml ..
+Total elapsed: 1.450s Memory: 529.00M
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_offgrid_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_offgrid_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_offgrid_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
new file mode 100644
index 0000000..235a7ab
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
@@ -0,0 +1,29 @@
+Running pin_label_purposes_overlapping_drawing.rb.drc on file=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper, output to /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
+ deep:true tiled:false threads:12
+--- #err|description, table for cell: user_analog_project_wrapper
+NO-Check ---- pwell:64/44/EMP 122/16/EMP 64/59/EMP 44/16/EMP 44/5/EMP
+ ---- nwell:64/20/dat 64/16/EMP 64/5/EMP
+ ---- diff:65/20/dat 65/16/EMP 65/6/EMP
+ ---- tap:65/44/dat 65/48/EMP 65/5/EMP
+ ---- poly:66/20/dat 66/16/EMP 66/5/EMP
+ ---- licon1:66/44/dat 66/58/EMP
+ ---- li1:67/20/dat 67/16/EMP 67/5/EMP
+ ---- mcon:67/44/dat 67/48/EMP
+ ---- met1:68/20/dat 68/16/EMP 68/5/EMP
+ ---- via:68/44/dat 68/58/EMP
+ ---- met2:69/20/dat 69/16/dat 69/5/EMP
+ ---- via2:69/44/dat 69/58/EMP
+ ---- met3:70/20/dat 70/16/dat 70/5/EMP
+ ---- via3:70/44/dat 70/48/EMP
+ ---- met4:71/20/dat 71/16/dat 71/5/EMP
+ ---- via4:71/44/dat 71/48/EMP
+ ---- met5:72/20/dat 72/16/dat 72/5/EMP
+ ---- pad:76/20/EMP 76/5/EMP 76/16/EMP
+ ---- pnp:82/44/EMP 82/59/EMP
+ ---- npn:82/20/EMP 82/5/EMP
+ ---- rdl:74/20/EMP 74/16/EMP 74/5/EMP
+ ---- inductor:82/24/EMP 82/25/EMP
+ 0 total error(s) among 0 error type(s), 33 checks, cell: user_analog_project_wrapper
+Writing report...
+VmPeak: 2305100 kB
+VmHWM: 259088 kB
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_pin_label_purposes_overlapping_drawing_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_zeroarea_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_zeroarea_check.log
new file mode 100644
index 0000000..4ba8df7
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_zeroarea_check.log
@@ -0,0 +1,4 @@
+0 zero-area shapes
+writing to /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_no_zero_areas.gds
+VmPeak: 541956 kB
+VmHWM: 262080 kB
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/klayout_zeroarea_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_zeroarea_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/klayout_zeroarea_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/magic_drc_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/magic_drc_check.log
new file mode 100644
index 0000000..e46cc42
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/magic_drc_check.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Could not find file '/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tech' in any of these directories:
+ . $CAD_ROOT/magic/sys $CAD_ROOT/magic/sys/current
+Error parsing "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc": couldn't read file "/usr/local/share/pdk/sky130A/sky130A/libs.tech/magic/sky130A.tcl": no such file or directory
+Bad local startup file "/home/krishna/mpw_precheck/checks/tech-files/sky130A.magicrc", continuing without.
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading "/home/krishna/mpw_precheck/checks/drc_checks/magic/magic_drc_check.tcl" from command line.
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+[INFO]: Loading user_analog_project_wrapper
+
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+"drc(full)" is not one of the DRC styles Magic knows.
+The current style is "default".
+The DRC styles are: default.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.drc.report)
+[INFO]: Saving mag view with DRC errors(/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/magic_drc_check.total b/precheck_results/18_MAR_2022___11_45_48/logs/magic_drc_check.total
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/magic_drc_check.total
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/pdks.info b/precheck_results/18_MAR_2022___11_45_48/logs/pdks.info
new file mode 100644
index 0000000..3072015
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/pdks.info
@@ -0,0 +1,2 @@
+Open PDKs a3d6ffea8022332b859daa454cef7ee7131c5181
+Skywater PDK f70d8ca46961ff92719d8870a18a076370b85f6c
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/precheck.log b/precheck_results/18_MAR_2022___11_45_48/logs/precheck.log
new file mode 100644
index 0000000..a388a8a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/precheck.log
@@ -0,0 +1,61 @@
+2022-03-18 11:45:48 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: /home/krishna/Z_submit
+2022-03-18 11:45:48 - [INFO] - {{Project Type Info}} analog
+2022-03-18 11:45:48 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 4a44d55b7e75babda3cf15c027ff7cf2441ccf99
+2022-03-18 11:45:48 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
+2022-03-18 11:45:48 - [INFO] - {{PDKs Info}} Open PDKs: a3d6ffea8022332b859daa454cef7ee7131c5181 | Skywater PDK: f70d8ca46961ff92719d8870a18a076370b85f6c
+2022-03-18 11:45:48 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/logs'
+2022-03-18 11:45:48 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
+2022-03-18 11:45:48 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
+2022-03-18 11:45:49 - [INFO] - An approved LICENSE (Apache-2.0) was found in /home/krishna/Z_submit.
+2022-03-18 11:45:49 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
+2022-03-18 11:45:49 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
+2022-03-18 11:45:49 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (/home/krishna/Z_submit/mag/myinv_layout2/PLS_INV1.raw): 'utf-8' codec can't decode byte 0x84 in position 990: invalid start byte
+2022-03-18 11:45:49 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in /home/krishna/Z_submit/openlane/Makefile
+2022-03-18 11:45:49 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 157 non-compliant file(s) with the SPDX Standard.
+2022-03-18 11:45:49 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/krishna/Z_submit/Makefile', '/home/krishna/Z_submit/verilog/dv/Makefile', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por.c', '/home/krishna/Z_submit/verilog/dv/mprj_por/mprj_por_tb.v', '/home/krishna/Z_submit/verilog/dv/mprj_por/Makefile', '/home/krishna/Z_submit/verilog/rtl/uprj_analog_netlists.v', '/home/krishna/Z_submit/verilog/rtl/example_por.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_proj_example.v', '/home/krishna/Z_submit/verilog/rtl/user_analog_project_wrapper.v', '/home/krishna/Z_submit/verilog/rtl/comparator.v', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/outputs/reports/magic_drc_check.drc.report', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_zeroarea_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/tools.info', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_beol_check.total', '/home/krishna/Z_submit/precheck_results/18_MAR_2022___05_10_50/logs/klayout_pin_label_purposes_overlapping_drawing_check.total']
+2022-03-18 11:45:49 - [INFO] - For the full SPDX compliance report check: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/logs/spdx_compliance_report.log
+2022-03-18 11:45:49 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
+2022-03-18 11:45:49 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
+2022-03-18 11:45:49 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
+2022-03-18 11:45:49 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
+2022-03-18 11:45:49 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
+2022-03-18 11:45:49 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
+2022-03-18 11:45:49 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
+2022-03-18 11:45:49 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
+2022-03-18 11:45:51 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
+2022-03-18 11:45:51 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
+2022-03-18 11:45:51 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
+2022-03-18 11:45:51 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
+2022-03-18 11:45:51 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
+2022-03-18 11:45:51 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
+2022-03-18 11:45:51 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (11 instances).
+2022-03-18 11:45:51 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
+2022-03-18 11:45:51 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
+2022-03-18 11:45:51 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
+2022-03-18 11:45:51 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
+2022-03-18 11:45:51 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
+2022-03-18 11:45:52 - [ERROR] - XOR CHECK FILE NOT FOUND in /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/logs/xor_check.total
+2022-03-18 11:45:52 - [WARNING] - {{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
+2022-03-18 11:45:52 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
+2022-03-18 11:45:52 - [INFO] - 0 DRC violations
+2022-03-18 11:45:52 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:45:52 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
+2022-03-18 11:45:54 - [INFO] - No DRC Violations found
+2022-03-18 11:45:54 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:45:54 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
+2022-03-18 11:45:59 - [INFO] - No DRC Violations found
+2022-03-18 11:45:59 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:45:59 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
+2022-03-18 11:46:01 - [INFO] - No DRC Violations found
+2022-03-18 11:46:01 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:46:01 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
+2022-03-18 11:46:02 - [INFO] - No DRC Violations found
+2022-03-18 11:46:02 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:46:02 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
+2022-03-18 11:46:03 - [INFO] - No DRC Violations found
+2022-03-18 11:46:03 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:46:03 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
+2022-03-18 11:46:04 - [INFO] - No DRC Violations found
+2022-03-18 11:46:04 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
+2022-03-18 11:46:04 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/logs'
+2022-03-18 11:46:04 - [CRITICAL] - {{FAILURE}} 1 Check(s) Failed: ['XOR'] !!!
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/spdx_compliance_report.log b/precheck_results/18_MAR_2022___11_45_48/logs/spdx_compliance_report.log
new file mode 100644
index 0000000..7268be9
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/spdx_compliance_report.log
@@ -0,0 +1,157 @@
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diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/tools.info b/precheck_results/18_MAR_2022___11_45_48/logs/tools.info
new file mode 100644
index 0000000..9b2230a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/tools.info
@@ -0,0 +1,2 @@
+KLayout: 0.27.8
+Magic: 8.3.274
\ No newline at end of file
diff --git a/precheck_results/18_MAR_2022___11_45_48/logs/xor_check.log b/precheck_results/18_MAR_2022___11_45_48/logs/xor_check.log
new file mode 100644
index 0000000..c797269
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/logs/xor_check.log
@@ -0,0 +1,179 @@
+Reading file /home/krishna/Z_submit/gds/user_analog_project_wrapper.gds for cell user_analog_project_wrapper
+dbu=0.001
+cell user_analog_project_wrapper dbu-bbox(ll;ur)=(-4000,-4000;2924000,3524000)
+cell user_analog_project_wrapper dbu-bbox(left,bottom,right,top)=(-4000,-4000,2924000,3524000)
+cell user_analog_project_wrapper dbu-size(width,height)=(2928000,3528000)
+cell user_analog_project_wrapper micron-bbox(left,bottom,right,top)=(-4.0,-4.0,2924.0,3524.0)
+cell user_analog_project_wrapper micron-size(width,height)=(2928.0,3528.0)
+Done.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds.
+File may be incompletely written.
+
+Magic 8.3 revision 274 - Compiled on Fri Mar 4 22:54:15 UTC 2022.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Loading "/home/krishna/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
+"sky130(vendor)" is not one of the CIF input styles Magic knows.
+Error: No style is set
+The CIF input styles are: .
+Don't know how to read GDS-II:
+Nothing in "cifinput" section of tech file.
+File user_analog_project_wrapper.mag couldn't be read
+No such file or directory
+Creating new cell
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 (-43.000, 0.000), ( 0.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( -43, 0 ), ( 0, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 43.000 x 3520.000 ( 2920.000, 0.000), ( 2963.000, 3520.000) 151360.000
+lambda: 43 x 3520 ( 2920, 0 ), ( 2963, 3520 ) 151360
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 38.000 (-43.000, -38.000), ( 2963.000, 0.000) 114228.000
+lambda: 3006 x 38 ( -43, -38 ), ( 2963, 0 ) 114228
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3006.000 x 37.000 (-43.000, 3520.000), ( 2963.000, 3557.000) 111222.000
+lambda: 3006 x 37 ( -43, 3520 ), ( 2963, 3557 ) 111222
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal5
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+Unrecognized layer: metal4
+Layer names are:
+ mag or magnet
+ f or fence
+ r or rotate
+ $
+ *
+ errors
+ labels
+ subcell
+ connect
+No CIF/GDS output style set!
+I/O error in writing file /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_empty_erased.gds.
+File may be incompletely written.
+Reading /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds ..
+ERROR: In /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds in Layout::read
+Total elapsed: 0.000s Memory: 521.00M
+ERROR: 'source': Stream has unknown format: /home/krishna/Z_submit/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds in Layout::read in Executable::execute
+ /home/krishna/mpw_precheck/checks/xor_check/xor.rb.drc:15:in `execute'
+ :/built-in-macros/drc_interpreters.lym:27:in `instance_eval'
+ :/built-in-macros/drc_interpreters.lym:27:in `execute'
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_beol_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_beol_check.xml
new file mode 100644
index 0000000..12e54e4
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_beol_check.xml
@@ -0,0 +1,447 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li.1</name>
+ <description>li.1 : min. li width : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.3</name>
+ <description>li.3 : min. li spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.5</name>
+ <description>li.5 : min. li enclosure of licon of 2 adjacent edges : 0.08um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li.6</name>
+ <description>li.6 : min. li area : 0.0561um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1</name>
+ <description>ct.1: non-ring mcon should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_a</name>
+ <description>ct.1_a : minimum width of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.1_b</name>
+ <description>ct.1_b : maximum length of mcon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.2</name>
+ <description>ct.2 : min. mcon spacing : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct.4</name>
+ <description>ct.4 : mcon should covered by li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.1</name>
+ <description>m1.1 : min. m1 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.2</name>
+ <description>m1.2 : min. m1 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.3ab</name>
+ <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>791_m1.4</name>
+ <description>791_m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4</name>
+ <description>m1.4 : mcon periphery must be enclosed by m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a</name>
+ <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.4a_a</name>
+ <description>m1.4a_a : mcon periph must be enclosed by met1 for specific cells</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.6</name>
+ <description>m1.6 : min. m1 area : 0.083um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.7</name>
+ <description>m1.7 : min. m1 with holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.5</name>
+ <description>m1.5 : min. m1 enclosure of mcon of 2 adjacent edges : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a</name>
+ <description>via.1a : via outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_a</name>
+ <description>via.1a_a : min. width of via outside of moduleCut : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.1a_b</name>
+ <description>via.1a_b : maximum length of via : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.2</name>
+ <description>via.2 : min. via spacing : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a</name>
+ <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.4a_a</name>
+ <description>via.4a_a : 0.15um via must be enclosed by met1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via.5a</name>
+ <description>via.5a : min. m1 enclosure of 0.15um via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.1</name>
+ <description>m2.1 : min. m2 width : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.2</name>
+ <description>m2.2 : min. m2 spacing : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.3ab</name>
+ <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.6</name>
+ <description>m2.6 : min. m2 area : 0.0676um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.7</name>
+ <description>m2.7 : min. m2 holes area : 0.14um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4</name>
+ <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.4_a</name>
+ <description>m2.4_a : via in periphery must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.5</name>
+ <description>m2.5 : min. m2 enclosure of via of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a</name>
+ <description>via2.1a : via2 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_a</name>
+ <description>via2.1a_a : min. width of via2 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.1a_b</name>
+ <description>via2.1a_b : maximum length of via2 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.2</name>
+ <description>via2.2 : min. via2 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4</name>
+ <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.4_a</name>
+ <description>via2.4_a : via must be enclosed by met2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2.5</name>
+ <description>via2.5 : min. m3 enclosure of via2 of 2 adjacent edges : 0.085um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.1</name>
+ <description>m3.1 : min. m3 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.2</name>
+ <description>m3.2 : min. m3 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.3cd</name>
+ <description>m3.3cd : min. 3um.m3 spacing m3 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4</name>
+ <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.4_a</name>
+ <description>m3.4_a : via2 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1</name>
+ <description>via3.1 : via3 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_a</name>
+ <description>via3.1_a : min. width of via3 outside of moduleCut : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.1_b</name>
+ <description>via3.1_b : maximum length of via3 : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.2</name>
+ <description>via3.2 : min. via3 spacing : 0.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4</name>
+ <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.4_a</name>
+ <description>via3.4_a : non-ring via3 must be enclosed by met3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3.5</name>
+ <description>via3.5 : min. m3 enclosure of via3 of 2 adjacent edges : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.1</name>
+ <description>m4.1 : min. m4 width : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.2</name>
+ <description>m4.2 : min. m4 spacing : 0.3um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.4a</name>
+ <description>m4.4a : min. m4 area : 0.240um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.5ab</name>
+ <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3</name>
+ <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.3_a</name>
+ <description>m4.3_a : via3 must be enclosed by met4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1</name>
+ <description>via4.1 : via4 outside of moduleCut should be rectangular</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_a</name>
+ <description>via4.1_a : min. width of via4 outside of moduleCut : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.1_b</name>
+ <description>via4.1_b : maximum length of via4 : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.2</name>
+ <description>via4.2 : min. via4 spacing : 0.8um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4</name>
+ <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4.4_a</name>
+ <description>via4.4_a : m4 must enclose all via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.1</name>
+ <description>m5.1 : min. m5 width : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.2</name>
+ <description>m5.2 : min. m5 spacing : 1.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3</name>
+ <description>m5.3 : min. m5 enclosure of via4 : 0.31um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.3_a</name>
+ <description>m5.3_a : via must be enclosed by m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.4</name>
+ <description>m5.4 : min. m5 area : 4.0um²</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad.2</name>
+ <description>pad.2 : min. pad spacing : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_feol_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_feol_check.xml
new file mode 100644
index 0000000..d0ecd3f
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_feol_check.xml
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.6</name>
+ <description>nwell.6 : min enclosure of nwellHole by dnwell : 1.03um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2_a</name>
+ <description>hvtr.2_a : hvtr must not overlap hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.1a</name>
+ <description>lvtn.1a : min. lvtn width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.2a</name>
+ <description>ncm.2a : min. ncm spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. diff width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_a</name>
+ <description>difftap.1_a : min. diff width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_b</name>
+ <description>difftap.1_b : min. tap width across areaid:ce : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1_c</name>
+ <description>difftap.1_c : min. tap width in periphery : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.1a</name>
+ <description>urpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>urpm.2</name>
+ <description>urpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be manually merged if less than : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.1</name>
+ <description>nsd.1 : min. nsdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsd.2</name>
+ <description>nsd.2 : min. nsdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.1</name>
+ <description>psd.1 : min. psdm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psd.2</name>
+ <description>psd.2 : min. psdm spacing, should be manually merged if less than : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : licon should be rectangle</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1_a/b</name>
+ <description>licon.1_a/b : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13_a</name>
+ <description>licon.13_a : licon of diffTap in periphery must not overlap npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : Licons may not overlap both poly and (diff or tap)</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b_a</name>
+ <description>capm.2b_a : min. spacing of m3_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. capm and m3 enclosure of m3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3_a</name>
+ <description>capm.3_a : min. m3 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via3 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.1</name>
+ <description>cap2m.1 : min. cap2m width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2a</name>
+ <description>cap2m.2a : min. cap2m spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b</name>
+ <description>cap2m.2b : min. cap2m spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.2b_a</name>
+ <description>cap2m.2b_a : min. spacing of m4_bot_plate : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3</name>
+ <description>cap2m.3 : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.3_a</name>
+ <description>cap2m.3_a : min. m4 enclosure of cap2m : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.4</name>
+ <description>cap2m.4 : min. cap2m enclosure of via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>cap2m.5</name>
+ <description>cap2m.5 : min. cap2m spacing to via4 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.2a</name>
+ <description>hvi.2a : min. hvi spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_met_min_ca_density_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_met_min_ca_density_check.xml
new file mode 100644
index 0000000..cdcd318
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_met_min_ca_density_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/met_min_ca_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_offgrid_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_offgrid_check.xml
new file mode 100644
index 0000000..b69c1b3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
new file mode 100644
index 0000000..cc456f5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>pin_label_purposes_overlapping_drawing.rb.drc, input=/home/krishna/Z_submit/gds/user_analog_project_wrapper.gds, topcell=user_analog_project_wrapper</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_zeroarea_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_zeroarea_check.xml
new file mode 100644
index 0000000..885685a
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/klayout_zeroarea_check.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>zero area check</description>
+ <original-file/>
+ <generator>drc: script='/home/krishna/mpw_precheck/checks/drc_checks/klayout/zeroarea.rb.drc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.drc.report b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.drc.report
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.drc.report
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.rdb b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.rdb
new file mode 100644
index 0000000..8a882f3
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.rdb
@@ -0,0 +1,2 @@
+$user_analog_project_wrapper
+ 100
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.tcl b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.tcl
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.tr b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.tr
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.xml b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.xml
new file mode 100644
index 0000000..7161d7c
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/reports/magic_drc_check.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper.magic.drc.mag b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..bc7865b
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,7 @@
+magic
+tech minimum
+magscale 1 2
+timestamp 0
+<< checkpaint >>
+rect 0 0 1 1
+<< end >>
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_empty_erased.gds b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_empty_erased.gds
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_erased.gds
diff --git a/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_no_zero_areas.gds b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_no_zero_areas.gds
new file mode 100644
index 0000000..40de98e
--- /dev/null
+++ b/precheck_results/18_MAR_2022___11_45_48/outputs/user_analog_project_wrapper_no_zero_areas.gds
Binary files differ
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
new file mode 100644
index 0000000..a9c2027
--- /dev/null
+++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = mprj_por
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% :
+ cd $* && make
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+ rm -rf *.log
+
+.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..6be9cd3
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,131 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
+# Simulation Environment Setup
+
+There are two options for setting up the simulation environment:
+
+* Pulling a pre-built docker image
+* Installing the dependecies locally
+
+## 1. Docker
+
+There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup)
+
+Run the following to pull the image:
+
+```
+docker pull efabless/dv_setup:latest
+```
+
+## 2. Local Installion (Linux)
+
+You will need to fullfil these dependecies:
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain,
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following:
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+ libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+ gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+## Docker
+
+First, you will need to export a number of environment variables:
+
+```bash
+export PDK_PATH=<pdk-location/sky130A>
+export CARAVEL_ROOT=<caravel_root>
+export UPRJ_ROOT=<user_project_root>
+```
+
+Then, run the following command to start the docker container :
+
+```
+docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+```
+
+Then, navigate to the directory where the DV tests reside :
+
+```bash
+cd $UPRJ_ROOT/verilog/dv/
+```
+
+Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
+
+## Local
+
+You will need to export these environment variables:
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
+
+## Both
+
+To run RTL simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+make
+```
+
+To run gate level simulation for one of the DV tests,
+
+```bash
+cd <dv-test>
+SIM=GL make
+```
+
+# User Analog Project Example DV
+
+> :construction: Under construction :construction:
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile
new file mode 100644
index 0000000..5d0825f
--- /dev/null
+++ b/verilog/dv/mprj_por/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## PDK
+PDK_PATH = $(PDK_ROOT)/sky130A
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+
+## Simulation mode: RTL/GL
+SIM_DEFINES = -DFUNCTIONAL -DSIM
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = mprj_por
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+check-env:
+ifndef PDK_ROOT
+ $(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+ $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+ $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/mprj_por/mprj_por.c b/verilog/dv/mprj_por/mprj_por.c
new file mode 100644
index 0000000..9a51fc5
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por.c
@@ -0,0 +1,49 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+
+// --------------------------------------------------------
+
+void main()
+{
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+
+ reg_mprj_datal = 0x00000000;
+ reg_mprj_datah = 0x00000000;
+
+ // Configure mprj_io 10 and 25 as analog (digital in/out = off)
+ // Configure mprj_io 11, 12, 26, and 27 as digital output
+ // mprj_io 14 to 24 are analog pads and cannot be configured
+
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_ANALOG;
+
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_ANALOG;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ /* Block until end of test */
+ while (1);
+}
+
diff --git a/verilog/dv/mprj_por/mprj_por_tb.v b/verilog/dv/mprj_por/mprj_por_tb.v
new file mode 100644
index 0000000..39e4a36
--- /dev/null
+++ b/verilog/dv/mprj_por/mprj_por_tb.v
@@ -0,0 +1,170 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_analog_netlists.v"
+`include "caravan_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module mprj_por_tb;
+ // Signals declaration
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3;
+
+ wire HIGH;
+ wire LOW;
+ wire TRI;
+ assign HIGH = 1'b1;
+ assign LOW = 1'b0;
+ assign TRI = 1'bz;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [3:0] checkbits;
+ wire [1:0] status;
+
+ // Signals Assignment
+ assign uart_tx = mprj_io[6];
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Power supply for POR
+ assign mprj_io[18] = power3;
+
+ // Readback from POR (digital HV through analog pad connection)
+ assign status = {mprj_io[25], mprj_io[10]};
+
+ // Readback from POR (digital LV)
+ assign checkbits = {mprj_io[27:26], mprj_io[12:11]};
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("mprj_por.vcd");
+ $dumpvars(0, mprj_por_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (150) begin
+ repeat (1000) @(posedge clock);
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(status == 2'h1);
+ $display("Monitor: mprj_por test started");
+ #100;
+ if (checkbits != 4'h9) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ wait(status == 2'h3);
+ #100;
+ if (checkbits != 4'h5) begin
+ $display("Monitor: mprj_por test failed");
+ $finish;
+ end
+ $display("Monitor: mprj_por test Passed");
+ #10000;
+ $finish;
+ end
+
+ // Reset Operation
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #150000; // Need time to run the managment SoC setup.
+ power3 <= 1'b1; // Power up the 2nd POR.
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire VSS = 1'b0;
+
+ caravan uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+
+ spiflash #(
+ .FILENAME("mprj_por.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/comparator.v b/verilog/rtl/comparator.v
new file mode 100644
index 0000000..9d691b6
--- /dev/null
+++ b/verilog/rtl/comparator.v
@@ -0,0 +1,37 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module comparator(
+`ifdef USE_POWER_PINS
+ inout VDD,
+ inout GND,
+`endif
+ input Vn,
+ input Vp,
+ input CLK,
+ input CLKBAR,
+ output Outn,
+ output Outp
+);
+
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v
new file mode 100644
index 0000000..d318fba
--- /dev/null
+++ b/verilog/rtl/example_por.v
@@ -0,0 +1,95 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+`timescale 1 ns / 1 ps
+
+// This is just a copy of simple_por.v from the Caravel project, used
+// as an analog user project example.
+
+module example_por(
+`ifdef USE_POWER_PINS
+ inout vdd3v3,
+ inout vdd1v8,
+ inout vss,
+`endif
+ output porb_h,
+ output porb_l,
+ output por_l
+);
+
+ wire mid, porb_h;
+ reg inode;
+
+ // This is a behavioral model! Actual circuit is a resitor dumping
+ // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+ // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+ initial begin
+ inode <= 1'b0;
+ end
+
+ // Emulate current source on capacitor as a 500ns delay either up or
+ // down. Note that this is sped way up for verilog simulation; the
+ // actual circuit is set to a 15ms delay.
+
+ always @(posedge vdd3v3) begin
+ #500 inode <= 1'b1;
+ end
+ always @(negedge vdd3v3) begin
+ #500 inode <= 1'b0;
+ end
+
+ // Instantiate two shmitt trigger buffers in series
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(inode),
+ .X(mid)
+ );
+
+ sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VGND(vss),
+ .VPB(vdd3v3),
+ .VNB(vss),
+`endif
+ .A(mid),
+ .X(porb_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
+`ifdef USE_POWER_PINS
+ .VPWR(vdd3v3),
+ .VPB(vdd3v3),
+ .LVPWR(vdd1v8),
+ .VNB(vss),
+ .VGND(vss),
+`endif
+ .A(porb_h),
+ .X(porb_l)
+ );
+
+ // since this is behavioral anyway, but this should be
+ // replaced by a proper inverter
+ assign por_l = ~porb_l;
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/uprj_analog_netlists.v
new file mode 100644
index 0000000..062a873
--- /dev/null
+++ b/verilog/rtl/uprj_analog_netlists.v
@@ -0,0 +1,38 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ `default_nettype wire
+ // Use behavorial model with gate-level simulation
+ `include "rtl/user_analog_project_wrapper.v"
+ `include "rtl/user_analog_proj_example.v"
+`else
+ `include "user_analog_project_wrapper.v"
+ `include "user_analog_proj_example.v"
+`endif
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
new file mode 100644
index 0000000..9ee51f0
--- /dev/null
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -0,0 +1,190 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`include "comparator.v"
+
+
+/*
+ * I/O mapping for analog
+ *
+ * mprj_io[37] io_in/out/oeb/in_3v3[26] --- ---
+ * mprj_io[36] io_in/out/oeb/in_3v3[25] --- ---
+ * mprj_io[35] io_in/out/oeb/in_3v3[24] gpio_analog/noesd[17] ---
+ * mprj_io[34] io_in/out/oeb/in_3v3[23] gpio_analog/noesd[16] ---
+ * mprj_io[33] io_in/out/oeb/in_3v3[22] gpio_analog/noesd[15] ---
+ * mprj_io[32] io_in/out/oeb/in_3v3[21] gpio_analog/noesd[14] ---
+ * mprj_io[31] io_in/out/oeb/in_3v3[20] gpio_analog/noesd[13] ---
+ * mprj_io[30] io_in/out/oeb/in_3v3[19] gpio_analog/noesd[12] ---
+ * mprj_io[29] io_in/out/oeb/in_3v3[18] gpio_analog/noesd[11] ---
+ * mprj_io[28] io_in/out/oeb/in_3v3[17] gpio_analog/noesd[10] ---
+ * mprj_io[27] io_in/out/oeb/in_3v3[16] gpio_analog/noesd[9] ---
+ * mprj_io[26] io_in/out/oeb/in_3v3[15] gpio_analog/noesd[8] ---
+ * mprj_io[25] io_in/out/oeb/in_3v3[14] gpio_analog/noesd[7] ---
+ * mprj_io[24] --- --- user_analog[10]
+ * mprj_io[23] --- --- user_analog[9]
+ * mprj_io[22] --- --- user_analog[8]
+ * mprj_io[21] --- --- user_analog[7]
+ * mprj_io[20] --- --- user_analog[6] clamp[2]
+ * mprj_io[19] --- --- user_analog[5] clamp[1]
+ * mprj_io[18] --- --- user_analog[4] clamp[0]
+ * mprj_io[17] --- --- user_analog[3]
+ * mprj_io[16] --- --- user_analog[2]
+ * mprj_io[15] --- --- user_analog[1]
+ * mprj_io[14] --- --- user_analog[0]
+ * mprj_io[13] io_in/out/oeb/in_3v3[13] gpio_analog/noesd[6] ---
+ * mprj_io[12] io_in/out/oeb/in_3v3[12] gpio_analog/noesd[5] ---
+ * mprj_io[11] io_in/out/oeb/in_3v3[11] gpio_analog/noesd[4] ---
+ * mprj_io[10] io_in/out/oeb/in_3v3[10] gpio_analog/noesd[3] ---
+ * mprj_io[9] io_in/out/oeb/in_3v3[9] gpio_analog/noesd[2] ---
+ * mprj_io[8] io_in/out/oeb/in_3v3[8] gpio_analog/noesd[1] ---
+ * mprj_io[7] io_in/out/oeb/in_3v3[7] gpio_analog/noesd[0] ---
+ * mprj_io[6] io_in/out/oeb/in_3v3[6] --- ---
+ * mprj_io[5] io_in/out/oeb/in_3v3[5] --- ---
+ * mprj_io[4] io_in/out/oeb/in_3v3[4] --- ---
+ * mprj_io[3] io_in/out/oeb/in_3v3[3] --- ---
+ * mprj_io[2] io_in/out/oeb/in_3v3[2] --- ---
+ * mprj_io[1] io_in/out/oeb/in_3v3[1] --- ---
+ * mprj_io[0] io_in/out/oeb/in_3v3[0] --- ---
+ *
+ */
+
+/*
+ *----------------------------------------------------------------
+ *
+ * user_analog_proj_example
+ *
+ * This is an example of a (trivially simple) analog user project,
+ * showing how the user project can connect to the I/O pads, both
+ * the digital pads, the analog connection on the digital pads,
+ * and the dedicated analog pins used as an additional power supply
+ * input, with a connected ESD clamp.
+ *
+ * See the testbench in directory "mprj_por" for the example
+ * program that drives this user project.
+ *
+ *----------------------------------------------------------------
+ */
+
+module user_analog_proj_example (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ // IOs
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ // GPIO-analog
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ // Dedicated analog
+ inout [`ANALOG_PADS-1:0] io_analog,
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Clock
+ input user_clock2,
+
+ // IRQ
+ output [2:0] irq
+);
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
+ wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
+ wire [`ANALOG_PADS-1:0] io_analog;
+
+ // wire [31:0] rdata;
+ // wire [31:0] wdata;
+
+ // wire valid;
+ // wire [3:0] wstrb;
+ `ifdef USE_POWER_PINS
+
+ assign io_clamp_high[2:1] = vccd1;
+ assign io_clamp_low[2:1] = vssa1;
+ `endif
+ wire analog0, analog2, analog3, ;
+
+ // WB MI A
+ // assign valid = wbs_cyc_i && wbs_stb_i;
+ // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+ // assign wbs_dat_o = rdata;
+ // assign wdata = wbs_dat_i;
+
+ // IO --- unused (no need to connect to anything)
+ // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
+ // assign io_out[14:13] = 11'b0;
+ // assign io_out[10:0] = 11'b0;
+
+ // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
+ // assign io_oeb[14:13] = 11'b1;
+ // assign io_oeb[10:0] = 11'b1;
+
+ // IO --- enable outputs on 11, 12, 15, and 16
+ assign io_analog[2] = analog2;
+ assign io_analog[3] = analog3;
+ assign io_analog[5] = analog5;
+ assign io_analog[6] = analog6;
+ assign io_analog[7] = analog7;
+ assign io_analog[8] = analog8;
+
+
+ comparator comp1 (
+ `ifdef USE_POWER_PINS
+ .VDD(vccd1),
+ .GND(vssa1),
+ `endif
+ .Vp(analog5), // 3.3V domain output
+ .Vn(analog6), // 1.8V domain output
+ .CLK(analog8),
+ .CLKBAR(analog7),
+ .Outn(analog3),
+ .Outp(analog2) // 1.8V domain output
+ );
+
+
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
new file mode 100644
index 0000000..7ee4c33
--- /dev/null
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+ inout vdda1, // User area 1 3.3V supply
+ inout vdda2, // User area 2 3.3V supply
+ inout vssa1, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V supply
+ inout vccd2, // User area 2 1.8v supply
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+`endif
+
+ // Wishbone Slave ports (WB MI A)
+ input wb_clk_i,
+ input wb_rst_i,
+ input wbs_stb_i,
+ input wbs_cyc_i,
+ input wbs_we_i,
+ input [3:0] wbs_sel_i,
+ input [31:0] wbs_dat_i,
+ input [31:0] wbs_adr_i,
+ output wbs_ack_o,
+ output [31:0] wbs_dat_o,
+
+ // Logic Analyzer Signals
+ input [127:0] la_data_in,
+ output [127:0] la_data_out,
+ input [127:0] la_oenb,
+
+ /* GPIOs. There are 27 GPIOs, on either side of the analog.
+ * These have the following mapping to the GPIO padframe pins
+ * and memory-mapped registers, since the numbering remains the
+ * same as caravel but skips over the analog I/O:
+ *
+ * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25]
+ * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0]
+ *
+ * When the GPIOs are configured by the Management SoC for
+ * user use, they have three basic bidirectional controls:
+ * in, out, and oeb (output enable, sense inverted). For
+ * analog projects, a 3.3V copy of the signal input is
+ * available. out and oeb must be 1.8V signals.
+ */
+
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+ input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+ output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+ /* Analog (direct connection to GPIO pad---not for high voltage or
+ * high frequency use). The management SoC must turn off both
+ * input and output buffers on these GPIOs to allow analog access.
+ * These signals may drive a voltage up to the value of VDDIO
+ * (3.3V typical, 5.5V maximum).
+ *
+ * Note that analog I/O is not available on the 7 lowest-numbered
+ * GPIO pads, and so the analog_io indexing is offset from the
+ * GPIO indexing by 7, as follows:
+ *
+ * gpio_analog/noesd [17:7] <---> mprj_io[35:25]
+ * gpio_analog/noesd [6:0] <---> mprj_io[13:7]
+ *
+ */
+
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+ inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+ /* Analog signals, direct through to pad. These have no ESD at all,
+ * so ESD protection is the responsibility of the designer.
+ *
+ * user_analog[10:0] <---> mprj_io[24:14]
+ *
+ */
+ inout [`ANALOG_PADS-1:0] io_analog,
+
+ /* Additional power supply ESD clamps, one per analog pad. The
+ * high side should be connected to a 3.3-5.5V power supply.
+ * The low side should be connected to ground.
+ *
+ * clamp_high[2:0] <---> mprj_io[20:18]
+ * clamp_low[2:0] <---> mprj_io[20:18]
+ *
+ */
+ inout [2:0] io_clamp_high,
+ inout [2:0] io_clamp_low,
+
+ // Independent clock (on independent integer divider)
+ input user_clock2,
+
+ // User maskable interrupt signals
+ output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated here */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
+ .vdda2(vdda2), // User area 2 3.3V power
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vccd2(vccd2), // User area 2 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ // MGMT SoC Wishbone Slave
+
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer
+
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oenb (la_oenb),
+
+ // IO Pads
+ .io_in (io_in),
+ .io_in_3v3 (io_in_3v3),
+ .io_out(io_out),
+ .io_oeb(io_oeb),
+
+ // GPIO-analog
+ .gpio_analog(gpio_analog),
+ .gpio_noesd(gpio_noesd),
+
+ // Dedicated analog
+ .io_analog(io_analog),
+ .io_clamp_high(vccd1),
+ .io_clamp_low(vssa1),
+
+ // Clock
+ .user_clock2(user_clock2),
+
+ // IRQ
+ .irq(user_irq)
+);
+
+endmodule // user_analog_project_wrapper
+
+`default_nettype wire
diff --git a/xschem/analog_wrapper_tb.sch b/xschem/analog_wrapper_tb.sch
new file mode 100644
index 0000000..564c41e
--- /dev/null
+++ b/xschem/analog_wrapper_tb.sch
@@ -0,0 +1,158 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 800 -820 800 -800 {
+lab=GND}
+N 800 -910 800 -880 {
+lab=VDD}
+N 1010 -710 1010 -690 {
+lab=io_analog[5]}
+N 1010 -790 1010 -770 {
+lab=io_analog[6]}
+N 1010 -690 1100 -690 {
+lab=io_analog[5]}
+N 1100 -690 1100 -670 {
+lab=io_analog[5]}
+N 1100 -610 1100 -590 {
+lab=GND}
+N 1100 -690 1170 -690 {
+lab=io_analog[5]}
+N 1170 -790 1170 -690 {
+lab=io_analog[5]}
+N 910 -1020 910 -990 {
+lab=io_analog[8]}
+N 800 -650 800 -630 {
+lab=GND}
+N 800 -740 800 -710 {
+lab=io_analog[7]}
+N 910 -930 910 -900 {
+lab=GND}
+N 1330 -710 1330 -670 {
+lab=GND}
+N 1330 -810 1330 -770 {
+lab=GND}
+N 1490 -1210 1540 -1210 {
+lab=#net1}
+N 1490 -1190 1540 -1190 {
+lab=#net2}
+N 1490 -1170 1540 -1170 {
+lab=GND}
+N 1490 -1150 1540 -1150 {
+lab=#net3}
+N 1490 -1130 1540 -1130 {
+lab=VDD}
+N 1490 -1110 1540 -1110 {
+lab=#net4}
+N 1490 -1090 1540 -1090 {
+lab=#net5}
+N 1490 -1070 1540 -1070 {
+lab=#net6}
+N 1490 -1050 1540 -1050 {
+lab=#net7}
+N 1490 -1030 1540 -1030 {
+lab=#net8}
+N 1490 -1010 1540 -1010 {
+lab=#net9}
+N 1490 -990 1540 -990 {
+lab=#net10}
+N 1490 -970 1540 -970 {
+lab=#net11}
+N 1490 -950 1540 -950 {
+lab=#net12}
+N 1490 -930 1540 -930 {
+lab=#net13}
+N 1490 -910 1540 -910 {
+lab=io_analog[3]}
+N 1490 -890 1540 -890 {
+lab=#net14}
+N 1490 -870 1540 -870 {
+lab=#net15}
+N 1490 -850 1540 -850 {
+lab=#net16}
+N 1840 -1210 1890 -1210 {
+lab=#net17}
+N 1840 -1190 1890 -1190 {
+lab=#net18}
+N 1840 -1170 1890 -1170 {
+lab=#net19}
+N 1840 -1150 1890 -1150 {
+lab=#net20}
+N 1840 -1130 1890 -1130 {
+lab=#net21}
+N 1840 -1110 1890 -1110 {
+lab=#net22}
+N 1840 -1090 1890 -1090 {
+lab=#net23}
+N 1840 -1070 1890 -1070 {
+lab=#net24}
+N 1840 -1050 1890 -1050 {
+lab=#net25}
+N 1840 -1030 1890 -1030 {
+lab=#net26}
+N 1840 -1010 1890 -1010 {
+lab=#net27}
+N 1840 -990 1890 -990 {
+lab=#net28}
+N 1840 -970 1890 -970 {
+lab=#net29}
+N 2030 -990 2030 -950 {
+lab=GND}
+N 2130 -990 2130 -940 {
+lab=GND}
+N 2030 -1120 2030 -1050 {
+lab=io_analog[3]}
+N 2130 -1120 2130 -1050 {
+lab=io_analog[2]}
+C {devices/TT_models.sym} 950 -1180 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+"
+spice_ignore=falsename=s1 only_toplevel=false value=blabla}
+C {devices/vsource.sym} 800 -850 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} 1010 -740 0 0 {name=Vn value="pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)"}
+C {devices/lab_pin.sym} 1010 -790 0 0 {name=l24 sig_type=std_logic lab=io_analog[6]}
+C {devices/vsource.sym} 1100 -640 0 0 {name=Vcm value=1.2}
+C {devices/lab_pin.sym} 1170 -790 2 0 {name=l25 sig_type=std_logic lab=io_analog[5]}
+C {devices/code_shown.sym} 2030 -770 0 0 {name=SPICE only_toplevel=false value=".tran 0.01n 50n
+.save all"}
+C {devices/vsource.sym} 910 -960 0 0 {name=V1 value="pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 910 -1020 0 0 {name=l22 sig_type=std_logic lab=io_analog[8]}
+C {devices/vsource.sym} 800 -680 0 0 {name=V2 value="pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 800 -740 0 0 {name=l27 sig_type=std_logic lab=io_analog[7]}
+C {devices/gnd.sym} 1330 -670 0 0 {name=l3 lab=GND}
+C {devices/lab_pin.sym} 1330 -810 2 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1100 -590 2 0 {name=l5 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -630 2 0 {name=l6 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -800 2 0 {name=l7 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 910 -900 2 0 {name=l8 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -910 0 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/res.sym} 1330 -740 0 0 {name=R1
+value=0
+footprint=1206
+device=resistor
+m=1}
+C {user_analog_project_wrapper.sym} 1690 -1030 0 1 {name=x1}
+C {devices/lab_pin.sym} 1490 -1130 0 0 {name=l1 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1490 -1170 0 0 {name=l2 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2030 -1120 1 0 {name=l12 sig_type=std_logic lab=io_analog[3]}
+C {devices/lab_pin.sym} 2130 -1120 1 0 {name=l13 sig_type=std_logic lab=io_analog[2]}
+C {devices/capa.sym} 2030 -1020 0 0 {name=C1
+m=1
+value=0.1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/capa.sym} 2130 -1020 0 0 {name=C2
+m=1
+value=0.1p
+footprint=1206
+device="ceramic capacitor"}
+C {devices/lab_pin.sym} 2030 -950 0 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2130 -940 0 0 {name=l11 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1490 -910 0 0 {name=l14 sig_type=std_logic lab=io_analog[10:0]}
diff --git a/xschem/analog_wrapper_tb.spice b/xschem/analog_wrapper_tb.spice
new file mode 100644
index 0000000..98c451e
--- /dev/null
+++ b/xschem/analog_wrapper_tb.spice
@@ -0,0 +1,406 @@
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/analog_wrapper_tb.sch
+**.subckt analog_wrapper_tb
+Vdd VDD GND 1.8
+Vn io_analog[6] io_analog[5] pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm io_analog[5] GND 1.2
+V1 io_analog[8] GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+V2 io_analog[7] GND pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)
+R1 GND GND 0 m=1
+x1 net1 net2 GND net3 VDD net4 net5 net6 net17 net18 net19 net20 net21 net22[3] net22[2] net22[1]
++ net22[0] net23[31] net23[30] net23[29] net23[28] net23[27] net23[26] net23[25] net23[24] net23[23] net23[22]
++ net23[21] net23[20] net23[19] net23[18] net23[17] net23[16] net23[15] net23[14] net23[13] net23[12] net23[11]
++ net23[10] net23[9] net23[8] net23[7] net23[6] net23[5] net23[4] net23[3] net23[2] net23[1] net23[0] net24[31]
++ net24[30] net24[29] net24[28] net24[27] net24[26] net24[25] net24[24] net24[23] net24[22] net24[21] net24[20]
++ net24[19] net24[18] net24[17] net24[16] net24[15] net24[14] net24[13] net24[12] net24[11] net24[10] net24[9]
++ net24[8] net24[7] net24[6] net24[5] net24[4] net24[3] net24[2] net24[1] net24[0] net7 net8[31] net8[30]
++ net8[29] net8[28] net8[27] net8[26] net8[25] net8[24] net8[23] net8[22] net8[21] net8[20] net8[19] net8[18]
++ net8[17] net8[16] net8[15] net8[14] net8[13] net8[12] net8[11] net8[10] net8[9] net8[8] net8[7] net8[6]
++ net8[5] net8[4] net8[3] net8[2] net8[1] net8[0] net25[127] net25[126] net25[125] net25[124] net25[123]
++ net25[122] net25[121] net25[120] net25[119] net25[118] net25[117] net25[116] net25[115] net25[114] net25[113]
++ net25[112] net25[111] net25[110] net25[109] net25[108] net25[107] net25[106] net25[105] net25[104] net25[103]
++ net25[102] net25[101] net25[100] net25[99] net25[98] net25[97] net25[96] net25[95] net25[94] net25[93]
++ net25[92] net25[91] net25[90] net25[89] net25[88] net25[87] net25[86] net25[85] net25[84] net25[83] net25[82]
++ net25[81] net25[80] net25[79] net25[78] net25[77] net25[76] net25[75] net25[74] net25[73] net25[72] net25[71]
++ net25[70] net25[69] net25[68] net25[67] net25[66] net25[65] net25[64] net25[63] net25[62] net25[61] net25[60]
++ net25[59] net25[58] net25[57] net25[56] net25[55] net25[54] net25[53] net25[52] net25[51] net25[50] net25[49]
++ net25[48] net25[47] net25[46] net25[45] net25[44] net25[43] net25[42] net25[41] net25[40] net25[39] net25[38]
++ net25[37] net25[36] net25[35] net25[34] net25[33] net25[32] net25[31] net25[30] net25[29] net25[28] net25[27]
++ net25[26] net25[25] net25[24] net25[23] net25[22] net25[21] net25[20] net25[19] net25[18] net25[17] net25[16]
++ net25[15] net25[14] net25[13] net25[12] net25[11] net25[10] net25[9] net25[8] net25[7] net25[6] net25[5]
++ net25[4] net25[3] net25[2] net25[1] net25[0] net9[127] net9[126] net9[125] net9[124] net9[123] net9[122]
++ net9[121] net9[120] net9[119] net9[118] net9[117] net9[116] net9[115] net9[114] net9[113] net9[112] net9[111]
++ net9[110] net9[109] net9[108] net9[107] net9[106] net9[105] net9[104] net9[103] net9[102] net9[101] net9[100]
++ net9[99] net9[98] net9[97] net9[96] net9[95] net9[94] net9[93] net9[92] net9[91] net9[90] net9[89] net9[88]
++ net9[87] net9[86] net9[85] net9[84] net9[83] net9[82] net9[81] net9[80] net9[79] net9[78] net9[77] net9[76]
++ net9[75] net9[74] net9[73] net9[72] net9[71] net9[70] net9[69] net9[68] net9[67] net9[66] net9[65] net9[64]
++ net9[63] net9[62] net9[61] net9[60] net9[59] net9[58] net9[57] net9[56] net9[55] net9[54] net9[53] net9[52]
++ net9[51] net9[50] net9[49] net9[48] net9[47] net9[46] net9[45] net9[44] net9[43] net9[42] net9[41] net9[40]
++ net9[39] net9[38] net9[37] net9[36] net9[35] net9[34] net9[33] net9[32] net9[31] net9[30] net9[29] net9[28]
++ net9[27] net9[26] net9[25] net9[24] net9[23] net9[22] net9[21] net9[20] net9[19] net9[18] net9[17] net9[16]
++ net9[15] net9[14] net9[13] net9[12] net9[11] net9[10] net9[9] net9[8] net9[7] net9[6] net9[5] net9[4]
++ net9[3] net9[2] net9[1] net9[0] net26[127] net26[126] net26[125] net26[124] net26[123] net26[122]
++ net26[121] net26[120] net26[119] net26[118] net26[117] net26[116] net26[115] net26[114] net26[113] net26[112]
++ net26[111] net26[110] net26[109] net26[108] net26[107] net26[106] net26[105] net26[104] net26[103] net26[102]
++ net26[101] net26[100] net26[99] net26[98] net26[97] net26[96] net26[95] net26[94] net26[93] net26[92]
++ net26[91] net26[90] net26[89] net26[88] net26[87] net26[86] net26[85] net26[84] net26[83] net26[82] net26[81]
++ net26[80] net26[79] net26[78] net26[77] net26[76] net26[75] net26[74] net26[73] net26[72] net26[71] net26[70]
++ net26[69] net26[68] net26[67] net26[66] net26[65] net26[64] net26[63] net26[62] net26[61] net26[60] net26[59]
++ net26[58] net26[57] net26[56] net26[55] net26[54] net26[53] net26[52] net26[51] net26[50] net26[49] net26[48]
++ net26[47] net26[46] net26[45] net26[44] net26[43] net26[42] net26[41] net26[40] net26[39] net26[38] net26[37]
++ net26[36] net26[35] net26[34] net26[33] net26[32] net26[31] net26[30] net26[29] net26[28] net26[27] net26[26]
++ net26[25] net26[24] net26[23] net26[22] net26[21] net26[20] net26[19] net26[18] net26[17] net26[16] net26[15]
++ net26[14] net26[13] net26[12] net26[11] net26[10] net26[9] net26[8] net26[7] net26[6] net26[5] net26[4]
++ net26[3] net26[2] net26[1] net26[0] net27[26] net27[25] net27[24] net27[23] net27[22] net27[21] net27[20]
++ net27[19] net27[18] net27[17] net27[16] net27[15] net27[14] net27[13] net27[12] net27[11] net27[10] net27[9]
++ net27[8] net27[7] net27[6] net27[5] net27[4] net27[3] net27[2] net27[1] net27[0] net28[26] net28[25]
++ net28[24] net28[23] net28[22] net28[21] net28[20] net28[19] net28[18] net28[17] net28[16] net28[15] net28[14]
++ net28[13] net28[12] net28[11] net28[10] net28[9] net28[8] net28[7] net28[6] net28[5] net28[4] net28[3]
++ net28[2] net28[1] net28[0] net10[26] net10[25] net10[24] net10[23] net10[22] net10[21] net10[20] net10[19]
++ net10[18] net10[17] net10[16] net10[15] net10[14] net10[13] net10[12] net10[11] net10[10] net10[9] net10[8]
++ net10[7] net10[6] net10[5] net10[4] net10[3] net10[2] net10[1] net10[0] net11[26] net11[25] net11[24]
++ net11[23] net11[22] net11[21] net11[20] net11[19] net11[18] net11[17] net11[16] net11[15] net11[14] net11[13]
++ net11[12] net11[11] net11[10] net11[9] net11[8] net11[7] net11[6] net11[5] net11[4] net11[3] net11[2]
++ net11[1] net11[0] net12[17] net12[16] net12[15] net12[14] net12[13] net12[12] net12[11] net12[10] net12[9]
++ net12[8] net12[7] net12[6] net12[5] net12[4] net12[3] net12[2] net12[1] net12[0] net13[17] net13[16]
++ net13[15] net13[14] net13[13] net13[12] net13[11] net13[10] net13[9] net13[8] net13[7] net13[6] net13[5]
++ net13[4] net13[3] net13[2] net13[1] net13[0] io_analog[10] io_analog[9] io_analog[8] io_analog[7]
++ io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0] net14[2] net14[1]
++ net14[0] net15[2] net15[1] net15[0] net29 net16[2] net16[1] net16[0] user_analog_project_wrapper
+C1 io_analog[3] GND 0.1p m=1
+C2 io_analog[2] GND 0.1p m=1
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+
+
+.tran 0.01n 50n
+.save all
+
+**** end user architecture code
+**.ends
+
+* expanding symbol: user_analog_project_wrapper.sym # of pins=32
+** sym_path: /home/krishna/mycomparator_copy1/prelayout/comparator/user_analog_project_wrapper.sym
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/user_analog_project_wrapper.sch
+.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
++ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3] wbs_sel_i[2] wbs_sel_i[1] wbs_sel_i[0] wbs_dat_i[31]
++ wbs_dat_i[30] wbs_dat_i[29] wbs_dat_i[28] wbs_dat_i[27] wbs_dat_i[26] wbs_dat_i[25] wbs_dat_i[24] wbs_dat_i[23]
++ wbs_dat_i[22] wbs_dat_i[21] wbs_dat_i[20] wbs_dat_i[19] wbs_dat_i[18] wbs_dat_i[17] wbs_dat_i[16] wbs_dat_i[15]
++ wbs_dat_i[14] wbs_dat_i[13] wbs_dat_i[12] wbs_dat_i[11] wbs_dat_i[10] wbs_dat_i[9] wbs_dat_i[8] wbs_dat_i[7]
++ wbs_dat_i[6] wbs_dat_i[5] wbs_dat_i[4] wbs_dat_i[3] wbs_dat_i[2] wbs_dat_i[1] wbs_dat_i[0] wbs_adr_i[31]
++ wbs_adr_i[30] wbs_adr_i[29] wbs_adr_i[28] wbs_adr_i[27] wbs_adr_i[26] wbs_adr_i[25] wbs_adr_i[24] wbs_adr_i[23]
++ wbs_adr_i[22] wbs_adr_i[21] wbs_adr_i[20] wbs_adr_i[19] wbs_adr_i[18] wbs_adr_i[17] wbs_adr_i[16] wbs_adr_i[15]
++ wbs_adr_i[14] wbs_adr_i[13] wbs_adr_i[12] wbs_adr_i[11] wbs_adr_i[10] wbs_adr_i[9] wbs_adr_i[8] wbs_adr_i[7]
++ wbs_adr_i[6] wbs_adr_i[5] wbs_adr_i[4] wbs_adr_i[3] wbs_adr_i[2] wbs_adr_i[1] wbs_adr_i[0] wbs_ack_o
++ wbs_dat_o[31] wbs_dat_o[30] wbs_dat_o[29] wbs_dat_o[28] wbs_dat_o[27] wbs_dat_o[26] wbs_dat_o[25] wbs_dat_o[24]
++ wbs_dat_o[23] wbs_dat_o[22] wbs_dat_o[21] wbs_dat_o[20] wbs_dat_o[19] wbs_dat_o[18] wbs_dat_o[17] wbs_dat_o[16]
++ wbs_dat_o[15] wbs_dat_o[14] wbs_dat_o[13] wbs_dat_o[12] wbs_dat_o[11] wbs_dat_o[10] wbs_dat_o[9] wbs_dat_o[8]
++ wbs_dat_o[7] wbs_dat_o[6] wbs_dat_o[5] wbs_dat_o[4] wbs_dat_o[3] wbs_dat_o[2] wbs_dat_o[1] wbs_dat_o[0]
++ la_data_in[127] la_data_in[126] la_data_in[125] la_data_in[124] la_data_in[123] la_data_in[122] la_data_in[121]
++ la_data_in[120] la_data_in[119] la_data_in[118] la_data_in[117] la_data_in[116] la_data_in[115] la_data_in[114]
++ la_data_in[113] la_data_in[112] la_data_in[111] la_data_in[110] la_data_in[109] la_data_in[108] la_data_in[107]
++ la_data_in[106] la_data_in[105] la_data_in[104] la_data_in[103] la_data_in[102] la_data_in[101] la_data_in[100]
++ la_data_in[99] la_data_in[98] la_data_in[97] la_data_in[96] la_data_in[95] la_data_in[94] la_data_in[93]
++ la_data_in[92] la_data_in[91] la_data_in[90] la_data_in[89] la_data_in[88] la_data_in[87] la_data_in[86]
++ la_data_in[85] la_data_in[84] la_data_in[83] la_data_in[82] la_data_in[81] la_data_in[80] la_data_in[79]
++ la_data_in[78] la_data_in[77] la_data_in[76] la_data_in[75] la_data_in[74] la_data_in[73] la_data_in[72]
++ la_data_in[71] la_data_in[70] la_data_in[69] la_data_in[68] la_data_in[67] la_data_in[66] la_data_in[65]
++ la_data_in[64] la_data_in[63] la_data_in[62] la_data_in[61] la_data_in[60] la_data_in[59] la_data_in[58]
++ la_data_in[57] la_data_in[56] la_data_in[55] la_data_in[54] la_data_in[53] la_data_in[52] la_data_in[51]
++ la_data_in[50] la_data_in[49] la_data_in[48] la_data_in[47] la_data_in[46] la_data_in[45] la_data_in[44]
++ la_data_in[43] la_data_in[42] la_data_in[41] la_data_in[40] la_data_in[39] la_data_in[38] la_data_in[37]
++ la_data_in[36] la_data_in[35] la_data_in[34] la_data_in[33] la_data_in[32] la_data_in[31] la_data_in[30]
++ la_data_in[29] la_data_in[28] la_data_in[27] la_data_in[26] la_data_in[25] la_data_in[24] la_data_in[23]
++ la_data_in[22] la_data_in[21] la_data_in[20] la_data_in[19] la_data_in[18] la_data_in[17] la_data_in[16]
++ la_data_in[15] la_data_in[14] la_data_in[13] la_data_in[12] la_data_in[11] la_data_in[10] la_data_in[9]
++ la_data_in[8] la_data_in[7] la_data_in[6] la_data_in[5] la_data_in[4] la_data_in[3] la_data_in[2] la_data_in[1]
++ la_data_in[0] la_data_out[127] la_data_out[126] la_data_out[125] la_data_out[124] la_data_out[123]
++ la_data_out[122] la_data_out[121] la_data_out[120] la_data_out[119] la_data_out[118] la_data_out[117]
++ la_data_out[116] la_data_out[115] la_data_out[114] la_data_out[113] la_data_out[112] la_data_out[111]
++ la_data_out[110] la_data_out[109] la_data_out[108] la_data_out[107] la_data_out[106] la_data_out[105]
++ la_data_out[104] la_data_out[103] la_data_out[102] la_data_out[101] la_data_out[100] la_data_out[99] la_data_out[98]
++ la_data_out[97] la_data_out[96] la_data_out[95] la_data_out[94] la_data_out[93] la_data_out[92] la_data_out[91]
++ la_data_out[90] la_data_out[89] la_data_out[88] la_data_out[87] la_data_out[86] la_data_out[85] la_data_out[84]
++ la_data_out[83] la_data_out[82] la_data_out[81] la_data_out[80] la_data_out[79] la_data_out[78] la_data_out[77]
++ la_data_out[76] la_data_out[75] la_data_out[74] la_data_out[73] la_data_out[72] la_data_out[71] la_data_out[70]
++ la_data_out[69] la_data_out[68] la_data_out[67] la_data_out[66] la_data_out[65] la_data_out[64] la_data_out[63]
++ la_data_out[62] la_data_out[61] la_data_out[60] la_data_out[59] la_data_out[58] la_data_out[57] la_data_out[56]
++ la_data_out[55] la_data_out[54] la_data_out[53] la_data_out[52] la_data_out[51] la_data_out[50] la_data_out[49]
++ la_data_out[48] la_data_out[47] la_data_out[46] la_data_out[45] la_data_out[44] la_data_out[43] la_data_out[42]
++ la_data_out[41] la_data_out[40] la_data_out[39] la_data_out[38] la_data_out[37] la_data_out[36] la_data_out[35]
++ la_data_out[34] la_data_out[33] la_data_out[32] la_data_out[31] la_data_out[30] la_data_out[29] la_data_out[28]
++ la_data_out[27] la_data_out[26] la_data_out[25] la_data_out[24] la_data_out[23] la_data_out[22] la_data_out[21]
++ la_data_out[20] la_data_out[19] la_data_out[18] la_data_out[17] la_data_out[16] la_data_out[15] la_data_out[14]
++ la_data_out[13] la_data_out[12] la_data_out[11] la_data_out[10] la_data_out[9] la_data_out[8] la_data_out[7]
++ la_data_out[6] la_data_out[5] la_data_out[4] la_data_out[3] la_data_out[2] la_data_out[1] la_data_out[0]
++ la_oenb[127] la_oenb[126] la_oenb[125] la_oenb[124] la_oenb[123] la_oenb[122] la_oenb[121] la_oenb[120]
++ la_oenb[119] la_oenb[118] la_oenb[117] la_oenb[116] la_oenb[115] la_oenb[114] la_oenb[113] la_oenb[112]
++ la_oenb[111] la_oenb[110] la_oenb[109] la_oenb[108] la_oenb[107] la_oenb[106] la_oenb[105] la_oenb[104]
++ la_oenb[103] la_oenb[102] la_oenb[101] la_oenb[100] la_oenb[99] la_oenb[98] la_oenb[97] la_oenb[96] la_oenb[95]
++ la_oenb[94] la_oenb[93] la_oenb[92] la_oenb[91] la_oenb[90] la_oenb[89] la_oenb[88] la_oenb[87] la_oenb[86]
++ la_oenb[85] la_oenb[84] la_oenb[83] la_oenb[82] la_oenb[81] la_oenb[80] la_oenb[79] la_oenb[78] la_oenb[77]
++ la_oenb[76] la_oenb[75] la_oenb[74] la_oenb[73] la_oenb[72] la_oenb[71] la_oenb[70] la_oenb[69] la_oenb[68]
++ la_oenb[67] la_oenb[66] la_oenb[65] la_oenb[64] la_oenb[63] la_oenb[62] la_oenb[61] la_oenb[60] la_oenb[59]
++ la_oenb[58] la_oenb[57] la_oenb[56] la_oenb[55] la_oenb[54] la_oenb[53] la_oenb[52] la_oenb[51] la_oenb[50]
++ la_oenb[49] la_oenb[48] la_oenb[47] la_oenb[46] la_oenb[45] la_oenb[44] la_oenb[43] la_oenb[42] la_oenb[41]
++ la_oenb[40] la_oenb[39] la_oenb[38] la_oenb[37] la_oenb[36] la_oenb[35] la_oenb[34] la_oenb[33] la_oenb[32]
++ la_oenb[31] la_oenb[30] la_oenb[29] la_oenb[28] la_oenb[27] la_oenb[26] la_oenb[25] la_oenb[24] la_oenb[23]
++ la_oenb[22] la_oenb[21] la_oenb[20] la_oenb[19] la_oenb[18] la_oenb[17] la_oenb[16] la_oenb[15] la_oenb[14]
++ la_oenb[13] la_oenb[12] la_oenb[11] la_oenb[10] la_oenb[9] la_oenb[8] la_oenb[7] la_oenb[6] la_oenb[5]
++ la_oenb[4] la_oenb[3] la_oenb[2] la_oenb[1] la_oenb[0] io_in[26] io_in[25] io_in[24] io_in[23] io_in[22]
++ io_in[21] io_in[20] io_in[19] io_in[18] io_in[17] io_in[16] io_in[15] io_in[14] io_in[13] io_in[12] io_in[11]
++ io_in[10] io_in[9] io_in[8] io_in[7] io_in[6] io_in[5] io_in[4] io_in[3] io_in[2] io_in[1] io_in[0]
++ io_in_3v3[26] io_in_3v3[25] io_in_3v3[24] io_in_3v3[23] io_in_3v3[22] io_in_3v3[21] io_in_3v3[20] io_in_3v3[19]
++ io_in_3v3[18] io_in_3v3[17] io_in_3v3[16] io_in_3v3[15] io_in_3v3[14] io_in_3v3[13] io_in_3v3[12] io_in_3v3[11]
++ io_in_3v3[10] io_in_3v3[9] io_in_3v3[8] io_in_3v3[7] io_in_3v3[6] io_in_3v3[5] io_in_3v3[4] io_in_3v3[3]
++ io_in_3v3[2] io_in_3v3[1] io_in_3v3[0] io_out[26] io_out[25] io_out[24] io_out[23] io_out[22] io_out[21]
++ io_out[20] io_out[19] io_out[18] io_out[17] io_out[16] io_out[15] io_out[14] io_out[13] io_out[12] io_out[11]
++ io_out[10] io_out[9] io_out[8] io_out[7] io_out[6] io_out[5] io_out[4] io_out[3] io_out[2] io_out[1] io_out[0]
++ io_oeb[26] io_oeb[25] io_oeb[24] io_oeb[23] io_oeb[22] io_oeb[21] io_oeb[20] io_oeb[19] io_oeb[18] io_oeb[17]
++ io_oeb[16] io_oeb[15] io_oeb[14] io_oeb[13] io_oeb[12] io_oeb[11] io_oeb[10] io_oeb[9] io_oeb[8] io_oeb[7]
++ io_oeb[6] io_oeb[5] io_oeb[4] io_oeb[3] io_oeb[2] io_oeb[1] io_oeb[0] gpio_analog[17] gpio_analog[16]
++ gpio_analog[15] gpio_analog[14] gpio_analog[13] gpio_analog[12] gpio_analog[11] gpio_analog[10] gpio_analog[9]
++ gpio_analog[8] gpio_analog[7] gpio_analog[6] gpio_analog[5] gpio_analog[4] gpio_analog[3] gpio_analog[2]
++ gpio_analog[1] gpio_analog[0] gpio_noesd[17] gpio_noesd[16] gpio_noesd[15] gpio_noesd[14] gpio_noesd[13]
++ gpio_noesd[12] gpio_noesd[11] gpio_noesd[10] gpio_noesd[9] gpio_noesd[8] gpio_noesd[7] gpio_noesd[6] gpio_noesd[5]
++ gpio_noesd[4] gpio_noesd[3] gpio_noesd[2] gpio_noesd[1] gpio_noesd[0] io_analog[10] io_analog[9] io_analog[8]
++ io_analog[7] io_analog[6] io_analog[5] io_analog[4] io_analog[3] io_analog[2] io_analog[1] io_analog[0]
++ io_clamp_high[2] io_clamp_high[1] io_clamp_high[0] io_clamp_low[2] io_clamp_low[1] io_clamp_low[0] user_clock2
++ user_irq[2] user_irq[1] user_irq[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vccd1 vssa1 io_analog[3] io_analog[8] io_analog[5] io_analog[6] io_analog[2] io_analog[7]
++ comparator_schv5
+V0 vssa1 io_clamp_low[1] 0.0
+V1 vssa1 io_clamp_low[2] 0.0
+V2 vccd1 io_clamp_high[2] 0.0
+V3 vccd1 io_clamp_high[1] 0.0
+.ends
+
+
+* expanding symbol: comparator_schv5.sym # of pins=8
+** sym_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sym
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sch
+.subckt comparator_schv5 VDD GND Outn CLK Vp Vn Outp CLKBAR
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+*.iopin CLKBAR
+XM1 net5 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net6 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net2 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net5 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net6 C net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net3 net6 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net5 C net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dn net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 Dp net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net4 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net7 net14 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net8 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net8 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net10 net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net10 net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM32 net11 CLKBAR GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM33 net11 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM34 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM35 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM36 net13 net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM37 net13 net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM38 net14 net13 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM39 net14 net13 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net15 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net15 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net16 net15 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net16 net15 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net17 net16 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net17 net16 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net17 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net17 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net18 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net18 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net19 net18 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net19 net18 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net20 net19 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net20 net19 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net20 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net20 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/comparator.sch b/xschem/comparator.sch
new file mode 100644
index 0000000..b1a4369
--- /dev/null
+++ b/xschem/comparator.sch
@@ -0,0 +1,1727 @@
+v {xschem version=3.0.0 file_version=1.2 }
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+N 3570 -1130 3600 -1130 {
+lab=GND}
+N 3100 -1220 3200 -1220 {
+lab=#net14}
+N 3260 -1220 3360 -1220 {
+lab=#net15}
+N 3420 -1220 3510 -1220 {
+lab=#net16}
+N 3570 -1220 3660 -1220 {
+lab=Outn}
+N 3010 -1220 3040 -1220 {
+lab=n}
+N 3100 -1340 3100 -1310 {
+lab=VDD}
+N 3420 -1340 3570 -1340 {
+lab=VDD}
+N 3570 -1340 3570 -1310 {
+lab=VDD}
+N 3260 -1340 3260 -1310 {
+lab=VDD}
+N 3420 -1340 3420 -1310 {
+lab=VDD}
+N 3100 -1140 3100 -1130 {
+lab=GND}
+N 3260 -1140 3260 -1130 {
+lab=GND}
+N 3420 -1140 3420 -1130 {
+lab=GND}
+N 3570 -1140 3570 -1130 {
+lab=GND}
+N 3100 -1240 3100 -1220 {
+lab=#net14}
+N 3200 -1270 3200 -1220 {
+lab=#net14}
+N 3260 -1240 3260 -1220 {
+lab=#net15}
+N 3360 -1270 3360 -1220 {
+lab=#net15}
+N 3420 -1240 3420 -1220 {
+lab=#net16}
+N 3510 -1270 3510 -1220 {
+lab=#net16}
+N 3570 -1240 3570 -1220 {
+lab=Outn}
+N 3040 -1270 3040 -1220 {
+lab=n}
+N 3100 -1340 3260 -1340 {
+lab=VDD}
+N 3260 -1340 3420 -1340 {
+lab=VDD}
+N 3100 -1120 3570 -1120 {
+lab=GND}
+N 3100 -850 3100 -830 {
+lab=#net17}
+N 3040 -900 3060 -900 {
+lab=p}
+N 3040 -850 3040 -800 {
+lab=p}
+N 3040 -800 3060 -800 {
+lab=p}
+N 3100 -940 3100 -930 {
+lab=VDD}
+N 3100 -900 3130 -900 {
+lab=VDD}
+N 3130 -940 3130 -900 {
+lab=VDD}
+N 3100 -940 3130 -940 {
+lab=VDD}
+N 3100 -760 3100 -750 {
+lab=GND}
+N 3100 -800 3130 -800 {
+lab=GND}
+N 3130 -800 3130 -760 {
+lab=GND}
+N 3100 -760 3130 -760 {
+lab=GND}
+N 3260 -850 3260 -830 {
+lab=#net18}
+N 3200 -900 3220 -900 {
+lab=#net17}
+N 3200 -850 3200 -800 {
+lab=#net17}
+N 3200 -800 3220 -800 {
+lab=#net17}
+N 3260 -940 3260 -930 {
+lab=VDD}
+N 3260 -900 3290 -900 {
+lab=VDD}
+N 3290 -940 3290 -900 {
+lab=VDD}
+N 3260 -940 3290 -940 {
+lab=VDD}
+N 3260 -760 3260 -750 {
+lab=GND}
+N 3260 -800 3290 -800 {
+lab=GND}
+N 3290 -800 3290 -760 {
+lab=GND}
+N 3260 -760 3290 -760 {
+lab=GND}
+N 3420 -850 3420 -830 {
+lab=#net19}
+N 3360 -900 3380 -900 {
+lab=#net18}
+N 3360 -850 3360 -800 {
+lab=#net18}
+N 3360 -800 3380 -800 {
+lab=#net18}
+N 3420 -940 3420 -930 {
+lab=VDD}
+N 3420 -900 3450 -900 {
+lab=VDD}
+N 3450 -940 3450 -900 {
+lab=VDD}
+N 3420 -940 3450 -940 {
+lab=VDD}
+N 3420 -760 3420 -750 {
+lab=GND}
+N 3420 -800 3450 -800 {
+lab=GND}
+N 3450 -800 3450 -760 {
+lab=GND}
+N 3420 -760 3450 -760 {
+lab=GND}
+N 3570 -850 3570 -830 {
+lab=Outp}
+N 3510 -900 3530 -900 {
+lab=#net19}
+N 3510 -850 3510 -800 {
+lab=#net19}
+N 3510 -800 3530 -800 {
+lab=#net19}
+N 3570 -940 3570 -930 {
+lab=VDD}
+N 3570 -900 3600 -900 {
+lab=VDD}
+N 3600 -940 3600 -900 {
+lab=VDD}
+N 3570 -940 3600 -940 {
+lab=VDD}
+N 3570 -760 3570 -750 {
+lab=GND}
+N 3570 -800 3600 -800 {
+lab=GND}
+N 3600 -800 3600 -760 {
+lab=GND}
+N 3570 -760 3600 -760 {
+lab=GND}
+N 3100 -850 3200 -850 {
+lab=#net17}
+N 3260 -850 3360 -850 {
+lab=#net18}
+N 3420 -850 3510 -850 {
+lab=#net19}
+N 3570 -850 3660 -850 {
+lab=Outp}
+N 3010 -850 3040 -850 {
+lab=p}
+N 3100 -970 3100 -940 {
+lab=VDD}
+N 3420 -970 3570 -970 {
+lab=VDD}
+N 3570 -970 3570 -940 {
+lab=VDD}
+N 3260 -970 3260 -940 {
+lab=VDD}
+N 3420 -970 3420 -940 {
+lab=VDD}
+N 3100 -770 3100 -760 {
+lab=GND}
+N 3260 -770 3260 -760 {
+lab=GND}
+N 3420 -770 3420 -760 {
+lab=GND}
+N 3570 -770 3570 -760 {
+lab=GND}
+N 3100 -870 3100 -850 {
+lab=#net17}
+N 3200 -900 3200 -850 {
+lab=#net17}
+N 3260 -870 3260 -850 {
+lab=#net18}
+N 3360 -900 3360 -850 {
+lab=#net18}
+N 3420 -870 3420 -850 {
+lab=#net19}
+N 3510 -900 3510 -850 {
+lab=#net19}
+N 3570 -870 3570 -850 {
+lab=Outp}
+N 3040 -900 3040 -850 {
+lab=p}
+N 3100 -970 3260 -970 {
+lab=VDD}
+N 3260 -970 3420 -970 {
+lab=VDD}
+N 3100 -750 3570 -750 {
+lab=GND}
+C {sky130_fd_pr/nfet_01v8.sym} 1350 -890 0 0 {name=M1
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1810 -880 0 1 {name=M2
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1570 -770 0 0 {name=M3
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1570 -920 0 0 {name=M4
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1670 -1020 0 0 {name=M5
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1670 -1110 0 0 {name=M6
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1520 -1020 0 1 {name=M7
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1520 -1110 0 1 {name=M8
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1230 -1160 0 1 {name=M9
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1920 -1160 0 0 {name=M10
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1400 -1250 0 0 {name=M11
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1500 -1250 0 0 {name=M12
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1640 -1250 0 0 {name=M13
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1740 -1250 0 0 {name=M14
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1510 -770 0 0 {name=l5 sig_type=std_logic lab=C}
+C {devices/lab_pin.sym} 1530 -920 0 0 {name=l6 sig_type=std_logic lab=C
+}
+C {devices/lab_pin.sym} 1630 -1110 3 0 {name=l7 sig_type=std_logic lab=C}
+C {sky130_fd_pr/nfet_01v8.sym} 2370 -920 0 0 {name=M15
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2170 -920 0 1 {name=M16
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2370 -1060 0 0 {name=M17
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2170 -1060 0 1 {name=M18
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2240 -1180 0 0 {name=M19
+L=0.15
+W=3
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 1210 -1220 0 0 {name=l12 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 1940 -1220 2 0 {name=l13 sig_type=std_logic lab=Dp}
+C {devices/lab_pin.sym} 2150 -970 0 0 {name=l14 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 2390 -990 2 0 {name=l15 sig_type=std_logic lab=Dp}
+C {sky130_fd_pr/nfet_01v8.sym} 2860 -910 0 1 {name=M20
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2580 -910 0 0 {name=M21
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2820 -1050 0 0 {name=M22
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2620 -1050 0 1 {name=M23
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 2530 -910 0 0 {name=l30 sig_type=std_logic lab=Dn}
+C {devices/lab_pin.sym} 2910 -910 2 0 {name=l31 sig_type=std_logic lab=Dp}
+C {devices/lab_pin.sym} 2840 -1000 2 0 {name=l34 sig_type=std_logic lab=p}
+C {devices/iopin.sym} 1020 -1510 0 0 {name=p1 lab=VDD}
+C {devices/iopin.sym} 1020 -1470 0 0 {name=p2 lab=GND
+}
+C {devices/ipin.sym} 1870 -880 2 0 {name=p3 lab=Vn
+}
+C {devices/ipin.sym} 1310 -890 0 0 {name=p4 lab=Vp}
+C {devices/iopin.sym} 470 -1130 2 0 {name=p5 lab=CLK}
+C {devices/opin.sym} 3650 -1220 0 0 {name=p7 lab=Outn}
+C {devices/opin.sym} 3650 -850 0 0 {name=p8 lab=Outp}
+C {devices/lab_pin.sym} 1590 -1290 1 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2260 -1230 1 0 {name=l11 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 2710 -1140 1 0 {name=l27 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1590 -710 3 0 {name=l10 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2260 -870 3 0 {name=l2 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 2690 -860 3 0 {name=l19 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1940 -1110 3 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1200 -1110 3 0 {name=l3 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1590 -850 0 0 {name=l1 sig_type=std_logic lab=GND}
+C {devices/lab_wire.sym} 2180 -1340 0 0 {name=l28 sig_type=std_logic lab=CB}
+C {sky130_fd_pr/nfet_01v8.sym} 530 -1080 0 0 {name=M24
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 530 -1180 0 0 {name=M25
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 690 -1080 0 0 {name=M26
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 690 -1180 0 0 {name=M27
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 850 -1080 0 0 {name=M28
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 850 -1180 0 0 {name=M29
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1000 -1080 0 0 {name=M30
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1000 -1180 0 0 {name=M31
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 830 -1030 3 0 {name=l24 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 840 -1250 1 0 {name=l25 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1110 -1130 0 0 {name=l29 sig_type=std_logic lab=C}
+C {devices/lab_pin.sym} 1340 -1250 0 0 {name=l8 sig_type=std_logic lab=C}
+C {devices/iopin.sym} 440 -740 2 0 {name=p9 lab=CLKBAR}
+C {sky130_fd_pr/nfet_01v8.sym} 500 -690 0 0 {name=M32
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 500 -790 0 0 {name=M33
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 660 -690 0 0 {name=M34
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 660 -790 0 0 {name=M35
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 820 -690 0 0 {name=M36
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 820 -790 0 0 {name=M37
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 970 -690 0 0 {name=M38
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 970 -790 0 0 {name=M39
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 800 -640 3 0 {name=l16 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 810 -860 1 0 {name=l26 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1080 -740 0 0 {name=l32 sig_type=std_logic lab=CB}
+C {sky130_fd_pr/nfet_01v8.sym} 3080 -1170 0 0 {name=M40
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3080 -1270 0 0 {name=M41
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3240 -1170 0 0 {name=M42
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3240 -1270 0 0 {name=M43
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3400 -1170 0 0 {name=M44
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3400 -1270 0 0 {name=M45
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3550 -1170 0 0 {name=M46
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3550 -1270 0 0 {name=M47
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 3380 -1120 3 0 {name=l20 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 3390 -1340 1 0 {name=l22 sig_type=std_logic lab=VDD}
+C {sky130_fd_pr/nfet_01v8.sym} 3080 -800 0 0 {name=M48
+L=0.15
+W=1
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3080 -900 0 0 {name=M49
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3240 -800 0 0 {name=M50
+L=0.15
+W=2
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3240 -900 0 0 {name=M51
+L=0.15
+W=4
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3400 -800 0 0 {name=M52
+L=0.15
+W=8
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3400 -900 0 0 {name=M53
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 3550 -800 0 0 {name=M54
+L=0.15
+W=16
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 3550 -900 0 0 {name=M55
+L=0.15
+W=32
+nf=1
+mult=1
+ad="'int((nf+1)/2) * W/nf * 0.29'"
+pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
+as="'int((nf+2)/2) * W/nf * 0.29'"
+ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+model=pfet_01v8
+spiceprefix=X
+}
+C {devices/lab_pin.sym} 3380 -750 3 0 {name=l21 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 3390 -970 1 0 {name=l23 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 3010 -850 2 0 {name=l17 sig_type=std_logic lab=p}
+C {devices/lab_pin.sym} 2600 -1000 2 0 {name=l18 sig_type=std_logic lab=n}
+C {devices/lab_pin.sym} 3010 -1220 0 0 {name=l33 sig_type=std_logic lab=n}
diff --git a/xschem/comparator.spice b/xschem/comparator.spice
new file mode 100644
index 0000000..a093396
--- /dev/null
+++ b/xschem/comparator.spice
@@ -0,0 +1,177 @@
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sch
+**.subckt comparator_schv5 VDD GND Vn Vp CLK Outn Outp CLKBAR
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+*.iopin CLKBAR
+XM1 net5 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net6 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net2 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net5 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net6 C net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net3 net6 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net5 C net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dn net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 Dp net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net4 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net7 CB VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net8 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net8 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net10 net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net10 net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM32 net11 CLKBAR GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM33 net11 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM34 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM35 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM36 net13 net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM37 net13 net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM38 CB net13 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM39 CB net13 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net14 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net14 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net15 net14 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net15 net14 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net16 net15 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net16 net15 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net16 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net16 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net17 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net17 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net18 net17 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net18 net17 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net19 net18 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net19 net18 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net19 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net19 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+**.ends
+.end
diff --git a/xschem/comparator.sym b/xschem/comparator.sym
new file mode 100644
index 0000000..7ebd68e
--- /dev/null
+++ b/xschem/comparator.sym
@@ -0,0 +1,35 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+T {@symname} -90 -6 0 0 0.3 0.3 {}
+T {@name} 135 -72 0 0 0.2 0.2 {}
+L 4 -130 -60 130 -60 {}
+L 4 -130 60 130 60 {}
+L 4 -130 -60 -130 60 {}
+L 4 130 -60 130 60 {}
+B 5 147.5 -52.5 152.5 -47.5 {name=VDD dir=inout }
+L 7 130 -50 150 -50 {}
+T {VDD} 125 -54 0 1 0.2 0.2 {}
+B 5 147.5 -32.5 152.5 -27.5 {name=GND dir=inout }
+L 7 130 -30 150 -30 {}
+T {GND} 125 -34 0 1 0.2 0.2 {}
+B 5 147.5 -12.5 152.5 -7.5 {name=Outn dir=out }
+L 4 130 -10 150 -10 {}
+T {Outn} 125 -14 0 1 0.2 0.2 {}
+B 5 147.5 7.5 152.5 12.5 {name=CLK dir=inout }
+L 7 130 10 150 10 {}
+T {CLK} 125 6 0 1 0.2 0.2 {}
+B 5 -152.5 -52.5 -147.5 -47.5 {name=Vp dir=in }
+L 4 -150 -50 -130 -50 {}
+T {Vp} -125 -54 0 0 0.2 0.2 {}
+B 5 -152.5 -32.5 -147.5 -27.5 {name=Vn dir=in }
+L 4 -150 -30 -130 -30 {}
+T {Vn} -125 -34 0 0 0.2 0.2 {}
+B 5 147.5 27.5 152.5 32.5 {name=Outp dir=out }
+L 4 130 30 150 30 {}
+T {Outp} 125 26 0 1 0.2 0.2 {}
+B 5 147.5 47.5 152.5 52.5 {name=CLKBAR dir=inout }
+L 7 130 50 150 50 {}
+T {CLKBAR} 125 46 0 1 0.2 0.2 {}
diff --git a/xschem/comparator_lvs.spice b/xschem/comparator_lvs.spice
new file mode 100644
index 0000000..16e622b
--- /dev/null
+++ b/xschem/comparator_lvs.spice
@@ -0,0 +1,81 @@
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5lvs.sch
+.subckt comparator_lvs VDD GND Vn Vp Outp Outn CLK CLKBAR
+.iopin VDD
+.iopin GND
+.ipin Vn
+.ipin Vp
+.opin Outp
+.opin Outn
+.iopin CLK
+.iopin CLKBAR
+XM1 net5 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net6 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net2 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net5 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net6 CLK net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net3 net6 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net5 CLK net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dn net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 Dp net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net3 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net4 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net7 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 Outp Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 Outn Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 Outp Outn VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 Outn Outp VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+.end
diff --git a/xschem/comparator_tb.sch b/xschem/comparator_tb.sch
new file mode 100644
index 0000000..5b6ed10
--- /dev/null
+++ b/xschem/comparator_tb.sch
@@ -0,0 +1,91 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 800 -820 800 -800 {
+lab=GND}
+N 800 -910 800 -880 {
+lab=VDD}
+N 1010 -710 1010 -690 {
+lab=Vp}
+N 1010 -790 1010 -770 {
+lab=Vn}
+N 1010 -690 1100 -690 {
+lab=Vp}
+N 1100 -690 1100 -670 {
+lab=Vp}
+N 1100 -610 1100 -590 {
+lab=GND}
+N 1100 -690 1170 -690 {
+lab=Vp}
+N 1170 -790 1170 -690 {
+lab=Vp}
+N 910 -910 910 -880 {
+lab=CLK}
+N 800 -650 800 -630 {
+lab=GND}
+N 800 -740 800 -710 {
+lab=CLKBAR}
+N 1340 -1000 1400 -1000 {
+lab=Vp}
+N 1340 -980 1400 -980 {
+lab=Vn}
+N 910 -820 910 -790 {
+lab=GND}
+N 1330 -710 1330 -670 {
+lab=GND}
+N 1330 -810 1330 -770 {
+lab=GND}
+N 1700 -1000 1790 -1000 {
+lab=VDD}
+N 1700 -980 1750 -980 {
+lab=GND}
+N 1700 -940 1730 -940 {
+lab=CLK}
+N 1700 -900 1760 -900 {
+lab=CLKBAR}
+N 1700 -960 1740 -960 {
+lab=#net1}
+N 1700 -920 1740 -920 {
+lab=#net2}
+C {devices/TT_models.sym} 950 -1180 0 0 {name=TT_MODELS
+only_toplevel=true
+format="tcleval( @value )"
+value="
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+"
+spice_ignore=falsename=s1 only_toplevel=false value=blabla}
+C {devices/vsource.sym} 800 -850 0 0 {name=Vdd value=1.8}
+C {devices/vsource.sym} 1010 -740 0 0 {name=Vn value="pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)"}
+C {devices/lab_pin.sym} 1010 -790 0 0 {name=l24 sig_type=std_logic lab=Vn}
+C {devices/vsource.sym} 1100 -640 0 0 {name=Vcm value=1.2}
+C {devices/lab_pin.sym} 1170 -790 2 0 {name=l25 sig_type=std_logic lab=Vp}
+C {devices/code_shown.sym} 2030 -770 0 0 {name=SPICE only_toplevel=false value=".tran 0.01n 50n
+.save all"}
+C {devices/vsource.sym} 910 -850 0 0 {name=V1 value="pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 910 -910 0 0 {name=l22 sig_type=std_logic lab=CLK}
+C {devices/vsource.sym} 800 -680 0 0 {name=V2 value="pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)"}
+C {devices/lab_pin.sym} 800 -740 0 0 {name=l27 sig_type=std_logic lab=CLKBAR}
+C {comparator_schv5.sym} 1550 -950 0 0 {name=x1}
+C {devices/lab_pin.sym} 1340 -980 0 0 {name=l1 sig_type=std_logic lab=Vn}
+C {devices/lab_pin.sym} 1340 -1000 0 0 {name=l2 sig_type=std_logic lab=Vp}
+C {devices/gnd.sym} 1330 -670 0 0 {name=l3 lab=GND}
+C {devices/lab_pin.sym} 1330 -810 2 0 {name=l4 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1100 -590 2 0 {name=l5 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -630 2 0 {name=l6 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -800 2 0 {name=l7 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 910 -790 2 0 {name=l8 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 800 -910 0 0 {name=l9 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1790 -1000 2 0 {name=l10 sig_type=std_logic lab=VDD}
+C {devices/lab_pin.sym} 1750 -980 2 0 {name=l11 sig_type=std_logic lab=GND}
+C {devices/lab_pin.sym} 1730 -940 2 0 {name=l12 sig_type=std_logic lab=CLK}
+C {devices/lab_pin.sym} 1760 -900 2 0 {name=l13 sig_type=std_logic lab=CLKBAR}
+C {devices/res.sym} 1330 -740 0 0 {name=R1
+value=0
+footprint=1206
+device=resistor
+m=1}
diff --git a/xschem/comparator_tb.spice b/xschem/comparator_tb.spice
new file mode 100644
index 0000000..6decc7c
--- /dev/null
+++ b/xschem/comparator_tb.spice
@@ -0,0 +1,203 @@
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_tb.sch
+**.subckt comparator_tb
+Vdd VDD GND 1.8
+Vn Vn Vp pulse(-10m 10m 1ps 1ps 1ps 4ns 8ns)
+Vcm Vp GND 1.2
+V1 CLK GND pulse(1.8 0 1ps 1ps 1ps 2ns 4ns)
+V2 CLKBAR GND pulse(0 1.8 1ps 1ps 1ps 2ns 4ns)
+x1 VDD GND net1 CLK Vp Vn net2 CLKBAR comparator_schv5
+R1 GND GND 0 m=1
+**** begin user architecture code
+
+** opencircuitdesign pdks install
+.lib /usr/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
+
+.control
+tran 0.01n 50n
+save all
+write comparator_tb.raw
+.endc
+**** end user architecture code
+**.ends
+
+* expanding symbol: comparator_schv5.sym # of pins=8
+** sym_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sym
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sch
+.subckt comparator_schv5 VDD GND Outn CLK Vp Vn Outp CLKBAR
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+*.iopin CLKBAR
+XM1 net5 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net6 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net2 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net5 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net6 C net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net3 net6 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net5 C net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dn net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 Dp net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net4 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net7 CB VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net8 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net8 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net10 net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net10 net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM32 net11 CLKBAR GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM33 net11 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM34 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM35 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM36 net13 net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM37 net13 net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM38 CB net13 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM39 CB net13 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net14 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net14 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net15 net14 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net15 net14 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net16 net15 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net16 net15 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net16 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net16 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net17 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net17 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net18 net17 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net18 net17 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net19 net18 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net19 net18 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net19 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net19 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.GLOBAL GND
+.end
diff --git a/xschem/user_analog_project_wrapper.sch b/xschem/user_analog_project_wrapper.sch
new file mode 100644
index 0000000..d01949a
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sch
@@ -0,0 +1,67 @@
+v {xschem version=3.0.0 file_version=1.2 }
+G {}
+K {}
+V {}
+S {}
+E {}
+N 4030 -200 4100 -200 {
+lab=vccd1}
+N 4030 -180 4100 -180 {
+lab=vssa1}
+N 4030 -160 4100 -160 {
+lab=io_analog[3]}
+N 4030 -120 4100 -120 {
+lab=io_analog[2]}
+N 4030 -140 4100 -140 {
+lab=io_analog[8]}
+N 4030 -100 4100 -100 {
+lab=io_analog[7]}
+N 3530 500 3580 500 {
+lab=io_clamp_high[2:1]}
+N 3530 540 3580 540 {
+lab=io_clamp_high[2:1]}
+C {devices/iopin.sym} 3240 -470 0 0 {name=p1 lab=vdda1}
+C {devices/iopin.sym} 3240 -440 0 0 {name=p2 lab=vdda2}
+C {devices/iopin.sym} 3240 -410 0 0 {name=p3 lab=vssa1}
+C {devices/iopin.sym} 3240 -380 0 0 {name=p4 lab=vssa2}
+C {devices/iopin.sym} 3240 -350 0 0 {name=p5 lab=vccd1}
+C {devices/iopin.sym} 3240 -320 0 0 {name=p6 lab=vccd2}
+C {devices/iopin.sym} 3240 -290 0 0 {name=p7 lab=vssd1}
+C {devices/iopin.sym} 3240 -260 0 0 {name=p8 lab=vssd2}
+C {devices/ipin.sym} 3290 -190 0 0 {name=p9 lab=wb_clk_i}
+C {devices/ipin.sym} 3290 -160 0 0 {name=p10 lab=wb_rst_i}
+C {devices/ipin.sym} 3290 -130 0 0 {name=p11 lab=wbs_stb_i}
+C {devices/ipin.sym} 3290 -100 0 0 {name=p12 lab=wbs_cyc_i}
+C {devices/ipin.sym} 3290 -70 0 0 {name=p13 lab=wbs_we_i}
+C {devices/ipin.sym} 3290 -40 0 0 {name=p14 lab=wbs_sel_i[3:0]}
+C {devices/ipin.sym} 3290 -10 0 0 {name=p15 lab=wbs_dat_i[31:0]}
+C {devices/ipin.sym} 3290 20 0 0 {name=p16 lab=wbs_adr_i[31:0]}
+C {devices/opin.sym} 3280 80 0 0 {name=p17 lab=wbs_ack_o}
+C {devices/opin.sym} 3280 110 0 0 {name=p18 lab=wbs_dat_o[31:0]}
+C {devices/ipin.sym} 3290 150 0 0 {name=p19 lab=la_data_in[127:0]}
+C {devices/opin.sym} 3280 180 0 0 {name=p20 lab=la_data_out[127:0]}
+C {devices/ipin.sym} 3290 260 0 0 {name=p21 lab=io_in[26:0]}
+C {devices/ipin.sym} 3290 290 0 0 {name=p22 lab=io_in_3v3[26:0]}
+C {devices/ipin.sym} 3280 570 0 0 {name=p23 lab=user_clock2}
+C {devices/opin.sym} 3280 320 0 0 {name=p24 lab=io_out[26:0]}
+C {devices/opin.sym} 3280 350 0 0 {name=p25 lab=io_oeb[26:0]}
+C {devices/iopin.sym} 3250 410 0 0 {name=p26 lab=gpio_analog[17:0]}
+C {devices/iopin.sym} 3250 440 0 0 {name=p27 lab=gpio_noesd[17:0]}
+C {devices/iopin.sym} 3250 470 0 0 {name=p29 lab=io_analog[10:0]}
+C {devices/iopin.sym} 3250 500 0 0 {name=p30 lab=io_clamp_high[2:0]}
+C {devices/iopin.sym} 3250 530 0 0 {name=p31 lab=io_clamp_low[2:0]}
+C {devices/opin.sym} 3270 600 0 0 {name=p32 lab=user_irq[2:0]}
+C {devices/ipin.sym} 3290 210 0 0 {name=p28 lab=la_oenb[127:0]}
+C {comparator_schv5.sym} 3880 -150 0 0 {name=x1}
+C {devices/lab_pin.sym} 4100 -200 2 0 {name=l1 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 4100 -180 0 1 {name=l2 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 4100 -160 2 0 {name=l3 sig_type=std_logic lab=io_analog[3]}
+C {devices/lab_pin.sym} 4100 -120 2 0 {name=l4 sig_type=std_logic lab=io_analog[2]}
+C {devices/lab_pin.sym} 4100 -140 2 0 {name=l5 sig_type=std_logic lab=io_analog[8]}
+C {devices/lab_pin.sym} 4100 -100 2 0 {name=l6 sig_type=std_logic lab=io_analog[7]}
+C {devices/lab_pin.sym} 3730 -200 0 0 {name=l7 sig_type=std_logic lab=io_analog[5]}
+C {devices/lab_pin.sym} 3730 -180 0 0 {name=l8 sig_type=std_logic lab=io_analog[6]}
+C {devices/lab_pin.sym} 3530 500 0 0 {name=l9 sig_type=std_logic lab=vccd1}
+C {devices/lab_pin.sym} 3530 540 2 1 {name=l10 sig_type=std_logic lab=vssa1}
+C {devices/lab_pin.sym} 3580 500 2 0 {name=l11 sig_type=std_logic lab=io_clamp_high[2:1]}
+C {devices/lab_pin.sym} 3580 540 2 0 {name=l12 sig_type=std_logic lab=io_clamp_high[2:1]}
diff --git a/xschem/user_analog_project_wrapper.spice b/xschem/user_analog_project_wrapper.spice
new file mode 100644
index 0000000..77e4508
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.spice
@@ -0,0 +1,246 @@
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/user_analog_project_wrapper.sch
+**.subckt user_analog_project_wrapper vdda1 vdda2 vssa1 vssa2 vccd1 vccd2 vssd1 vssd2 wb_clk_i
+*+ wb_rst_i wbs_stb_i wbs_cyc_i wbs_we_i wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0] wbs_ack_o
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0] user_clock2
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0] io_clamp_high[2],io_clamp_high[1],io_clamp_high[0] io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*+ user_irq[2],user_irq[1],user_irq[0]
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+*.iopin vdda1
+*.iopin vdda2
+*.iopin vssa1
+*.iopin vssa2
+*.iopin vccd1
+*.iopin vccd2
+*.iopin vssd1
+*.iopin vssd2
+*.ipin wb_clk_i
+*.ipin wb_rst_i
+*.ipin wbs_stb_i
+*.ipin wbs_cyc_i
+*.ipin wbs_we_i
+*.ipin wbs_sel_i[3],wbs_sel_i[2],wbs_sel_i[1],wbs_sel_i[0]
+*.ipin
+*+ wbs_dat_i[31],wbs_dat_i[30],wbs_dat_i[29],wbs_dat_i[28],wbs_dat_i[27],wbs_dat_i[26],wbs_dat_i[25],wbs_dat_i[24],wbs_dat_i[23],wbs_dat_i[22],wbs_dat_i[21],wbs_dat_i[20],wbs_dat_i[19],wbs_dat_i[18],wbs_dat_i[17],wbs_dat_i[16],wbs_dat_i[15],wbs_dat_i[14],wbs_dat_i[13],wbs_dat_i[12],wbs_dat_i[11],wbs_dat_i[10],wbs_dat_i[9],wbs_dat_i[8],wbs_dat_i[7],wbs_dat_i[6],wbs_dat_i[5],wbs_dat_i[4],wbs_dat_i[3],wbs_dat_i[2],wbs_dat_i[1],wbs_dat_i[0]
+*.ipin
+*+ wbs_adr_i[31],wbs_adr_i[30],wbs_adr_i[29],wbs_adr_i[28],wbs_adr_i[27],wbs_adr_i[26],wbs_adr_i[25],wbs_adr_i[24],wbs_adr_i[23],wbs_adr_i[22],wbs_adr_i[21],wbs_adr_i[20],wbs_adr_i[19],wbs_adr_i[18],wbs_adr_i[17],wbs_adr_i[16],wbs_adr_i[15],wbs_adr_i[14],wbs_adr_i[13],wbs_adr_i[12],wbs_adr_i[11],wbs_adr_i[10],wbs_adr_i[9],wbs_adr_i[8],wbs_adr_i[7],wbs_adr_i[6],wbs_adr_i[5],wbs_adr_i[4],wbs_adr_i[3],wbs_adr_i[2],wbs_adr_i[1],wbs_adr_i[0]
+*.opin wbs_ack_o
+*.opin
+*+ wbs_dat_o[31],wbs_dat_o[30],wbs_dat_o[29],wbs_dat_o[28],wbs_dat_o[27],wbs_dat_o[26],wbs_dat_o[25],wbs_dat_o[24],wbs_dat_o[23],wbs_dat_o[22],wbs_dat_o[21],wbs_dat_o[20],wbs_dat_o[19],wbs_dat_o[18],wbs_dat_o[17],wbs_dat_o[16],wbs_dat_o[15],wbs_dat_o[14],wbs_dat_o[13],wbs_dat_o[12],wbs_dat_o[11],wbs_dat_o[10],wbs_dat_o[9],wbs_dat_o[8],wbs_dat_o[7],wbs_dat_o[6],wbs_dat_o[5],wbs_dat_o[4],wbs_dat_o[3],wbs_dat_o[2],wbs_dat_o[1],wbs_dat_o[0]
+*.ipin
+*+ la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]
+*.opin
+*+ la_data_out[127],la_data_out[126],la_data_out[125],la_data_out[124],la_data_out[123],la_data_out[122],la_data_out[121],la_data_out[120],la_data_out[119],la_data_out[118],la_data_out[117],la_data_out[116],la_data_out[115],la_data_out[114],la_data_out[113],la_data_out[112],la_data_out[111],la_data_out[110],la_data_out[109],la_data_out[108],la_data_out[107],la_data_out[106],la_data_out[105],la_data_out[104],la_data_out[103],la_data_out[102],la_data_out[101],la_data_out[100],la_data_out[99],la_data_out[98],la_data_out[97],la_data_out[96],la_data_out[95],la_data_out[94],la_data_out[93],la_data_out[92],la_data_out[91],la_data_out[90],la_data_out[89],la_data_out[88],la_data_out[87],la_data_out[86],la_data_out[85],la_data_out[84],la_data_out[83],la_data_out[82],la_data_out[81],la_data_out[80],la_data_out[79],la_data_out[78],la_data_out[77],la_data_out[76],la_data_out[75],la_data_out[74],la_data_out[73],la_data_out[72],la_data_out[71],la_data_out[70],la_data_out[69],la_data_out[68],la_data_out[67],la_data_out[66],la_data_out[65],la_data_out[64],la_data_out[63],la_data_out[62],la_data_out[61],la_data_out[60],la_data_out[59],la_data_out[58],la_data_out[57],la_data_out[56],la_data_out[55],la_data_out[54],la_data_out[53],la_data_out[52],la_data_out[51],la_data_out[50],la_data_out[49],la_data_out[48],la_data_out[47],la_data_out[46],la_data_out[45],la_data_out[44],la_data_out[43],la_data_out[42],la_data_out[41],la_data_out[40],la_data_out[39],la_data_out[38],la_data_out[37],la_data_out[36],la_data_out[35],la_data_out[34],la_data_out[33],la_data_out[32],la_data_out[31],la_data_out[30],la_data_out[29],la_data_out[28],la_data_out[27],la_data_out[26],la_data_out[25],la_data_out[24],la_data_out[23],la_data_out[22],la_data_out[21],la_data_out[20],la_data_out[19],la_data_out[18],la_data_out[17],la_data_out[16],la_data_out[15],la_data_out[14],la_data_out[13],la_data_out[12],la_data_out[11],la_data_out[10],la_data_out[9],la_data_out[8],la_data_out[7],la_data_out[6],la_data_out[5],la_data_out[4],la_data_out[3],la_data_out[2],la_data_out[1],la_data_out[0]
+*.ipin
+*+ io_in[26],io_in[25],io_in[24],io_in[23],io_in[22],io_in[21],io_in[20],io_in[19],io_in[18],io_in[17],io_in[16],io_in[15],io_in[14],io_in[13],io_in[12],io_in[11],io_in[10],io_in[9],io_in[8],io_in[7],io_in[6],io_in[5],io_in[4],io_in[3],io_in[2],io_in[1],io_in[0]
+*.ipin
+*+ io_in_3v3[26],io_in_3v3[25],io_in_3v3[24],io_in_3v3[23],io_in_3v3[22],io_in_3v3[21],io_in_3v3[20],io_in_3v3[19],io_in_3v3[18],io_in_3v3[17],io_in_3v3[16],io_in_3v3[15],io_in_3v3[14],io_in_3v3[13],io_in_3v3[12],io_in_3v3[11],io_in_3v3[10],io_in_3v3[9],io_in_3v3[8],io_in_3v3[7],io_in_3v3[6],io_in_3v3[5],io_in_3v3[4],io_in_3v3[3],io_in_3v3[2],io_in_3v3[1],io_in_3v3[0]
+*.ipin user_clock2
+*.opin
+*+ io_out[26],io_out[25],io_out[24],io_out[23],io_out[22],io_out[21],io_out[20],io_out[19],io_out[18],io_out[17],io_out[16],io_out[15],io_out[14],io_out[13],io_out[12],io_out[11],io_out[10],io_out[9],io_out[8],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]
+*.opin
+*+ io_oeb[26],io_oeb[25],io_oeb[24],io_oeb[23],io_oeb[22],io_oeb[21],io_oeb[20],io_oeb[19],io_oeb[18],io_oeb[17],io_oeb[16],io_oeb[15],io_oeb[14],io_oeb[13],io_oeb[12],io_oeb[11],io_oeb[10],io_oeb[9],io_oeb[8],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]
+*.iopin
+*+ gpio_analog[17],gpio_analog[16],gpio_analog[15],gpio_analog[14],gpio_analog[13],gpio_analog[12],gpio_analog[11],gpio_analog[10],gpio_analog[9],gpio_analog[8],gpio_analog[7],gpio_analog[6],gpio_analog[5],gpio_analog[4],gpio_analog[3],gpio_analog[2],gpio_analog[1],gpio_analog[0]
+*.iopin
+*+ gpio_noesd[17],gpio_noesd[16],gpio_noesd[15],gpio_noesd[14],gpio_noesd[13],gpio_noesd[12],gpio_noesd[11],gpio_noesd[10],gpio_noesd[9],gpio_noesd[8],gpio_noesd[7],gpio_noesd[6],gpio_noesd[5],gpio_noesd[4],gpio_noesd[3],gpio_noesd[2],gpio_noesd[1],gpio_noesd[0]
+*.iopin
+*+ io_analog[10],io_analog[9],io_analog[8],io_analog[7],io_analog[6],io_analog[5],io_analog[4],io_analog[3],io_analog[2],io_analog[1],io_analog[0]
+*.iopin io_clamp_high[2],io_clamp_high[1],io_clamp_high[0]
+*.iopin io_clamp_low[2],io_clamp_low[1],io_clamp_low[0]
+*.opin user_irq[2],user_irq[1],user_irq[0]
+*.ipin
+*+ la_oenb[127],la_oenb[126],la_oenb[125],la_oenb[124],la_oenb[123],la_oenb[122],la_oenb[121],la_oenb[120],la_oenb[119],la_oenb[118],la_oenb[117],la_oenb[116],la_oenb[115],la_oenb[114],la_oenb[113],la_oenb[112],la_oenb[111],la_oenb[110],la_oenb[109],la_oenb[108],la_oenb[107],la_oenb[106],la_oenb[105],la_oenb[104],la_oenb[103],la_oenb[102],la_oenb[101],la_oenb[100],la_oenb[99],la_oenb[98],la_oenb[97],la_oenb[96],la_oenb[95],la_oenb[94],la_oenb[93],la_oenb[92],la_oenb[91],la_oenb[90],la_oenb[89],la_oenb[88],la_oenb[87],la_oenb[86],la_oenb[85],la_oenb[84],la_oenb[83],la_oenb[82],la_oenb[81],la_oenb[80],la_oenb[79],la_oenb[78],la_oenb[77],la_oenb[76],la_oenb[75],la_oenb[74],la_oenb[73],la_oenb[72],la_oenb[71],la_oenb[70],la_oenb[69],la_oenb[68],la_oenb[67],la_oenb[66],la_oenb[65],la_oenb[64],la_oenb[63],la_oenb[62],la_oenb[61],la_oenb[60],la_oenb[59],la_oenb[58],la_oenb[57],la_oenb[56],la_oenb[55],la_oenb[54],la_oenb[53],la_oenb[52],la_oenb[51],la_oenb[50],la_oenb[49],la_oenb[48],la_oenb[47],la_oenb[46],la_oenb[45],la_oenb[44],la_oenb[43],la_oenb[42],la_oenb[41],la_oenb[40],la_oenb[39],la_oenb[38],la_oenb[37],la_oenb[36],la_oenb[35],la_oenb[34],la_oenb[33],la_oenb[32],la_oenb[31],la_oenb[30],la_oenb[29],la_oenb[28],la_oenb[27],la_oenb[26],la_oenb[25],la_oenb[24],la_oenb[23],la_oenb[22],la_oenb[21],la_oenb[20],la_oenb[19],la_oenb[18],la_oenb[17],la_oenb[16],la_oenb[15],la_oenb[14],la_oenb[13],la_oenb[12],la_oenb[11],la_oenb[10],la_oenb[9],la_oenb[8],la_oenb[7],la_oenb[6],la_oenb[5],la_oenb[4],la_oenb[3],la_oenb[2],la_oenb[1],la_oenb[0]
+x1 vccd1 vssa1 io_analog[3] io_analog[8] io_analog[5] io_analog[6] io_analog[2] io_analog[7]
++ comparator_schv5
+**.ends
+
+* expanding symbol: comparator_schv5.sym # of pins=8
+** sym_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sym
+** sch_path: /home/krishna/mycomparator_copy1/prelayout/comparator/comparator_schv5.sch
+.subckt comparator_schv5 VDD GND Outn CLK Vp Vn Outp CLKBAR
+*.iopin VDD
+*.iopin GND
+*.ipin Vn
+*.ipin Vp
+*.iopin CLK
+*.opin Outn
+*.opin Outp
+*.iopin CLKBAR
+XM1 net5 Vp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net6 Vn net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net2 C GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 net5 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net6 C net4 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net3 net6 net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net5 C net3 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM9 Dn net5 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM10 Dp net6 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM11 net3 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net6 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM14 net4 C VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM15 Dp Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM16 Dn Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM17 Dp Dn net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM18 Dn Dp net7 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM19 net7 CB VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=3 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM20 p Dp GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM21 n Dn GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM22 p n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM23 n p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM24 net8 CLK GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM25 net8 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM26 net9 net8 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM27 net9 net8 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM28 net10 net9 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM29 net10 net9 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM30 C net10 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM31 C net10 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM32 net11 CLKBAR GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM33 net11 CLKBAR VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM34 net12 net11 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM35 net12 net11 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM36 net13 net12 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM37 net13 net12 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM38 CB net13 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM39 CB net13 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM40 net14 n GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM41 net14 n VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM42 net15 net14 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM43 net15 net14 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM44 net16 net15 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM45 net16 net15 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM46 Outn net16 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM47 Outn net16 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM48 net17 p GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM49 net17 p VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM50 net18 net17 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM51 net18 net17 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM52 net19 net18 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM53 net19 net18 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM54 Outp net19 GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=16 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+XM55 Outp net19 VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=32 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
++ sa=0 sb=0 sd=0 mult=1 m=1
+.ends
+
+.end
diff --git a/xschem/user_analog_project_wrapper.sym b/xschem/user_analog_project_wrapper.sym
new file mode 100644
index 0000000..6cb4d88
--- /dev/null
+++ b/xschem/user_analog_project_wrapper.sym
@@ -0,0 +1,108 @@
+v {xschem version=3.0.0 file_version=1.2}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+
+T {@symname} -139.5 -6 0 0 0.3 0.3 {}
+T {@name} 135 -202 0 0 0.2 0.2 {}
+L 4 -130 -190 130 -190 {}
+L 4 -130 190 130 190 {}
+L 4 -130 -190 -130 190 {}
+L 4 130 -190 130 190 {}
+B 5 147.5 -182.5 152.5 -177.5 {name=vdda1 dir=inout }
+L 7 130 -180 150 -180 {}
+T {vdda1} 125 -184 0 1 0.2 0.2 {}
+B 5 147.5 -162.5 152.5 -157.5 {name=vdda2 dir=inout }
+L 7 130 -160 150 -160 {}
+T {vdda2} 125 -164 0 1 0.2 0.2 {}
+B 5 147.5 -142.5 152.5 -137.5 {name=vssa1 dir=inout }
+L 7 130 -140 150 -140 {}
+T {vssa1} 125 -144 0 1 0.2 0.2 {}
+B 5 147.5 -122.5 152.5 -117.5 {name=vssa2 dir=inout }
+L 7 130 -120 150 -120 {}
+T {vssa2} 125 -124 0 1 0.2 0.2 {}
+B 5 147.5 -102.5 152.5 -97.5 {name=vccd1 dir=inout }
+L 7 130 -100 150 -100 {}
+T {vccd1} 125 -104 0 1 0.2 0.2 {}
+B 5 147.5 -82.5 152.5 -77.5 {name=vccd2 dir=inout }
+L 7 130 -80 150 -80 {}
+T {vccd2} 125 -84 0 1 0.2 0.2 {}
+B 5 147.5 -62.5 152.5 -57.5 {name=vssd1 dir=inout }
+L 7 130 -60 150 -60 {}
+T {vssd1} 125 -64 0 1 0.2 0.2 {}
+B 5 147.5 -42.5 152.5 -37.5 {name=vssd2 dir=inout }
+L 7 130 -40 150 -40 {}
+T {vssd2} 125 -44 0 1 0.2 0.2 {}
+B 5 -152.5 -182.5 -147.5 -177.5 {name=wb_clk_i dir=in }
+L 4 -150 -180 -130 -180 {}
+T {wb_clk_i} -125 -184 0 0 0.2 0.2 {}
+B 5 -152.5 -162.5 -147.5 -157.5 {name=wb_rst_i dir=in }
+L 4 -150 -160 -130 -160 {}
+T {wb_rst_i} -125 -164 0 0 0.2 0.2 {}
+B 5 -152.5 -142.5 -147.5 -137.5 {name=wbs_stb_i dir=in }
+L 4 -150 -140 -130 -140 {}
+T {wbs_stb_i} -125 -144 0 0 0.2 0.2 {}
+B 5 -152.5 -122.5 -147.5 -117.5 {name=wbs_cyc_i dir=in }
+L 4 -150 -120 -130 -120 {}
+T {wbs_cyc_i} -125 -124 0 0 0.2 0.2 {}
+B 5 -152.5 -102.5 -147.5 -97.5 {name=wbs_we_i dir=in }
+L 4 -150 -100 -130 -100 {}
+T {wbs_we_i} -125 -104 0 0 0.2 0.2 {}
+B 5 -152.5 -82.5 -147.5 -77.5 {name=wbs_sel_i[3:0] dir=in }
+L 4 -150 -80 -130 -80 {}
+T {wbs_sel_i[3:0]} -125 -84 0 0 0.2 0.2 {}
+B 5 -152.5 -62.5 -147.5 -57.5 {name=wbs_dat_i[31:0] dir=in }
+L 4 -150 -60 -130 -60 {}
+T {wbs_dat_i[31:0]} -125 -64 0 0 0.2 0.2 {}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=wbs_adr_i[31:0] dir=in }
+L 4 -150 -40 -130 -40 {}
+T {wbs_adr_i[31:0]} -125 -44 0 0 0.2 0.2 {}
+B 5 147.5 -22.5 152.5 -17.5 {name=wbs_ack_o dir=out }
+L 4 130 -20 150 -20 {}
+T {wbs_ack_o} 125 -24 0 1 0.2 0.2 {}
+B 5 147.5 -2.5 152.5 2.5 {name=wbs_dat_o[31:0] dir=out }
+L 4 130 0 150 0 {}
+T {wbs_dat_o[31:0]} 125 -4 0 1 0.2 0.2 {}
+B 5 -152.5 -22.5 -147.5 -17.5 {name=la_data_in[127:0] dir=in }
+L 4 -150 -20 -130 -20 {}
+T {la_data_in[127:0]} -125 -24 0 0 0.2 0.2 {}
+B 5 147.5 17.5 152.5 22.5 {name=la_data_out[127:0] dir=out }
+L 4 130 20 150 20 {}
+T {la_data_out[127:0]} 125 16 0 1 0.2 0.2 {}
+B 5 -152.5 -2.5 -147.5 2.5 {name=la_oenb[127:0] dir=in }
+L 4 -150 0 -130 0 {}
+T {la_oenb[127:0]} -125 -4 0 0 0.2 0.2 {}
+B 5 -152.5 17.5 -147.5 22.5 {name=io_in[26:0] dir=in }
+L 4 -150 20 -130 20 {}
+T {io_in[26:0]} -125 16 0 0 0.2 0.2 {}
+B 5 -152.5 37.5 -147.5 42.5 {name=io_in_3v3[26:0] dir=in }
+L 4 -150 40 -130 40 {}
+T {io_in_3v3[26:0]} -125 36 0 0 0.2 0.2 {}
+B 5 147.5 37.5 152.5 42.5 {name=io_out[26:0] dir=out }
+L 4 130 40 150 40 {}
+T {io_out[26:0]} 125 36 0 1 0.2 0.2 {}
+B 5 147.5 57.5 152.5 62.5 {name=io_oeb[26:0] dir=out }
+L 4 130 60 150 60 {}
+T {io_oeb[26:0]} 125 56 0 1 0.2 0.2 {}
+B 5 147.5 77.5 152.5 82.5 {name=gpio_analog[17:0] dir=inout }
+L 7 130 80 150 80 {}
+T {gpio_analog[17:0]} 125 76 0 1 0.2 0.2 {}
+B 5 147.5 97.5 152.5 102.5 {name=gpio_noesd[17:0] dir=inout }
+L 7 130 100 150 100 {}
+T {gpio_noesd[17:0]} 125 96 0 1 0.2 0.2 {}
+B 5 147.5 117.5 152.5 122.5 {name=io_analog[10:0] dir=inout }
+L 7 130 120 150 120 {}
+T {io_analog[10:0]} 125 116 0 1 0.2 0.2 {}
+B 5 147.5 137.5 152.5 142.5 {name=io_clamp_high[2:0] dir=inout }
+L 7 130 140 150 140 {}
+T {io_clamp_high[2:0]} 125 136 0 1 0.2 0.2 {}
+B 5 147.5 157.5 152.5 162.5 {name=io_clamp_low[2:0] dir=inout }
+L 7 130 160 150 160 {}
+T {io_clamp_low[2:0]} 125 156 0 1 0.2 0.2 {}
+B 5 -152.5 57.5 -147.5 62.5 {name=user_clock2 dir=in }
+L 4 -150 60 -130 60 {}
+T {user_clock2} -125 56 0 0 0.2 0.2 {}
+B 5 147.5 177.5 152.5 182.5 {name=user_irq[2:0] dir=out }
+L 4 130 180 150 180 {}
+T {user_irq[2:0]} 125 176 0 1 0.2 0.2 {}
diff --git a/xschem/xschemrc b/xschem/xschemrc
new file mode 100644
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+#### xschemrc system configuration file
+
+#### values may be overridden by user's ~/.xschem/xschemrc configuration file
+#### or by project-local ./xschemrc
+
+###########################################################################
+#### XSCHEM INSTALLATION DIRECTORY: XSCHEM_SHAREDIR
+###########################################################################
+#### Normally there is no reason to set this variable if using standard
+#### installation. Location of files is set at compile time but may be overridden
+#### with following line:
+# set XSCHEM_SHAREDIR $env(HOME)/share/xschem
+
+###########################################################################
+#### XSCHEM SYSTEM-WIDE DESIGN LIBRARY PATHS: XSCHEM_LIBRARY_PATH
+###########################################################################
+#### If unset xschem starts with XSCHEM_LIBRARY_PATH set to the default, typically:
+# /home/schippes/.xschem/xschem_library
+# /home/schippes/share/xschem/xschem_library/devices
+# /home/schippes/share/doc/xschem/examples
+# /home/schippes/share/doc/xschem/ngspice
+# /home/schippes/share/doc/xschem/logic
+# /home/schippes/share/doc/xschem/xschem_simulator
+# /home/schippes/share/doc/xschem/binto7seg
+# /home/schippes/share/doc/xschem/pcb
+# /home/schippes/share/doc/xschem/rom8k
+
+#### Allow user environment to override the path to the PDK
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "usr/local/share/pdk/sky130A"
+}
+#### Flush any previous definition
+set XSCHEM_LIBRARY_PATH {}
+#### include devices/*.sym
+append XSCHEM_LIBRARY_PATH ${XSCHEM_SHAREDIR}/xschem_library
+#### include skywater libraries. Here i use [pwd]. This works if i start xschem from here.
+append XSCHEM_LIBRARY_PATH :$env(PWD)
+append XSCHEM_LIBRARY_PATH :$PDKPATH/libs.tech/xschem
+# append XSCHEM_LIBRARY_PATH :/mnt/sda7/home/schippes/pdks/sky130A/libs.tech/xschem
+#### add ~/.xschem/xschem_library (USER_CONF_DIR is normally ~/.xschem)
+append XSCHEM_LIBRARY_PATH :$USER_CONF_DIR/xschem_library
+
+###########################################################################
+#### SET CUSTOM COLORS FOR XSCHEM LIBRARIES MATCHING CERTAIN PATTERNS
+###########################################################################
+#### each line contains a dircolor(pattern) followed by a color
+#### color can be an ordinary name (grey, brown, blue) or a hex code {#77aaff}
+#### hex code must be enclosed in braces
+array unset dircolor
+set dircolor(sky130_fd_pr$) blue
+set dircolor(sky130_tests$) blue
+set dircolor(xschem_sky130$) blue
+set dircolor(xschem_library$) red
+set dircolor(devices$) red
+
+###########################################################################
+#### WINDOW TO OPEN ON STARTUP: XSCHEM_START_WINDOW
+###########################################################################
+#### Start without a design if no filename given on command line:
+#### To avoid absolute paths, use a path that is relative to one of the
+#### XSCHEM_LIBRARY_PATH directories. Default: empty
+set XSCHEM_START_WINDOW {sky130_tests/top.sch}
+
+###########################################################################
+#### DIRECTORY WHERE SIMULATIONS, NETLIST AND SIMULATOR OUTPUTS ARE PLACED
+###########################################################################
+#### If unset $USER_CONF_DIR/simulations is assumed (normally ~/.xschem/simulations)
+# set netlist_dir $env(HOME)/.xschem/simulations
+set netlist_dir .
+
+###########################################################################
+#### CHANGE DEFAULT [] WITH SOME OTHER CHARACTERS FOR BUSSED SIGNALS
+#### IN SPICE NETLISTS (EXAMPLE: DATA[7] --> DATA<7>)
+###########################################################################
+#### default: empty (use xschem default, [ ])
+# set bus_replacement_char {<>}
+#### for XSPICE: replace square brackets as the are used for XSPICE vector nodes.
+# set bus_replacement_char {__}
+
+###########################################################################
+#### SOME DEFAULT BEHAVIOR
+###########################################################################
+#### Allowed values: spice, verilog, vhdl, tedax, default: spice
+# set netlist_type spice
+
+#### Some netlisting options (these are the defaults)
+# set hspice_netlist 1
+# set verilog_2001 1
+
+#### to use a fixed line with set change_lw to 0 and set some value to line_width
+#### these are the defaults
+# set line_width 0
+# set change_lw 1
+
+#### allow color postscript and svg exports. Default: 1, enable color
+# set color_ps 1
+
+#### initial size of xschem window you can specify also position with (wxh+x+y)
+#### this is the default:
+# set initial_geometry {900x600}
+
+#### if set to 0, when zooming out allow the viewport do drift toward the mouse position,
+#### allowing to move away by zooming / unzooming with mouse wheel
+#### default setting: 0
+# set unzoom_nodrift 0
+
+#### if set to 1 allow to place multiple components with same name.
+#### Warning: this is normally not allowed in any simulation netlist.
+#### default: 0, do not allow place multiple elements with same name (refdes)
+# set disable_unique_names 0
+
+#### if set to 1 continue drawing lines / wires after click
+#### default: 0
+# set persistent_command 1
+
+#### if set to 1 automatically join/trim wires while editing
+#### this may slow down on rally big designs. Can be disabled via menu
+#### default: 0
+# set autotrim_wires 0
+
+#### set widget scaling (mainly for font display), this is useful on 4K displays
+#### default: unset (tk uses its default) > 1.0 ==> bigger
+# set tk_scaling 1.7
+
+#### disable some symbol layers. Default: none, all layers are visible.
+# set enable_layer(5) 0 ;# example to disable pin red boxes
+
+#### enable to scale grid point size as done with lines at close zoom, default: 0
+# set big_grid_points 0
+
+###########################################################################
+#### EXPORT FORMAT TRANSLATORS, PNG AND PDF
+###########################################################################
+#### command to translate xpm to png; (assumes command takes source
+#### and dest file as arguments, example: gm convert plot.xpm plot.png)
+#### default: {gm convert}
+# set to_png {gm convert}
+
+#### command to translate ps to pdf; (assumes command takes source
+#### and dest file as arguments, example: ps2pdf plot.ps plot.pdf)
+#### default: ps2pdf
+# set to_pdf ps2pdf
+set to_pdf {ps2pdf -dAutoRotatePages=/None}
+
+
+###########################################################################
+#### CUSTOM GRID / SNAP VALUE SETTINGS
+###########################################################################
+#### Warning: changing these values will likely break compatibility
+#### with existing symbol libraries. Defaults: grid 20, snap 10.
+# set grid 20
+# set snap 10
+
+###########################################################################
+#### CUSTOM COLORS MAY BE DEFINED HERE
+###########################################################################
+# set cadlayers 22
+# set light_colors {
+# "#ffffff" "#0044ee" "#aaaaaa" "#222222" "#229900"
+# "#bb2200" "#00ccee" "#ff0000" "#888800" "#00aaaa"
+# "#880088" "#00ff00" "#0000cc" "#666600" "#557755"
+# "#aa2222" "#7ccc40" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+# set dark_colors {
+# "#000000" "#00ccee" "#3f3f3f" "#cccccc" "#88dd00"
+# "#bb2200" "#00ccee" "#ff0000" "#ffff00" "#ffffff"
+# "#ff00ff" "#00ff00" "#0000cc" "#aaaa00" "#aaccaa"
+# "#ff7777" "#bfff81" "#00ffcc" "#ce0097" "#d2d46b"
+# "#ef6158" "#fdb200" }
+
+###########################################################################
+#### CAIRO STUFF
+###########################################################################
+#### Scale all fonts by this number
+# set cairo_font_scale 1.0
+
+#### default for following two is 0.85 (xscale) and 0.88 (yscale) to
+#### match cairo font spacing
+# set nocairo_font_xscale 1.0
+#### set nocairo_font_yscale 1.0
+
+#### Scale line spacing by this number
+# set cairo_font_line_spacing 1.0
+
+#### Specify a font
+# set cairo_font_name {Sans-Serif}
+# set svg_font_name {Sans-Serif}
+
+#### Lift up text by some zoom-corrected pixels for
+#### better compatibility wrt no cairo version.
+#### Useful values in the range [-1, 3]
+# set cairo_vert_correct 0
+# set nocairo_vert_correct 0
+
+###########################################################################
+#### KEYBINDINGS
+###########################################################################
+#### General format for specifying a replacement for a keybind
+#### Replace Ctrl-d with Escape (so you wont kill the program)
+# set replace_key(Control-d) Escape
+
+#### swap w and W keybinds; Always specify Shift for capital letters
+# set replace_key(Shift-W) w
+# set replace_key(w) Shift-W
+
+###########################################################################
+#### TERMINAL
+###########################################################################
+#### default for linux: xterm
+# set terminal {xterm -geometry 100x35 -fn 9x15 -bg black -fg white -cr white -ms white }
+#### lxterminal is not OK since it will not inherit env vars:
+#### In order to reduce memory usage and increase the performance, all instances
+#### of the lxterminal are sharing a single process. LXTerminal is part of LXDE
+
+###########################################################################
+#### EDITOR
+###########################################################################
+#### editor must not detach from launching shell (-f mandatory for gvim)
+#### default for linux: gvim -f
+# set editor {gvim -f -geometry 90x28}
+# set editor { xterm -geometry 100x40 -e nano }
+# set editor { xterm -geometry 100x40 -e pico }
+
+#### For Windows
+# set editor {notepad.exe}
+
+###########################################################################
+#### SHOW ERC INFO WINDOW (erc errors, warnings etc)
+###########################################################################
+#### default: 0 (can be enabled by menu)
+# set show_infowindow 0
+
+###########################################################################
+#### CONFIGURE COMPUTER FARM JOB REDIRECTORS FOR SIMULATIONS
+###########################################################################
+#### RTDA NC
+# set computerfarm {nc run -Il}
+#### LSF BSUB
+# set computerfarm {bsub -Is}
+
+###########################################################################
+#### TCP CONNECTION WITH GAW
+###########################################################################
+#### set gaw address for socket connection: {host port}
+#### default: set to localhost, port 2020
+# set gaw_tcp_address {localhost 2020}
+
+###########################################################################
+#### XSCHEM LISTEN TO TCP PORT
+###########################################################################
+#### set xschem listening port; default: not enabled
+# set xschem_listen_port 2021
+
+###########################################################################
+#### BESPICE WAVE SOCKET CONNECTION
+###########################################################################
+#### set bespice wave listening port; default: not enabled
+set bespice_listen_port 2022
+
+
+
+###########################################################################
+#### UTILE SPICE STIMULI DESCRIPTION LANGUAGE AND TRANSLATOR
+###########################################################################
+#### default paths are set as shown here:
+# set utile_gui_path ${XSCHEM_SHAREDIR}/utile/utile3
+# set utile_cmd_path ${XSCHEM_SHAREDIR}/utile/utile
+
+###########################################################################
+#### TCL FILES TO LOAD AT STARTUP
+###########################################################################
+#### list of tcl files to preload.
+# lappend tcl_files ${XSCHEM_SHAREDIR}/change_index.tcl
+lappend tcl_files ${XSCHEM_SHAREDIR}/ngspice_backannotate.tcl
+lappend tcl_files $PDKPATH/libs.tech/xschem/scripts/sky130_models.tcl
+###########################################################################
+#### XSCHEM TOOLBAR
+###########################################################################
+#### default: not enabled.
+# set toolbar_visible 1
+# set toolbar_horiz 1
+
+###########################################################################
+#### SKYWATER PDK SPECIFIC VARIABLES
+###########################################################################
+
+## (spice patched) skywater-pdk install
+# set SKYWATER_MODELS ~/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest
+# set SKYWATER_STDCELLS ~/skywater-pdk/libraries/sky130_fd_sc_hd/latest
+
+## opencircuitdesign pdks install. You need to change these to point to your open_pdks installation
+# set SKYWATER_MODELS /usr/local/share/pdk/sky130A/libs.tech/ngspice
+# set SKYWATER_STDCELLS /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
+set SKYWATER_MODELS $PDKPATH/libs.tech/ngspice
+set SKYWATER_STDCELLS $PDKPATH/libs.ref/sky130_fd_sc_hd/spice
