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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-013 / e9e96bd223d8899b009968c29bfc8debf4277c82
commite9e96bd223d8899b009968c29bfc8debf4277c82[log] [tgz]
authorJeff DiCorpo <jeffdi@efabless.com>Tue Dec 13 10:31:29 2022 -0800
committerJeff DiCorpo <jeffdi@efabless.com>Tue Dec 13 10:31:29 2022 -0800
tree3c7605fc71fe0da1a441d9acf263a4a5abd2c924
parent10bd1cc27766114dfc8c06d8c6bd0782964dcc96 [diff]
remove degenerate geometries
2 files changed
tree: 3c7605fc71fe0da1a441d9acf263a4a5abd2c924
  1. docs/
  2. gds/
  3. mag/
  4. mpw_precheck/
  5. netgen/
  6. openlane/
  7. signoff/
  8. tapeout/
  9. verilog/
  10. xschem/
  11. caravel
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

10 bit SAR-ADC + Analog Circuits

This submission features:

  • 10b SAR-ADC on powered from external supply.
  • 10b SAR-ADC powered from internal regulators.
  • Bandgap reference.
  • Testbuffer with multiplexer input.
  • Clock generator
  • 2 linear regulators, 1.2V and 1.5V.
  • Bias current/voltage generator.

Included are:

  • Hierachical GDS of the whole layout with all individual blocks.
  • Schematics for all parts of the layout.
  • Testbenches for all the individual blocks.
  • Simulation corners setups for process corner simulations.

Schematics

Simply source cadrc in the xschem folder and execute xschem afterwards to get an full overview.

Top Schematic

Layout

Top-level layout