Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-013 / 8ae43973df866c44118faaaf239d6f5ce2434d16
commit8ae43973df866c44118faaaf239d6f5ce2434d16[log] [tgz]
authorchrische <christoph-weiser@gmx.de>Tue May 17 21:50:32 2022 +0200
committerchrische <christoph-weiser@gmx.de>Tue May 17 21:50:32 2022 +0200
treedfedbc1ef318e4d7b95496fc4793d67c47b346f7
parentb48b6ce547d272d3b0bd60cc0ac2914fc1494365 [diff]
updated README
5 files changed
tree: dfedbc1ef318e4d7b95496fc4793d67c47b346f7
  1. docs/
  2. gds/
  3. mag/
  4. netgen/
  5. openlane/
  6. verilog/
  7. xschem/
  8. caravel
  9. .gitignore
  10. LICENSE
  11. Makefile
  12. README.md
README.md

10 bit SAR-ADC + Analog Circuits

This submission features:

  • 10b SAR-ADC on powered from external supply.
  • 10b SAR-ADC powered from internal regulators.
  • Bandgap reference.
  • Testbuffer with multiplexer input.
  • Clock generator
  • 2 linear regulators, 1.2V and 1.5V.
  • Bias current/voltage generator.

Included are:

  • Hierachical GDS of the whole layout with all individual blocks.
  • Schematics for all parts of the layout.
  • Testbenches for all the individual blocks.
  • Simulation corners setups for process corner simulations.

Schematics

Simply source cadrc in the xschem folder and execute xschem afterwards to get an full overview.

Top Schematic

Layout

SAR-ADC layout

Main block layout

Top-level layout