Added spi ip

openlane/spi_master/config.tcl

diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
new file mode 100755
index 0000000..a2a3a26
--- /dev/null
+++ b/openlane/spi_master/config.tcl
@@ -0,0 +1,56 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) $::env(PDK)
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) spi_master
+
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/spi_master.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "clock_in"
+#set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 150 100"
+
+#set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(FP_CORE_UTIL) 5
+set ::env(PL_TARGET_DENSITY) 0.1
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper) 
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
+# 
+set ::env(RT_MAX_LAYER) {met4}
+
+# You can draw more power domains if you need to 
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4 
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1
+#set ::env(LEC_ENABLE) 1

openlane/spi_master/pin_order.cfg

diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
new file mode 100644
index 0000000..2fda806
--- /dev/null
+++ b/openlane/spi_master/pin_order.cfg
@@ -0,0 +1,10 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+irq.*
+
+#N
+io_.*

verilog/rtl/cpu.v

diff --git a/verilog/rtl/cpu.v b/verilog/rtl/cpu.v
index 6c20cb0..5b7f5b7 100644
--- a/verilog/rtl/cpu.v
+++ b/verilog/rtl/cpu.v
@@ -24,8 +24,8 @@
   input [15:0] datain;
   output [15:0] dataout;
   output [11:0] addr;
-  input clkin, en_inp, en_out, rst;
-  output en, rdwr;
+  input clkin, en_inp, rst;
+  output en, rdwr, en_out;
   input [7:0] keyboard;
   output [7:0] display;
 
@@ -43,7 +43,8 @@
   assign dataout = (t[4] && d[5]) ? {4'h0, pc} : 16'hzzzz;
   assign dataout = (t[6] && d[6]) ? dr : 16'hzzzz;
 
-  assign display = (t[3] && d[7] && ir[10] && ir[15] && en_out) ? ac[7:0] : display;
+  assign en_out =   t[3] && d[7] && ir[10] && ir[15];
+  assign display = en_out ? ac[7:0] : display;
 
   DECODER decode2 (
     .d(d),

verilog/rtl/spi_master.v

diff --git a/verilog/rtl/spi_master.v b/verilog/rtl/spi_master.v
new file mode 100644
index 0000000..b3a2a8f
--- /dev/null
+++ b/verilog/rtl/spi_master.v
@@ -0,0 +1,47 @@
+module spi_master (
+  reset,
+  clock_in,
+  load,
+  unload,
+  datain,
+  dataout,
+  sclk,
+  miso,
+  mosi,
+  ssn
+);
+
+  input reset, clock_in, miso, load, unload;
+  input [7:0] datain;
+  output [7:0] dataout;
+  output sclk, mosi, ssn;
+
+  wire int_clk;
+  reg [7:0] datareg, dataout;
+  reg [2:0] cntreg;
+
+  assign mosi = datareg[7];
+  assign ssn = |cntreg;
+
+  always @(posedge clock_in or posedge reset) begin
+    if (reset) begin
+      datareg  <= 8'h00;
+    end else if (load) begin
+      datareg <= datain;
+    end else if (unload) begin
+      dataout <= datareg;
+    end else begin
+      datareg <= datareg << 1;
+      datareg[0] <= miso;
+    end
+  end
+
+  always @(posedge clock_in or posedge reset) begin
+    if (reset) begin
+      cntreg  <= 3'h0;
+    end else if (ssn || load) begin
+      cntreg  <= cntreg + 1;
+    end
+  end
+
+endmodule