| commit | c56cb101653433a4286e2e25a0295f9bed39886c | [log] [tgz] |
|---|---|---|
| author | Anton Blanchard <anton@linux.ibm.com> | Mon Jun 06 17:44:54 2022 +1000 |
| committer | Anton Blanchard <anton@ozlabs.org> | Mon Jun 06 17:44:54 2022 +1000 |
| tree | fb68eb89c77cab3b3c0a62efd67f81c004cd2f43 | |
| parent | b2c6eb30456fabf04e1e62608abf23accda8f778 [diff] |
Update register file config.tcl Instead of constraining the period of register file significantly more than the rest of the design, increase the input and output I/O delay so that top level logic and routing has more margin to play with.
