)]}'
{
  "commit": "c56cb101653433a4286e2e25a0295f9bed39886c",
  "tree": "fb68eb89c77cab3b3c0a62efd67f81c004cd2f43",
  "parents": [
    "b2c6eb30456fabf04e1e62608abf23accda8f778"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Mon Jun 06 17:44:54 2022 +1000"
  },
  "committer": {
    "name": "Anton Blanchard",
    "email": "anton@ozlabs.org",
    "time": "Mon Jun 06 17:44:54 2022 +1000"
  },
  "message": "Update register file config.tcl\n\nInstead of constraining the period of register file significantly more\nthan the rest of the design, increase the input and output I/O delay so\nthat top level logic and routing has more margin to play with.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0ed8cab13edc76e9aec73acc5574f2024aa73001",
      "old_mode": 33188,
      "old_path": "openlane/Microwatt_FP_DFFRFile/config.tcl",
      "new_id": "9de5f9772dab611eafb1d1e5117be26a48aef67c",
      "new_mode": 33188,
      "new_path": "openlane/Microwatt_FP_DFFRFile/config.tcl"
    }
  ]
}