tree fb68eb89c77cab3b3c0a62efd67f81c004cd2f43
parent b2c6eb30456fabf04e1e62608abf23accda8f778
author Anton Blanchard <anton@linux.ibm.com> 1654501494 +1000
committer Anton Blanchard <anton@ozlabs.org> 1654501494 +1000

Update register file config.tcl

Instead of constraining the period of register file significantly more
than the rest of the design, increase the input and output I/O delay so
that top level logic and routing has more margin to play with.