commit	883a958441d9b9048bf648caaacc800b0e3a6f67	[log] [tgz]
author	HexKotnk <gnadrag@gmail.com>	Thu Mar 17 19:28:03 2022 +0100
committer	HexKotnk <gnadrag@gmail.com>	Thu Mar 17 19:28:03 2022 +0100
tree	71f5b6f2d60a9041e3b0d2314564b06506100f61
parent	b3ac77dd3737f2aa461199484538fd91c363deed [diff]

Fibonacci counter commit

README.md[diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_project_wrapper/config.tcl[diff]
verilog/dv/Makefile[diff]
verilog/dv/count_test/Makefile[Added - diff]
verilog/dv/count_test/count_test.c[Added - diff]
verilog/dv/count_test/count_test.vvp[Added - diff]
verilog/dv/count_test/count_test_tb.v[Added - diff]
verilog/gl/user_proj_example.v[diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl _bak/c_elem.v[Added - diff]
verilog/rtl _bak/c_elem_xil.v[Added - diff]
verilog/rtl _bak/el_adder.v[Added - diff]
verilog/rtl _bak/el_adder_linked.v[Added - diff]
verilog/rtl _bak/el_counter.v[Added - diff]
verilog/rtl _bak/el_counter_tb.v[Added - diff]
verilog/rtl _bak/el_ed.v[Added - diff]
verilog/rtl _bak/el_fa.v[Added - diff]
verilog/rtl _bak/el_fa_fl.v[Added - diff]
verilog/rtl _bak/el_fa_tb.v[Added - diff]
verilog/rtl _bak/el_fib.v[Added - diff]
verilog/rtl _bak/el_fib_impl_top.v[Added - diff]
verilog/rtl _bak/el_fib_tb.v[Added - diff]
verilog/rtl _bak/el_header.vh[Added - diff]
verilog/rtl _bak/el_latch.v[Added - diff]
verilog/rtl _bak/el_link.v[Added - diff]
verilog/rtl _bak/el_min.v[Added - diff]
verilog/rtl _bak/el_pipeline.v[Added - diff]
verilog/rtl _bak/el_pipeline_tb.v[Added - diff]
verilog/rtl _bak/el_sync.v[Added - diff]
verilog/rtl _bak/el_t_mid.v[Added - diff]
verilog/rtl _bak/rs_lat.v[Added - diff]
verilog/rtl _bak/uprj_netlists.v[Added - diff]
verilog/rtl _bak/user_proj_example.v[Added - diff]
verilog/rtl _bak/user_project_wrapper.v[Added - diff]
verilog/rtl/c_elem.v[Added - diff]
verilog/rtl/c_elem_xil.v[Added - diff]
verilog/rtl/el_adder.v[Added - diff]
verilog/rtl/el_adder_linked.v[Added - diff]
verilog/rtl/el_counter.v[Added - diff]
verilog/rtl/el_counter_tb.v[Added - diff]
verilog/rtl/el_ed.v[Added - diff]
verilog/rtl/el_fa.v[Added - diff]
verilog/rtl/el_fa_fl.v[Added - diff]
verilog/rtl/el_fa_tb.v[Added - diff]
verilog/rtl/el_fib.v[Added - diff]
verilog/rtl/el_fib_impl_top.v[Added - diff]
verilog/rtl/el_fib_tb.v[Added - diff]
verilog/rtl/el_header.vh[Added - diff]
verilog/rtl/el_latch.v[Added - diff]
verilog/rtl/el_link.v[Added - diff]
verilog/rtl/el_min.v[Added - diff]
verilog/rtl/el_pipeline.v[Added - diff]
verilog/rtl/el_pipeline_tb.v[Added - diff]
verilog/rtl/el_sync.v[Added - diff]
verilog/rtl/el_t_mid.v[Added - diff]
verilog/rtl/rs_lat.v[Added - diff]
verilog/rtl/user_proj_example.v[diff]

59 files changed

tree: 71f5b6f2d60a9041e3b0d2314564b06506100f61

README.md

Caravel User Project

Async fibbonaci counter test