blob: 278e739634f91dc01b45653390ab3582f071f147 [file] [log] [blame]
Emre Goncu8ef4c9b2022-03-14 13:26:16 +03001# Caravel user project includes
2-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
3-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
4-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_interconnect.sv
5-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_stagging.sv
6-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuart.v
7-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuart.v
8-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuartlite.v
9-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuartlite.v
10-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/ufifo.v
11-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/skidbuffer.v
12-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/wbuart.v