UPDATE: fix some localparam issues that failed on iverilog
diff --git a/verilog/rtl/wbuart32/rxuart.v b/verilog/rtl/wbuart32/rxuart.v index 18966c8..43a2928 100644 --- a/verilog/rtl/wbuart32/rxuart.v +++ b/verilog/rtl/wbuart32/rxuart.v
@@ -89,12 +89,12 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module rxuart #( // {{{ // 8 data bits, no parity, (at least 1) stop bit - parameter [30:0] INITIAL_SETUP = 31'd868, + parameter [30:0] INITIAL_SETUP = 31'd868 // States: (@ baud counter == 0) // 0 First bit arrives // ..7 Bits arrive @@ -104,22 +104,6 @@ // d Waiting for the channel to go high // e Waiting for the reset to complete // f Idle state - localparam [3:0] RXU_BIT_ZERO = 4'h0, - RXU_BIT_ONE = 4'h1, - RXU_BIT_TWO = 4'h2, - RXU_BIT_THREE = 4'h3, - // RXU_BIT_FOUR = 4'h4, // UNUSED - // RXU_BIT_FIVE = 4'h5, // UNUSED - // RXU_BIT_SIX = 4'h6, // UNUSED - RXU_BIT_SEVEN = 4'h7, - RXU_PARITY = 4'h8, - RXU_STOP = 4'h9, - RXU_SECOND_STOP = 4'ha, - // Unused 4'hb - // Unused 4'hc - RXU_BREAK = 4'hd, - RXU_RESET_IDLE = 4'he, - RXU_IDLE = 4'hf // }}} ) ( // {{{ @@ -135,7 +119,22 @@ output wire o_ck_uart // }}} ); - + localparam [3:0] RXU_BIT_ZERO = 4'h0; + localparam [3:0] RXU_BIT_ONE = 4'h1; + localparam [3:0] RXU_BIT_TWO = 4'h2; + localparam [3:0] RXU_BIT_THREE = 4'h3; + //localparam [3:0] RXU_BIT_FOUR = 4'h4, // UNUSED + //localparam [3:0] RXU_BIT_FIVE = 4'h5, // UNUSED + //localparam [3:0] RXU_BIT_SIX = 4'h6, // UNUSED + localparam [3:0] RXU_BIT_SEVEN = 4'h7; + localparam [3:0] RXU_PARITY = 4'h8; + localparam [3:0] RXU_STOP = 4'h9; + localparam [3:0] RXU_SECOND_STOP = 4'ha; + //localparam [3:0] Unused 4'hb + //localparam [3:0] Unused 4'hc + localparam [3:0] RXU_BREAK = 4'hd; + localparam [3:0] RXU_RESET_IDLE = 4'he; + localparam [3:0] RXU_IDLE = 4'hf; // Signal declarations // {{{ wire [27:0] clocks_per_baud, break_condition, half_baud;
diff --git a/verilog/rtl/wbuart32/rxuartlite.v b/verilog/rtl/wbuart32/rxuartlite.v index 8063ed9..988b664 100644 --- a/verilog/rtl/wbuart32/rxuartlite.v +++ b/verilog/rtl/wbuart32/rxuartlite.v
@@ -46,7 +46,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module rxuartlite #( // {{{ @@ -54,24 +54,9 @@ `ifdef FORMAL parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof `else - parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, // 115200 MBaud at 100MHz + parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868 // 115200 MBaud at 100MHz `endif - localparam TB = TIMER_BITS, - // - localparam [3:0] RXUL_BIT_ZERO = 4'h0, - // Verilator lint_off UNUSED - // These are used by the formal solver - localparam [3:0] RXUL_BIT_ONE = 4'h1, - localparam [3:0] RXUL_BIT_TWO = 4'h2, - localparam [3:0] RXUL_BIT_THREE = 4'h3, - localparam [3:0] RXUL_BIT_FOUR = 4'h4, - localparam [3:0] RXUL_BIT_FIVE = 4'h5, - localparam [3:0] RXUL_BIT_SIX = 4'h6, - localparam [3:0] RXUL_BIT_SEVEN = 4'h7, - // Verilator lint_on UNUSED - localparam [3:0] RXUL_STOP = 4'h8, - localparam [3:0] RXUL_WAIT = 4'h9, - localparam [3:0] RXUL_IDLE = 4'hf + // }}} ) ( // {{{ @@ -82,6 +67,24 @@ // }}} ); + + localparam TB = TIMER_BITS; + // + localparam [3:0] RXUL_BIT_ZERO = 4'h0; + // Verilator lint_off UNUSED + // These are used by the formal solver + localparam [3:0] RXUL_BIT_ONE = 4'h1; + localparam [3:0] RXUL_BIT_TWO = 4'h2; + localparam [3:0] RXUL_BIT_THREE = 4'h3; + localparam [3:0] RXUL_BIT_FOUR = 4'h4; + localparam [3:0] RXUL_BIT_FIVE = 4'h5; + localparam [3:0] RXUL_BIT_SIX = 4'h6; + localparam [3:0] RXUL_BIT_SEVEN = 4'h7; + // Verilator lint_on UNUSED + localparam [3:0] RXUL_STOP = 4'h8; + localparam [3:0] RXUL_WAIT = 4'h9; + localparam [3:0] RXUL_IDLE = 4'hf; + // Signal/register declarations // {{{ wire [(TB-1):0] half_baud;
diff --git a/verilog/rtl/wbuart32/skidbuffer.v b/verilog/rtl/wbuart32/skidbuffer.v index fb0fc39..9ed3986 100644 --- a/verilog/rtl/wbuart32/skidbuffer.v +++ b/verilog/rtl/wbuart32/skidbuffer.v
@@ -80,7 +80,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module skidbuffer #( // {{{
diff --git a/verilog/rtl/wbuart32/txuart.v b/verilog/rtl/wbuart32/txuart.v index 5dc4040..dbc5cff 100644 --- a/verilog/rtl/wbuart32/txuart.v +++ b/verilog/rtl/wbuart32/txuart.v
@@ -93,27 +93,14 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // // }}} module txuart #( // {{{ - parameter [30:0] INITIAL_SETUP = 31'd868, + parameter [30:0] INITIAL_SETUP = 31'd868 // - localparam [3:0] TXU_BIT_ZERO = 4'h0, - localparam [3:0] TXU_BIT_ONE = 4'h1, - localparam [3:0] TXU_BIT_TWO = 4'h2, - localparam [3:0] TXU_BIT_THREE = 4'h3, - // localparam [3:0] TXU_BIT_FOUR = 4'h4, - // localparam [3:0] TXU_BIT_FIVE = 4'h5, - // localparam [3:0] TXU_BIT_SIX = 4'h6, - localparam [3:0] TXU_BIT_SEVEN = 4'h7, - localparam [3:0] TXU_PARITY = 4'h8, - localparam [3:0] TXU_STOP = 4'h9, - localparam [3:0] TXU_SECOND_STOP = 4'ha, - // - localparam [3:0] TXU_BREAK = 4'he, - localparam [3:0] TXU_IDLE = 4'hf + // }}} ) ( // {{{ @@ -135,6 +122,23 @@ // }}} ); + localparam [3:0] TXU_BIT_ZERO = 4'h0; + localparam [3:0] TXU_BIT_ONE = 4'h1; + localparam [3:0] TXU_BIT_TWO = 4'h2; + localparam [3:0] TXU_BIT_THREE = 4'h3; + // localparam [3:0] TXU_BIT_FOUR = 4'h4, + // localparam [3:0] TXU_BIT_FIVE = 4'h5, + // localparam [3:0] TXU_BIT_SIX = 4'h6, + localparam [3:0] TXU_BIT_SEVEN = 4'h7; + localparam [3:0] TXU_PARITY = 4'h8; + localparam [3:0] TXU_STOP = 4'h9; + localparam [3:0] TXU_SECOND_STOP = 4'ha; + // + localparam [3:0] TXU_BREAK = 4'he; + localparam [3:0] TXU_IDLE = 4'hf; + + + // Signal declarations // {{{ wire [27:0] clocks_per_baud, break_condition;
diff --git a/verilog/rtl/wbuart32/txuartlite.v b/verilog/rtl/wbuart32/txuartlite.v index d6fed00..05b19a1 100644 --- a/verilog/rtl/wbuart32/txuartlite.v +++ b/verilog/rtl/wbuart32/txuartlite.v
@@ -49,7 +49,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module txuartlite #( // {{{ @@ -58,7 +58,6 @@ // most baud rates, but you can trim it down to save logic if // you would like. TB is just an abbreviation for TIMING_BITS. parameter [4:0] TIMING_BITS = 5'd24, - localparam TB = TIMING_BITS, // CLOCKS_PER_BAUD -- the number of system clocks per baud // interval. parameter [(TB-1):0] CLOCKS_PER_BAUD = 8 // 24'd868 @@ -77,6 +76,8 @@ // }}} ); + localparam TB = TIMING_BITS; + // Register/net declarations // {{{ localparam [3:0] TXUL_BIT_ZERO = 4'h0,
diff --git a/verilog/rtl/wbuart32/ufifo.v b/verilog/rtl/wbuart32/ufifo.v index 39bbb48..a50519b 100644 --- a/verilog/rtl/wbuart32/ufifo.v +++ b/verilog/rtl/wbuart32/ufifo.v
@@ -43,14 +43,14 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module ufifo #( // {{{ parameter BW=8, // Byte/data width parameter [3:0] LGFLEN=4, - parameter [0:0] RXFIFO=1'b1, - localparam FLEN=(1<<LGFLEN) + parameter [0:0] RXFIFO=1'b1 + // }}} ) ( // {{{ @@ -65,6 +65,8 @@ // }}} ); + localparam FLEN=(1<<LGFLEN); + // Signal declarations // {{{ reg [(BW-1):0] fifo[0:(FLEN-1)];
diff --git a/verilog/rtl/wbuart32/wbuart.v b/verilog/rtl/wbuart32/wbuart.v index 95994bf..c37e86b 100644 --- a/verilog/rtl/wbuart32/wbuart.v +++ b/verilog/rtl/wbuart32/wbuart.v
@@ -39,7 +39,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} `define USE_LITE_UART module wbuart #( @@ -47,12 +47,11 @@ // 4MB 8N1, when using 100MHz clock parameter [30:0] INITIAL_SETUP = 31'd25, parameter [3:0] LGFLEN = 4, - parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1, + parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1 // Perform a simple/quick bounds check on the log FIFO length, // to make sure its within the bounds we can support with our // current interface. - localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha - : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN) + // }}} ) ( // {{{ @@ -76,6 +75,9 @@ // }}} ); + localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha + : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN); + localparam [1:0] UART_SETUP = 2'b00, UART_FIFO = 2'b01, UART_RXREG = 2'b10,