| # Caravel user project includes |
| -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v |
| -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v |
| -v $(USER_PROJECT_VERILOG)/rtl/simpleUART/simple_uart.v |
| #-v $(USER_PROJECT_VERILOG)/rtl/sram/sram_wb_wrapper.sv |
| -v $(USER_PROJECT_VERILOG)/rtl/sram/sram_wb_wrapper_xor.sv |
| -v $(USER_PROJECT_VERILOG)/rtl/aes/aes.v |
| -v $(USER_PROJECT_VERILOG)/rtl/security_monitor/lfsr.v |
| -v $(USER_PROJECT_VERILOG)/rtl/spi/tiny_spi.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/wb_interconnect.sv |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuart.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuart.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/rxuartlite.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/txuartlite.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/ufifo.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/skidbuffer.v |
| -v $(USER_PROJECT_VERILOG)/rtl/wbuart32/wbuart.v |
| -v $(USER_PROJECT_VERILOG)/rtl/sram/sky130_sram_1kbyte_1rw1r_32x256_8.v |
| -v $(USER_PROJECT_VERILOG)/rtl/trng/ringosc_macro.v |
| -v $(USER_PROJECT_VERILOG)/rtl/trng/trng_wb_wrapper.v |