update testbench
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index d5c2983..7e118c8 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -18,41 +18,43 @@
`timescale 1 ns / 1 ps
module wb_port_tb;
- reg clock;
- reg RSTB;
- reg CSB;
- reg power1, power2;
- reg power3, power4;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- wire [15:0] checkbits;
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+ wire [7:0] result;
- assign checkbits = mprj_io[31:16];
+ assign checkbits = mprj_io[31:16];
+ assign result = mprj_io[15:8];
- assign mprj_io[3] = 1'b1;
+ assign mprj_io[3] = 1'b1;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+ always #10.0 clock <= (clock === 1'b0);
- initial begin
- clock = 0;
- end
+ initial begin
+ clock = 0;
+ end
- initial begin
- $dumpfile("wb_port.vcd");
- $dumpvars(0, wb_port_tb);
+ initial begin
+ $dumpfile("wb_port.vcd");
+ $dumpvars(0, wb_port_tb);
- // Repeat cycles of 1000 clock edges as needed to complete testbench
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (70) begin
repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ // $display("+1000 cycles");
+ end
$display("%c[1;31m",27);
+ $display ("MPRJ_IO value : 0x%0h", mprj_io[31:0]);
`ifdef GL
$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
`else
@@ -62,86 +64,87 @@
$finish;
end
- initial begin
- wait(checkbits == 16'hAB60);
- $display("Monitor: MPRJ-Logic WB Started");
- wait(checkbits == 16'hAB61);
- `ifdef GL
- $display("Monitor: Mega-Project WB (GL) Passed");
- `else
- $display("Monitor: Mega-Project WB (RTL) Passed");
- `endif
- $finish;
- end
+ initial begin
+ wait(checkbits == 16'hAB60);
+ $display("Monitor: MPRJ-Logic WB Started");
+ wait(result == 8'h12);
+ $display ("MPRJ_IO value : 0x%0h", mprj_io[31:0]);
+ `ifdef GL
+ $display("Monitor: Mega-Project WB (GL) Passed");
+ `else
+ $display("Monitor: Mega-Project WB (RTL) Passed");
+ `endif
+ $finish;
+ end
- initial begin
- RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
- #2000;
- RSTB <= 1'b1; // Release reset
- #100000;
- CSB = 1'b0; // CSB can be released
- end
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #100000;
+ CSB = 1'b0; // CSB can be released
+ end
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
- caravel uut (
- .vddio (VDD3V3),
- .vddio_2 (VDD3V3),
- .vssio (VSS),
- .vssio_2 (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda1_2 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa1_2 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
- spiflash #(
- .FILENAME("wb_port.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
+ spiflash #(
+ .FILENAME("wb_port.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
endmodule
`default_nettype wire
\ No newline at end of file
