| /root/secure_memory/Makefile |
| /root/secure_memory/docs/Makefile |
| /root/secure_memory/docs/environment.yml |
| /root/secure_memory/docs/source/conf.py |
| /root/secure_memory/docs/source/index.rst |
| /root/secure_memory/docs/source/quickstart.rst |
| /root/secure_memory/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib |
| /root/secure_memory/lib/sky130_sram_1kbyte_1rw1r_8x1024_8_TT_1p8V_25C.lib |
| /root/secure_memory/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib |
| /root/secure_memory/openlane/Makefile |
| /root/secure_memory/openlane/trng_wb_wrapper/base.sdc |
| /root/secure_memory/openlane/trng_wb_wrapper/config.tcl |
| /root/secure_memory/openlane/user_proj_example/base.sdc |
| /root/secure_memory/openlane/user_proj_example/config.tcl |
| /root/secure_memory/openlane/user_project_wrapper/config.json |
| /root/secure_memory/openlane/user_project_wrapper/config.tcl |
| /root/secure_memory/openlane/user_project_wrapper/pdn.tcl |
| /root/secure_memory/spef/sram_wb_wrapper.spef |
| /root/secure_memory/verilog/dv/Makefile |
| /root/secure_memory/verilog/dv/io_ports/Makefile |
| /root/secure_memory/verilog/dv/io_ports/io_ports.c |
| /root/secure_memory/verilog/dv/io_ports/io_ports_tb.v |
| /root/secure_memory/verilog/dv/la_test1/Makefile |
| /root/secure_memory/verilog/dv/la_test1/la_test1.c |
| /root/secure_memory/verilog/dv/la_test1/la_test1_tb.v |
| /root/secure_memory/verilog/dv/la_test2/Makefile |
| /root/secure_memory/verilog/dv/la_test2/la_test2.c |
| /root/secure_memory/verilog/dv/la_test2/la_test2_tb.v |
| /root/secure_memory/verilog/dv/mprj_stimulus/Makefile |
| /root/secure_memory/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/secure_memory/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/secure_memory/verilog/dv/wb_sec_mon/Makefile |
| /root/secure_memory/verilog/dv/wb_sec_mon/seed.h |
| /root/secure_memory/verilog/dv/wb_sec_mon/wb_sec_mon.c |
| /root/secure_memory/verilog/dv/wb_sec_mon/wb_sec_mon_tb.v |
| /root/secure_memory/verilog/dv/wb_spi/Makefile |
| /root/secure_memory/verilog/dv/wb_spi/seed.h |
| /root/secure_memory/verilog/dv/wb_spi/wb_spi.c |
| /root/secure_memory/verilog/dv/wb_spi/wb_spi_tb.v |
| /root/secure_memory/verilog/dv/wb_sram/Makefile |
| /root/secure_memory/verilog/dv/wb_sram/seed.h |
| /root/secure_memory/verilog/dv/wb_sram/wb_sram.c |
| /root/secure_memory/verilog/dv/wb_sram/wb_sram_tb.v |
| /root/secure_memory/verilog/dv/wb_trng/Makefile |
| /root/secure_memory/verilog/dv/wb_trng/wb_trng.c |
| /root/secure_memory/verilog/dv/wb_trng/wb_trng_tb.v |
| /root/secure_memory/verilog/dv/wb_uart/Makefile |
| /root/secure_memory/verilog/dv/wb_uart/seed.h |
| /root/secure_memory/verilog/dv/wb_uart/wb_uart.c |
| /root/secure_memory/verilog/dv/wb_uart/wb_uart_tb.v |
| /root/secure_memory/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/secure_memory/verilog/includes/includes.gl.caravel_user_project |
| /root/secure_memory/verilog/includes/includes.rtl.caravel_user_project |
| /root/secure_memory/verilog/includes/includes.rtl.secure-memory |
| /root/secure_memory/verilog/rtl/uprj_netlists.v |
| /root/secure_memory/verilog/rtl/user_proj_example.v |
| /root/secure_memory/verilog/rtl/user_project_wrapper.v |
| /root/secure_memory/verilog/rtl/aes/aes.v |
| /root/secure_memory/verilog/rtl/security_monitor/lfsr.v |
| /root/secure_memory/verilog/rtl/simpleUART/simple_uart.v |
| /root/secure_memory/verilog/rtl/spi/tiny_spi.v |
| /root/secure_memory/verilog/rtl/sram/sky130_sram_1kbyte_1rw1r_32x256_8.v |
| /root/secure_memory/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/secure_memory/verilog/rtl/sram/sram_wb_wrapper.sv |
| /root/secure_memory/verilog/rtl/sram/sram_wb_wrapper_xor.sv |
| /root/secure_memory/verilog/rtl/trng/ring_osc2x13.v |
| /root/secure_memory/verilog/rtl/trng/ringosc_macro.v |
| /root/secure_memory/verilog/rtl/trng/trng_wb_wrapper.v |
| /root/secure_memory/verilog/rtl/wb_interconnect/wb_interconnect.sv |
| /root/secure_memory/verilog/rtl/wbuart32/rxuart.v |
| /root/secure_memory/verilog/rtl/wbuart32/rxuartlite.v |
| /root/secure_memory/verilog/rtl/wbuart32/skidbuffer.v |
| /root/secure_memory/verilog/rtl/wbuart32/txuart.v |
| /root/secure_memory/verilog/rtl/wbuart32/txuartlite.v |
| /root/secure_memory/verilog/rtl/wbuart32/ufifo.v |
| /root/secure_memory/verilog/rtl/wbuart32/wbuart.v |