commit c616beeb7d849c92f9b47b26584ee4a5062b01b7
author Sukru Uzun <sukru.uzun@procenne.com> Sun Mar 13 18:03:59 2022 +0300
committer Sukru Uzun <sukru.uzun@procenne.com> Sun Mar 13 18:03:59 2022 +0300
tree 90d1479931759cd4442f2cb109da4ce243c75e3b
parent 61aac8ccd5caef282d7ec53b748859a3a1397b3e

fix address range

verilog/rtl/wb_interconnect/wb_interconnect.sv

diff --git a/verilog/rtl/wb_interconnect/wb_interconnect.sv b/verilog/rtl/wb_interconnect/wb_interconnect.sv
index 426a3e0..05912ce 100644
--- a/verilog/rtl/wb_interconnect/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/wb_interconnect.sv
@@ -188,7 +188,7 @@
         if(m0_wb_stb_i && m0_wb_cyc_i && s_bus_rd_wb_ack == 0) begin
             // holding_busy    <= 1'b1;
             m0_wb_dat_i_reg <= m0_wb_dat_i;
-            m0_wb_adr_reg   <= {m0_wb_adr_i[31:2],2'b00};
+            m0_wb_adr_reg   <= {2'b00,m0_wb_adr_i[31:2]};
             m0_wb_sel_reg   <= m0_wb_sel_i;
             m0_wb_we_reg    <= m0_wb_we_i;
             m0_wb_cyc_reg   <= m0_wb_cyc_i;