FIX: TRNG
diff --git a/openlane/trng_wb_wrapper/config.tcl b/openlane/trng_wb_wrapper/config.tcl
index 00cc361..5632c51 100644
--- a/openlane/trng_wb_wrapper/config.tcl
+++ b/openlane/trng_wb_wrapper/config.tcl
@@ -51,7 +51,7 @@
set ::env(DESIGN_IS_CORE) 0
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 750 1000"
+set ::env(DIE_AREA) "0 0 900 1200"
set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.40
diff --git a/openlane/user_proj_example/base.sdc b/openlane/user_proj_example/base.sdc
new file mode 100644
index 0000000..fac5cd6
--- /dev/null
+++ b/openlane/user_proj_example/base.sdc
@@ -0,0 +1,48 @@
+# Randsack digital top macro timing constraints.
+#
+# SPDX-FileCopyrightText: (c) 2021 Harrison Pham <harrison@harrisonpham.com>
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+# } else {
+# create_clock -name VIRTUAL_CLK -period $::env(CLOCK_PERIOD)
+# set ::env(WB_CLOCK_PORT) VIRTUAL_CLK
+# }
+
+# set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+# set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+# puts "\[INFO\]: Setting output delay to: $output_delay_value"
+# puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+# set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+# set clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+# set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+# set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+# TODO set this as parameter
+# set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+# set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+# puts "\[INFO\]: Setting load to: $cap_load"
+# set_load $cap_load [all_outputs]
+
+# Extra clocks for macros.
+# NOTE: These don't need any input/output delays since this design just uses it for clock counting.
+set_false_path -from [get_pins wb_wrapper0/core.encdec] -to [get_pins wb_wrapper0/core/keymem.round[0]]
+set_false_path -from [get_pins wb_wrapper0/core.encdec] -to [get_pins wb_wrapper0.SRAM_data_next[31]]
+
+
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 64d972d..81e4e28 100644
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -1,6 +1,8 @@
# User config
set ::env(DESIGN_NAME) user_proj_example
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set script_dir [file dirname [file normalize [info script]]]
@@ -10,8 +12,11 @@
$::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/wb_interconnect.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/user_proj_example.v \
$::env(DESIGN_DIR)/../../verilog/rtl/sram/sram_wb_wrapper.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/aes/aes.v \
$::env(DESIGN_DIR)/../../verilog/rtl/simpleUART/simple_uart.v \
- $::env(DESIGN_DIR)/../../verilog/rtl/spi/tiny_spi.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl/spi/tiny_spi.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/security_monitor/lfsr.v"
+
# Fill this
@@ -36,7 +41,7 @@
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 800 1600"
+set ::env(DIE_AREA) "0 0 1500 1000"
#set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.50
diff --git a/verilog/dv/wb_trng/Makefile b/verilog/dv/wb_trng/Makefile
index 0121c39..46c6e6b 100644
--- a/verilog/dv/wb_trng/Makefile
+++ b/verilog/dv/wb_trng/Makefile
@@ -18,6 +18,9 @@
PWDD := $(shell pwd)
BLOCKS := $(shell basename $(PWDD))
+CARAVEL_PATH = $(CARAVEL_ROOT)
+CARAVEL_VERILOG_PATH = $(CARAVEL_ROOT)/verilog
+CONFIG = caravel_user_project
# ---- Include Partitioned Makefiles ----
diff --git a/verilog/rtl/sram/sram_wb_wrapper.sv b/verilog/rtl/sram/sram_wb_wrapper.sv
index b6a400c..7d38173 100644
--- a/verilog/rtl/sram/sram_wb_wrapper.sv
+++ b/verilog/rtl/sram/sram_wb_wrapper.sv
@@ -407,7 +407,7 @@
wire aes_init = (wr_busy) ? aes_init_wr : (rd_busy) ? aes_init_rd : 'h0 ;
wire aes_next = (wr_busy) ? aes_next_wr : (rd_busy) ? aes_next_rd : 'h0 ;
wire [127:0] aes_ptx = (wr_busy) ? aes_ptx_wr_reg : (rd_busy) ? aes_ptx_rd_reg : 'h0;
- wire enc_dec = (wr_busy) ? enc_dec_wr : (rd_busy) ? enc_dec_rd : 'h0 ;
+ wire enc_dec = (wr_busy) ? 1'b1 : (rd_busy) ? 1'b0 : 'h0 ;
aes_core core (
diff --git a/verilog/rtl/trng/trng_wb_wrapper.v b/verilog/rtl/trng/trng_wb_wrapper.v
index 1650c39..64edbf7 100644
--- a/verilog/rtl/trng/trng_wb_wrapper.v
+++ b/verilog/rtl/trng/trng_wb_wrapper.v
@@ -50,7 +50,7 @@
// Wishbone to TRNG signalization and vice versa.
assign read_trng = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_cyc_i == 1'b1) ? 1'b1 : 1'b0;
-assign wb_dat_o = (trng_valid_o == 1'b1 && read_trng == 1'b1) ? trng_buffer : 'h0;
+assign wb_dat_o = (trng_valid_o == 1'b1 && read_trng == 1'b1) ? trng_buffer_o : 'h0;
ringosc_macro #(.TRIM_BITS(26))
ringosc_macro_dut (
@@ -148,7 +148,7 @@
wb_ack_o <= 1'b0;
trng_valid_o <= 1'b0;
trng_counter <= 'h0;
- trng_buffer <= 'h0;
+ trng_buffer_o <= 'h0;
end
else begin
// TRNG signalization
@@ -171,7 +171,7 @@
trng_valid_o <= 1'b0;
end
- trng_buffer <= {trng_buffer[30:0],trng_o};
+ trng_buffer_o <= {trng_buffer_o[30:0],trng_o};
end
end
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 3942d06..b2e6506 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -192,7 +192,7 @@
.s2_wb_sel_o(),
.s2_wb_we_o (trng_wb_we_o),
.s2_wb_cyc_o(trng_wb_cyc_o),
- .s2_wb_stb_o(trng_wb_cyc_o),
+ .s2_wb_stb_o(trng_wb_stb_o),
// Slave 3 Interface
.s3_wb_dat_i(s3_wb_dat_o),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index f61c19e..2190831 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -146,9 +146,11 @@
.BUFFER_SIZE (BITS )
)
trng_wb_wrapper_dut (
- .vccd1 (vccd1 ),
- .vssd1 (vssd1 ),
- .rst_i (rst_i ),
+ `ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ), // User area 1 1.8V power
+ .vssd1 (vssd1 ), // User area 1 digital ground
+ `endif
+ .rst_i (wb_rst_i ),
.wb_clk_i (wb_clk_i ),
.wb_cyc_i (wb_cyc_i ),
.wb_stb_i (wb_stb_i ),
@@ -157,7 +159,7 @@
.wb_dat_i (wb_dat_i ),
.wb_dat_o (wb_dat_o ),
.wb_ack_o (wb_ack_o ),
- .trng_valid_o (trng_valid_o ),
+ .trng_valid_o (),
.trng_buffer_o ( trng_buffer_o)
);
diff --git a/vivado.jou b/vivado.jou
deleted file mode 100644
index d9a5e9c..0000000
--- a/vivado.jou
+++ /dev/null
@@ -1,99 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2018.3 (64-bit)
-# SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
-# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
-# Start of session at: Sun Mar 20 16:00:09 2022
-# Process ID: 223153
-# Current directory: /home/egoncu/workspace/secure-memory-uart
-# Command line: vivado
-# Log file: /home/egoncu/workspace/secure-memory-uart/vivado.log
-# Journal file: /home/egoncu/workspace/secure-memory-uart/vivado.jou
-#-----------------------------------------------------------
-start_gui
-create_project project_1 /home/egoncu/workspace/project_1 -part xc7vx485tffg1157-1
-file mkdir /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v w ]
-add_files /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v
-update_compile_order -fileset sources_1
-file mkdir /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v w ]
-add_files -fileset sim_1 /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v
-update_compile_order -fileset sources_1
-update_compile_order -fileset sim_1
-update_compile_order -fileset sim_1
-launch_simulation
-source aes128_tb.tcl
-relaunch_sim
-update_compile_order -fileset sim_1
-launch_simulation
-source aes.tcl
-run 1 us
-relaunch_sim
-current_sim simulation_1
-close_sim
-run all
-run all
-relaunch_sim
-run all
-run all
-close_sim
-launch_simulation
-source aes.tcl
-relaunch_sim
-close_sim
-# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top aes_tb [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-update_compile_order -fileset sim_1
-launch_simulation
-source aes_tb.tcl
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-relaunch_sim
-run 1 us
-relaunch_sim
-run 1 us
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v w ]
-add_files /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v
-update_compile_order -fileset sources_1
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb_lfsr.v w ]
-add_files -fileset sim_1 /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb_lfsr.v
-update_compile_order -fileset sim_1
-# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top LFSR_TB [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-update_compile_order -fileset sim_1
-launch_simulation
-launch_simulation
-source LFSR_TB.tcl
-synth_design -rtl -name rtl_1
-# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top LFSR [current_fileset]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-refresh_design
-update_compile_order -fileset sources_1
-refresh_design
-refresh_design
-refresh_design
-refresh_design
-refresh_design
-refresh_design
-close_sim
-close_sim
diff --git a/vivado.log b/vivado.log
deleted file mode 100644
index a96775f..0000000
--- a/vivado.log
+++ /dev/null
@@ -1,1465 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2018.3 (64-bit)
-# SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
-# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
-# Start of session at: Sun Mar 20 16:00:09 2022
-# Process ID: 223153
-# Current directory: /home/egoncu/workspace/secure-memory-uart
-# Command line: vivado
-# Log file: /home/egoncu/workspace/secure-memory-uart/vivado.log
-# Journal file: /home/egoncu/workspace/secure-memory-uart/vivado.jou
-#-----------------------------------------------------------
-start_gui
-create_project project_1 /home/egoncu/workspace/project_1 -part xc7vx485tffg1157-1
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2018.3/data/ip'.
-file mkdir /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v w ]
-add_files /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v
-update_compile_order -fileset sources_1
-file mkdir /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v w ]
-add_files -fileset sim_1 /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v
-update_compile_order -fileset sources_1
-update_compile_order -fileset sim_1
-update_compile_order -fileset sim_1
-launch_simulation
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes128_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes128_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes128
-INFO: [VRFC 10-311] analyzing module expand_key_128
-INFO: [VRFC 10-311] analyzing module one_round
-INFO: [VRFC 10-311] analyzing module final_round
-INFO: [VRFC 10-311] analyzing module S
-INFO: [VRFC 10-311] analyzing module xS
-INFO: [VRFC 10-311] analyzing module table_lookup
-INFO: [VRFC 10-311] analyzing module S4
-INFO: [VRFC 10-311] analyzing module T
-INFO: [VRFC 10-311] analyzing module S_table
-INFO: [VRFC 10-311] analyzing module xS_table
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes128_tb
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module glbl
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes128_tb_behav xil_defaultlib.aes128_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 17. Module aes128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 97. Module one_round doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-INFO: [Common 17-14] Message 'XSIM 43-4099' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.S
-Compiling module xil_defaultlib.S4
-Compiling module xil_defaultlib.expand_key_128
-Compiling module xil_defaultlib.xS
-Compiling module xil_defaultlib.T
-Compiling module xil_defaultlib.table_lookup
-Compiling module xil_defaultlib.one_round
-Compiling module xil_defaultlib.final_round
-Compiling module xil_defaultlib.aes128
-Compiling module xil_defaultlib.aes128_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes128_tb_behav
-
-****** Webtalk v2018.3 (64-bit)
- **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
- **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
- ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-
-source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/aes128_tb_behav/webtalk/xsim_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Sun Mar 20 16:03:40 2022...
-INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
- with args "aes128_tb_behav -key {Behavioral:sim_1:Functional:aes128_tb} -tclbatch {aes128_tb.tcl} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-source aes128_tb.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-# if { [llength [get_objects]] > 0} {
-# add_wave /
-# set_property needs_save false [current_wave_config]
-# } else {
-# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-# }
-# }
-# run 1000ns
-$finish called at time : 20 ns : File "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" Line 51
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes128_tb_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 1000ns
-launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 6703.629 ; gain = 68.848 ; free physical = 3396 ; free virtual = 17370
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes128_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes128_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes128
-INFO: [VRFC 10-311] analyzing module expand_key_128
-INFO: [VRFC 10-311] analyzing module one_round
-INFO: [VRFC 10-311] analyzing module final_round
-INFO: [VRFC 10-311] analyzing module S
-INFO: [VRFC 10-311] analyzing module xS
-INFO: [VRFC 10-311] analyzing module table_lookup
-INFO: [VRFC 10-311] analyzing module S4
-INFO: [VRFC 10-311] analyzing module T
-INFO: [VRFC 10-311] analyzing module S_table
-INFO: [VRFC 10-311] analyzing module xS_table
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes128_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes128_tb_behav xil_defaultlib.aes128_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 17. Module aes128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 97. Module one_round doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale.
-WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale.
-INFO: [Common 17-14] Message 'XSIM 43-4099' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.S
-Compiling module xil_defaultlib.S4
-Compiling module xil_defaultlib.expand_key_128
-Compiling module xil_defaultlib.xS
-Compiling module xil_defaultlib.T
-Compiling module xil_defaultlib.table_lookup
-Compiling module xil_defaultlib.one_round
-Compiling module xil_defaultlib.final_round
-Compiling module xil_defaultlib.aes128
-Compiling module xil_defaultlib.aes128_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes128_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 6727.602 ; gain = 0.000 ; free physical = 3408 ; free virtual = 17384
-update_compile_order -fileset sim_1
-launch_simulation
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_behav
-
-****** Webtalk v2018.3 (64-bit)
- **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
- **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
- ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-
-source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/aes_behav/webtalk/xsim_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Sun Mar 20 18:41:00 2022...
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
- with args "aes_behav -key {Behavioral:sim_1:Functional:aes} -tclbatch {aes.tcl} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-source aes.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-# if { [llength [get_objects]] > 0} {
-# add_wave /
-# set_property needs_save false [current_wave_config]
-# } else {
-# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-# }
-# }
-# run 1000ns
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 1000ns
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6855.473 ; gain = 60.836 ; free physical = 619 ; free virtual = 17333
-run 1 us
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_vlog.prj
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-current_sim simulation_1
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-run all
-run all
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_vlog.prj
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-run all
-run all
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-launch_simulation
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_vlog.prj
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
- with args "aes_behav -key {Behavioral:sim_1:Functional:aes} -tclbatch {aes.tcl} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-source aes.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-# if { [llength [get_objects]] > 0} {
-# add_wave /
-# set_property needs_save false [current_wave_config]
-# } else {
-# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-# }
-# }
-# run 1000ns
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 1000ns
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_vlog.prj
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '0' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-set_property top aes_tb [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-update_compile_order -fileset sim_1
-launch_simulation
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33]
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-
-****** Webtalk v2018.3 (64-bit)
- **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
- **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
- ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-
-source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/aes_tb_behav/webtalk/xsim_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Sun Mar 20 18:47:32 2022...
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
- with args "aes_tb_behav -key {Behavioral:sim_1:Functional:aes_tb} -tclbatch {aes_tb.tcl} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-source aes_tb.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-# if { [llength [get_objects]] > 0} {
-# add_wave /
-# set_property needs_save false [current_wave_config]
-# } else {
-# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-# }
-# }
-# run 1000ns
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes_tb_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 1000ns
-launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6855.473 ; gain = 0.000 ; free physical = 437 ; free virtual = 17167
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33]
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 6855.473 ; gain = 0.000 ; free physical = 490 ; free virtual = 17221
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33]
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33]
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33]
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33]
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [USF-XSim-69] 'compile' step finished in '0' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-run 1 us
-relaunch_sim
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj aes_tb_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes
-INFO: [VRFC 10-311] analyzing module aes_core
-INFO: [VRFC 10-311] analyzing module aes_decipher_block
-INFO: [VRFC 10-311] analyzing module aes_inv_sbox
-INFO: [VRFC 10-311] analyzing module aes_key_mem
-INFO: [VRFC 10-311] analyzing module aes_sbox
-INFO: [VRFC 10-311] analyzing module aes_encipher_block
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module aes_tb
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34]
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.aes_encipher_block
-Compiling module xil_defaultlib.aes_inv_sbox
-Compiling module xil_defaultlib.aes_decipher_block
-Compiling module xil_defaultlib.aes_key_mem
-Compiling module xil_defaultlib.aes_sbox
-Compiling module xil_defaultlib.aes_core
-Compiling module xil_defaultlib.aes_tb
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot aes_tb_behav
-INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-run 1 us
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v w ]
-add_files /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v
-update_compile_order -fileset sources_1
-set_property SOURCE_SET sources_1 [get_filesets sim_1]
-close [ open /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb_lfsr.v w ]
-add_files -fileset sim_1 /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb_lfsr.v
-update_compile_order -fileset sim_1
-set_property top LFSR_TB [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-update_compile_order -fileset sim_1
-launch_simulation
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'LFSR_TB' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj LFSR_TB_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module LFSR
-ERROR: [VRFC 10-1214] parameter initial value cannot be omitted in this mode of verilog [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
-ERROR: [VRFC 10-2865] module 'LFSR' ignored due to previous errors [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-99] Step results log file:'/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log'
-ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xvlog.log' file for more information.
-ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
-ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
-launch_simulation
-INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [SIM-utils-51] Simulation object is 'sim_1'
-INFO: [SIM-utils-54] Inspecting design source files for 'LFSR_TB' in fileset 'sim_1'...
-INFO: [USF-XSim-97] Finding global include files...
-INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
-INFO: [USF-XSim-2] XSim::Compile design
-INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-xvlog --incr --relax -prj LFSR_TB_vlog.prj
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module LFSR
-INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb_lfsr.v" into library xil_defaultlib
-INFO: [VRFC 10-311] analyzing module LFSR_TB
-INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
-INFO: [USF-XSim-3] XSim::Elaborate design
-INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-Vivado Simulator 2018.3
-Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot LFSR_TB_behav xil_defaultlib.LFSR_TB xil_defaultlib.glbl -log elaborate.log
-Using 8 slave threads.
-Starting static elaboration
-Completed static elaboration
-Starting simulation data flow analysis
-WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale.
-Completed simulation data flow analysis
-Time Resolution for simulation is 1ps
-Compiling module xil_defaultlib.LFSR
-Compiling module xil_defaultlib.LFSR_TB
-Compiling module xil_defaultlib.glbl
-Built simulation snapshot LFSR_TB_behav
-
-****** Webtalk v2018.3 (64-bit)
- **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
- **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
- ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-
-source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/LFSR_TB_behav/webtalk/xsim_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Mon Mar 21 00:04:53 2022...
-INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
-INFO: [USF-XSim-4] XSim::Simulate design
-INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim'
-INFO: [USF-XSim-98] *** Running xsim
- with args "LFSR_TB_behav -key {Behavioral:sim_1:Functional:LFSR_TB} -tclbatch {LFSR_TB.tcl} -log {simulate.log}"
-INFO: [USF-XSim-8] Loading simulator feature
-Vivado Simulator 2018.3
-Time resolution is 1 ps
-source LFSR_TB.tcl
-# set curr_wave [current_wave_config]
-# if { [string length $curr_wave] == 0 } {
-# if { [llength [get_objects]] > 0} {
-# add_wave /
-# set_property needs_save false [current_wave_config]
-# } else {
-# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
-# }
-# }
-# run 1000ns
-INFO: [USF-XSim-96] XSim completed. Design snapshot 'LFSR_TB_behav' loaded.
-INFO: [USF-XSim-97] XSim simulation ran for 1000ns
-synth_design -rtl -name rtl_1
-Command: synth_design -rtl -name rtl_1
-Starting synth_design
-Using part: xc7vx485tffg1157-1
-Top: aes
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7156.852 ; gain = 26.445 ; free physical = 820 ; free virtual = 16281
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'aes' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:39]
- Parameter ADDR_NAME0 bound to: 8'b00000000
- Parameter ADDR_NAME1 bound to: 8'b00000001
- Parameter ADDR_VERSION bound to: 8'b00000010
- Parameter ADDR_CTRL bound to: 8'b00001000
- Parameter CTRL_INIT_BIT bound to: 0 - type: integer
- Parameter CTRL_NEXT_BIT bound to: 1 - type: integer
- Parameter ADDR_STATUS bound to: 8'b00001001
- Parameter STATUS_READY_BIT bound to: 0 - type: integer
- Parameter STATUS_VALID_BIT bound to: 1 - type: integer
- Parameter ADDR_CONFIG bound to: 8'b00001010
- Parameter CTRL_ENCDEC_BIT bound to: 0 - type: integer
- Parameter CTRL_KEYLEN_BIT bound to: 1 - type: integer
- Parameter ADDR_KEY0 bound to: 8'b00010000
- Parameter ADDR_KEY7 bound to: 8'b00010111
- Parameter ADDR_BLOCK0 bound to: 8'b00100000
- Parameter ADDR_BLOCK3 bound to: 8'b00100011
- Parameter ADDR_RESULT0 bound to: 8'b00110000
- Parameter ADDR_RESULT3 bound to: 8'b00110011
- Parameter CORE_NAME0 bound to: 1634038560 - type: integer
- Parameter CORE_NAME1 bound to: 538976288 - type: integer
- Parameter CORE_VERSION bound to: 808334896 - type: integer
-INFO: [Synth 8-6157] synthesizing module 'aes_core' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:313]
- Parameter CTRL_IDLE bound to: 2'b00
- Parameter CTRL_INIT bound to: 2'b01
- Parameter CTRL_NEXT bound to: 2'b10
-INFO: [Synth 8-6157] synthesizing module 'aes_encipher_block' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:2261]
- Parameter AES_128_BIT_KEY bound to: 1'b0
- Parameter AES_256_BIT_KEY bound to: 1'b1
- Parameter AES128_ROUNDS bound to: 4'b1010
- Parameter AES256_ROUNDS bound to: 4'b1110
- Parameter NO_UPDATE bound to: 3'b000
- Parameter INIT_UPDATE bound to: 3'b001
- Parameter SBOX_UPDATE bound to: 3'b010
- Parameter MAIN_UPDATE bound to: 3'b011
- Parameter FINAL_UPDATE bound to: 3'b100
- Parameter CTRL_IDLE bound to: 3'b000
- Parameter CTRL_INIT bound to: 3'b001
- Parameter CTRL_SBOX bound to: 3'b010
- Parameter CTRL_MAIN bound to: 3'b011
- Parameter CTRL_FINAL bound to: 3'b100
-INFO: [Synth 8-6155] done synthesizing module 'aes_encipher_block' (1#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:2261]
-INFO: [Synth 8-6157] synthesizing module 'aes_decipher_block' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:653]
- Parameter AES_128_BIT_KEY bound to: 1'b0
- Parameter AES_256_BIT_KEY bound to: 1'b1
- Parameter AES128_ROUNDS bound to: 4'b1010
- Parameter AES256_ROUNDS bound to: 4'b1110
- Parameter NO_UPDATE bound to: 3'b000
- Parameter INIT_UPDATE bound to: 3'b001
- Parameter SBOX_UPDATE bound to: 3'b010
- Parameter MAIN_UPDATE bound to: 3'b011
- Parameter FINAL_UPDATE bound to: 3'b100
- Parameter CTRL_IDLE bound to: 3'b000
- Parameter CTRL_INIT bound to: 3'b001
- Parameter CTRL_SBOX bound to: 3'b010
- Parameter CTRL_MAIN bound to: 3'b011
- Parameter CTRL_FINAL bound to: 3'b100
-INFO: [Synth 8-6157] synthesizing module 'aes_inv_sbox' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1176]
-INFO: [Synth 8-6155] done synthesizing module 'aes_inv_sbox' (2#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1176]
-INFO: [Synth 8-6155] done synthesizing module 'aes_decipher_block' (3#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:653]
-INFO: [Synth 8-6157] synthesizing module 'aes_key_mem' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1502]
- Parameter AES_128_BIT_KEY bound to: 1'b0
- Parameter AES_256_BIT_KEY bound to: 1'b1
- Parameter AES_128_NUM_ROUNDS bound to: 10 - type: integer
- Parameter AES_256_NUM_ROUNDS bound to: 14 - type: integer
- Parameter CTRL_IDLE bound to: 3'b000
- Parameter CTRL_INIT bound to: 3'b001
- Parameter CTRL_GENERATE bound to: 3'b010
- Parameter CTRL_DONE bound to: 3'b011
-INFO: [Synth 8-226] default block is never used [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1695]
-WARNING: [Synth 8-5788] Register prev_key0_reg_reg in module aes_key_mem is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1623]
-WARNING: [Synth 8-5788] Register prev_key1_reg_reg in module aes_key_mem is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1626]
-INFO: [Synth 8-6155] done synthesizing module 'aes_key_mem' (4#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1502]
-INFO: [Synth 8-6157] synthesizing module 'aes_sbox' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1934]
-INFO: [Synth 8-6155] done synthesizing module 'aes_sbox' (5#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:1934]
-INFO: [Synth 8-6155] done synthesizing module 'aes_core' (6#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:313]
-INFO: [Synth 8-6155] done synthesizing module 'aes' (7#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v:39]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 7210.602 ; gain = 80.195 ; free physical = 815 ; free virtual = 16281
----------------------------------------------------------------------------------
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 7210.602 ; gain = 80.195 ; free physical = 819 ; free virtual = 16286
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 7210.602 ; gain = 80.195 ; free physical = 819 ; free virtual = 16286
----------------------------------------------------------------------------------
-INFO: [Device 21-403] Loading part xc7vx485tffg1157-1
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Completed Processing XDC Constraints
-
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 7718.266 ; gain = 0.000 ; free physical = 317 ; free virtual = 15889
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-RTL Elaboration Complete: : Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 7886.691 ; gain = 756.285 ; free physical = 271 ; free virtual = 15712
-19 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 7886.691 ; gain = 756.285 ; free physical = 270 ; free virtual = 15712
-set_property top LFSR [current_fileset]
-refresh_design
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 273 ; free virtual = 15678
----------------------------------------------------------------------------------
-ERROR: [Synth 8-439] module 'LFSR' not found
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 302 ; free virtual = 15707
----------------------------------------------------------------------------------
-RTL Elaboration failed
-ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
-update_compile_order -fileset sources_1
-refresh_design
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 261 ; free virtual = 15670
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
- Parameter NUM_BITS bound to: 32 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'LFSR' (1#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 276 ; free virtual = 15685
----------------------------------------------------------------------------------
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 278 ; free virtual = 15687
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 278 ; free virtual = 15687
----------------------------------------------------------------------------------
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Completed Processing XDC Constraints
-
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-refresh_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 283 ; free virtual = 15689
-refresh_design
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 315 ; free virtual = 15637
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
- Parameter NUM_BITS bound to: 32 - type: integer
-ERROR: [Synth 8-524] part-select [30:0] out of range of prefix 'r_LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:44]
-ERROR: [Synth 8-6156] failed synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 329 ; free virtual = 15651
----------------------------------------------------------------------------------
-RTL Elaboration failed
-ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
-refresh_design
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 313 ; free virtual = 15632
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
- Parameter NUM_BITS bound to: 32 - type: integer
-ERROR: [Synth 8-524] part-select [30:0] out of range of prefix 'r_LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:44]
-ERROR: [Synth 8-6156] failed synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 327 ; free virtual = 15646
----------------------------------------------------------------------------------
-RTL Elaboration failed
-ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
-refresh_design
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 280 ; free virtual = 15599
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
- Parameter NUM_BITS bound to: 32 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'LFSR' (1#1) [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 295 ; free virtual = 15614
----------------------------------------------------------------------------------
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
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-Start Handling Custom Attributes
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-Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 297 ; free virtual = 15616
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-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7886.691 ; gain = 0.000 ; free physical = 297 ; free virtual = 15616
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-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Completed Processing XDC Constraints
-
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-refresh_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 7930.230 ; gain = 43.539 ; free physical = 288 ; free virtual = 15608
-refresh_design
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-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7930.230 ; gain = 0.000 ; free physical = 555 ; free virtual = 15690
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
- Parameter NUM_BITS bound to: 32 - type: integer
-ERROR: [Synth 8-524] part-select [30:0] out of range of prefix 'r_LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:44]
-ERROR: [Synth 8-6156] failed synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7930.230 ; gain = 0.000 ; free physical = 563 ; free virtual = 15697
----------------------------------------------------------------------------------
-RTL Elaboration failed
-ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
-refresh_design
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-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 7930.230 ; gain = 0.000 ; free physical = 538 ; free virtual = 15672
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
- Parameter NUM_BITS bound to: 32 - type: integer
-ERROR: [Synth 8-524] part-select [30:0] out of range of prefix 'r_LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:44]
-ERROR: [Synth 8-6156] failed synthesizing module 'LFSR' [/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/lfsr.v:18]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7930.230 ; gain = 0.000 ; free physical = 549 ; free virtual = 15683
----------------------------------------------------------------------------------
-RTL Elaboration failed
-ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-close_sim
-INFO: [Simtcl 6-16] Simulation closed
-exit
-INFO: [Common 17-206] Exiting Vivado at Mon Mar 21 13:37:23 2022...
