| #----------------------------------------------------------- |
| # Vivado v2018.3 (64-bit) |
| # SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 |
| # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 |
| # Start of session at: Sun Mar 20 16:00:09 2022 |
| # Process ID: 223153 |
| # Current directory: /home/egoncu/workspace/secure-memory-uart |
| # Command line: vivado |
| # Log file: /home/egoncu/workspace/secure-memory-uart/vivado.log |
| # Journal file: /home/egoncu/workspace/secure-memory-uart/vivado.jou |
| #----------------------------------------------------------- |
| start_gui |
| create_project project_1 /home/egoncu/workspace/project_1 -part xc7vx485tffg1157-1 |
| INFO: [IP_Flow 19-234] Refreshing IP repositories |
| INFO: [IP_Flow 19-1704] No user IP repositories specified |
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2018.3/data/ip'. |
| file mkdir /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new |
| close [ open /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v w ] |
| add_files /home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v |
| update_compile_order -fileset sources_1 |
| file mkdir /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new |
| set_property SOURCE_SET sources_1 [get_filesets sim_1] |
| close [ open /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v w ] |
| add_files -fileset sim_1 /home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v |
| update_compile_order -fileset sources_1 |
| update_compile_order -fileset sim_1 |
| update_compile_order -fileset sim_1 |
| launch_simulation |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes128_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes128_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes128 |
| INFO: [VRFC 10-311] analyzing module expand_key_128 |
| INFO: [VRFC 10-311] analyzing module one_round |
| INFO: [VRFC 10-311] analyzing module final_round |
| INFO: [VRFC 10-311] analyzing module S |
| INFO: [VRFC 10-311] analyzing module xS |
| INFO: [VRFC 10-311] analyzing module table_lookup |
| INFO: [VRFC 10-311] analyzing module S4 |
| INFO: [VRFC 10-311] analyzing module T |
| INFO: [VRFC 10-311] analyzing module S_table |
| INFO: [VRFC 10-311] analyzing module xS_table |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes128_tb |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module glbl |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes128_tb_behav xil_defaultlib.aes128_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 17. Module aes128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 97. Module one_round doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| INFO: [Common 17-14] Message 'XSIM 43-4099' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.S |
| Compiling module xil_defaultlib.S4 |
| Compiling module xil_defaultlib.expand_key_128 |
| Compiling module xil_defaultlib.xS |
| Compiling module xil_defaultlib.T |
| Compiling module xil_defaultlib.table_lookup |
| Compiling module xil_defaultlib.one_round |
| Compiling module xil_defaultlib.final_round |
| Compiling module xil_defaultlib.aes128 |
| Compiling module xil_defaultlib.aes128_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes128_tb_behav |
| |
| ****** Webtalk v2018.3 (64-bit) |
| **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 |
| **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 |
| ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
| |
| source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/aes128_tb_behav/webtalk/xsim_webtalk.tcl -notrace |
| INFO: [Common 17-206] Exiting Webtalk at Sun Mar 20 16:03:40 2022... |
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds |
| INFO: [USF-XSim-4] XSim::Simulate design |
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-98] *** Running xsim |
| with args "aes128_tb_behav -key {Behavioral:sim_1:Functional:aes128_tb} -tclbatch {aes128_tb.tcl} -log {simulate.log}" |
| INFO: [USF-XSim-8] Loading simulator feature |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| source aes128_tb.tcl |
| # set curr_wave [current_wave_config] |
| # if { [string length $curr_wave] == 0 } { |
| # if { [llength [get_objects]] > 0} { |
| # add_wave / |
| # set_property needs_save false [current_wave_config] |
| # } else { |
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." |
| # } |
| # } |
| # run 1000ns |
| $finish called at time : 20 ns : File "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" Line 51 |
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes128_tb_behav' loaded. |
| INFO: [USF-XSim-97] XSim simulation ran for 1000ns |
| launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 6703.629 ; gain = 68.848 ; free physical = 3396 ; free virtual = 17370 |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes128_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes128_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes128 |
| INFO: [VRFC 10-311] analyzing module expand_key_128 |
| INFO: [VRFC 10-311] analyzing module one_round |
| INFO: [VRFC 10-311] analyzing module final_round |
| INFO: [VRFC 10-311] analyzing module S |
| INFO: [VRFC 10-311] analyzing module xS |
| INFO: [VRFC 10-311] analyzing module table_lookup |
| INFO: [VRFC 10-311] analyzing module S4 |
| INFO: [VRFC 10-311] analyzing module T |
| INFO: [VRFC 10-311] analyzing module S_table |
| INFO: [VRFC 10-311] analyzing module xS_table |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes128_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes128_tb_behav xil_defaultlib.aes128_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 17. Module aes128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 59. Module expand_key_128 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 342. Module S4 doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 97. Module one_round doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 327. Module table_lookup doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 355. Module T doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 165. Module S doesn't have a timescale but at least one module in design has a timescale. |
| WARNING: [XSIM 43-4099] "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" Line 305. Module xS doesn't have a timescale but at least one module in design has a timescale. |
| INFO: [Common 17-14] Message 'XSIM 43-4099' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.S |
| Compiling module xil_defaultlib.S4 |
| Compiling module xil_defaultlib.expand_key_128 |
| Compiling module xil_defaultlib.xS |
| Compiling module xil_defaultlib.T |
| Compiling module xil_defaultlib.table_lookup |
| Compiling module xil_defaultlib.one_round |
| Compiling module xil_defaultlib.final_round |
| Compiling module xil_defaultlib.aes128 |
| Compiling module xil_defaultlib.aes128_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes128_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 6727.602 ; gain = 0.000 ; free physical = 3408 ; free virtual = 17384 |
| update_compile_order -fileset sim_1 |
| launch_simulation |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_behav |
| |
| ****** Webtalk v2018.3 (64-bit) |
| **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 |
| **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 |
| ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
| |
| source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/aes_behav/webtalk/xsim_webtalk.tcl -notrace |
| INFO: [Common 17-206] Exiting Webtalk at Sun Mar 20 18:41:00 2022... |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| INFO: [USF-XSim-4] XSim::Simulate design |
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-98] *** Running xsim |
| with args "aes_behav -key {Behavioral:sim_1:Functional:aes} -tclbatch {aes.tcl} -log {simulate.log}" |
| INFO: [USF-XSim-8] Loading simulator feature |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| source aes.tcl |
| # set curr_wave [current_wave_config] |
| # if { [string length $curr_wave] == 0 } { |
| # if { [llength [get_objects]] > 0} { |
| # add_wave / |
| # set_property needs_save false [current_wave_config] |
| # } else { |
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." |
| # } |
| # } |
| # run 1000ns |
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes_behav' loaded. |
| INFO: [USF-XSim-97] XSim simulation ran for 1000ns |
| launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6855.473 ; gain = 60.836 ; free physical = 619 ; free virtual = 17333 |
| run 1 us |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_vlog.prj |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| current_sim simulation_1 |
| close_sim |
| INFO: [Simtcl 6-16] Simulation closed |
| run all |
| run all |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_vlog.prj |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| run all |
| run all |
| close_sim |
| INFO: [Simtcl 6-16] Simulation closed |
| launch_simulation |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_vlog.prj |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| INFO: [USF-XSim-4] XSim::Simulate design |
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-98] *** Running xsim |
| with args "aes_behav -key {Behavioral:sim_1:Functional:aes} -tclbatch {aes.tcl} -log {simulate.log}" |
| INFO: [USF-XSim-8] Loading simulator feature |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| source aes.tcl |
| # set curr_wave [current_wave_config] |
| # if { [string length $curr_wave] == 0 } { |
| # if { [llength [get_objects]] > 0} { |
| # add_wave / |
| # set_property needs_save false [current_wave_config] |
| # } else { |
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." |
| # } |
| # } |
| # run 1000ns |
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes_behav' loaded. |
| INFO: [USF-XSim-97] XSim simulation ran for 1000ns |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_vlog.prj |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_behav xil_defaultlib.aes xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| Completed static elaboration |
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel |
| INFO: [USF-XSim-69] 'elaborate' step finished in '0' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| close_sim |
| INFO: [Simtcl 6-16] Simulation closed |
| set_property top aes_tb [get_filesets sim_1] |
| set_property top_lib xil_defaultlib [get_filesets sim_1] |
| update_compile_order -fileset sim_1 |
| launch_simulation |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33] |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| |
| ****** Webtalk v2018.3 (64-bit) |
| **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 |
| **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 |
| ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. |
| |
| source /home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/aes_tb_behav/webtalk/xsim_webtalk.tcl -notrace |
| INFO: [Common 17-206] Exiting Webtalk at Sun Mar 20 18:47:32 2022... |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| INFO: [USF-XSim-4] XSim::Simulate design |
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-98] *** Running xsim |
| with args "aes_tb_behav -key {Behavioral:sim_1:Functional:aes_tb} -tclbatch {aes_tb.tcl} -log {simulate.log}" |
| INFO: [USF-XSim-8] Loading simulator feature |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| source aes_tb.tcl |
| # set curr_wave [current_wave_config] |
| # if { [string length $curr_wave] == 0 } { |
| # if { [llength [get_objects]] > 0} { |
| # add_wave / |
| # set_property needs_save false [current_wave_config] |
| # } else { |
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." |
| # } |
| # } |
| # run 1000ns |
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'aes_tb_behav' loaded. |
| INFO: [USF-XSim-97] XSim simulation ran for 1000ns |
| launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6855.473 ; gain = 0.000 ; free physical = 437 ; free virtual = 17167 |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33] |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 6855.473 ; gain = 0.000 ; free physical = 490 ; free virtual = 17221 |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33] |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33] |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33] |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 128 differs from formal bit length 256 for port 'key' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:33] |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [USF-XSim-69] 'compile' step finished in '0' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| run 1 us |
| relaunch_sim |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [SIM-utils-51] Simulation object is 'sim_1' |
| INFO: [SIM-utils-54] Inspecting design source files for 'aes_tb' in fileset 'sim_1'... |
| INFO: [USF-XSim-97] Finding global include files... |
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... |
| INFO: [USF-XSim-2] XSim::Compile design |
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| xvlog --incr --relax -prj aes_tb_vlog.prj |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sources_1/new/aes.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes |
| INFO: [VRFC 10-311] analyzing module aes_core |
| INFO: [VRFC 10-311] analyzing module aes_decipher_block |
| INFO: [VRFC 10-311] analyzing module aes_inv_sbox |
| INFO: [VRFC 10-311] analyzing module aes_key_mem |
| INFO: [VRFC 10-311] analyzing module aes_sbox |
| INFO: [VRFC 10-311] analyzing module aes_encipher_block |
| INFO: [VRFC 10-2263] Analyzing Verilog file "/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v" into library xil_defaultlib |
| INFO: [VRFC 10-311] analyzing module aes_tb |
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds |
| INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| INFO: [USF-XSim-3] XSim::Elaborate design |
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim' |
| Vivado Simulator 2018.3 |
| Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. |
| Running: /tools/Xilinx/Vivado/2018.3/bin/unwrapped/lnx64.o/xelab -wto d15e9ad086eb4733bafd2c3fb4aa35cd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot aes_tb_behav xil_defaultlib.aes_tb xil_defaultlib.glbl -log elaborate.log |
| Using 8 slave threads. |
| Starting static elaboration |
| WARNING: [VRFC 10-3091] actual bit length 2 differs from formal bit length 1 for port 'keylen' [/home/egoncu/workspace/project_1/project_1.srcs/sim_1/new/tb.v:34] |
| Completed static elaboration |
| Starting simulation data flow analysis |
| WARNING: [XSIM 43-4100] "/home/egoncu/workspace/project_1/project_1.sim/sim_1/behav/xsim/glbl.v" Line 6. Module glbl has a timescale but at least one module in design doesn't have timescale. |
| Completed simulation data flow analysis |
| Time Resolution for simulation is 1ps |
| Compiling module xil_defaultlib.aes_encipher_block |
| Compiling module xil_defaultlib.aes_inv_sbox |
| Compiling module xil_defaultlib.aes_decipher_block |
| Compiling module xil_defaultlib.aes_key_mem |
| Compiling module xil_defaultlib.aes_sbox |
| Compiling module xil_defaultlib.aes_core |
| Compiling module xil_defaultlib.aes_tb |
| Compiling module xil_defaultlib.glbl |
| Built simulation snapshot aes_tb_behav |
| INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds |
| Vivado Simulator 2018.3 |
| Time resolution is 1 ps |
| run 1 us |
