update testbench
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 4f59055..e575fcd 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -19,40 +19,45 @@
#include <defs.h>
#include <stub.c>
+// User Project Slaves (0x3000_0000)
+#define sram_offset (*(volatile uint32_t*)0x30000000)
+
/*
- Wishbone Test:
- - Configures MPRJ lower 8-IO pins as outputs
- - Checks counter value through the wishbone port
+ Wishbone Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Checks counter value through the wishbone port
*/
void main()
{
- /*
- IO Control Registers
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
- Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-
-
- Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
- | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
- | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
- */
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
- /* Set up the housekeeping SPI to be connected internally so */
- /* that external pin changes don't affect it. */
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ int number_of_test = 5;
+ int fail = 0;
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
reg_spi_enable = 1;
reg_wb_enable = 1;
- // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
- // Connect the housekeeping SPI to the SPI master
- // so that the CSB line is not left floating. This allows
- // all of the GPIO pins to be used for user functions.
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -70,18 +75,42 @@
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
- /* Apply configuration */
+ /* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
// Flag start of the test
- reg_mprj_datal = 0xAB600000;
+ reg_mprj_datal = 0xAB600000;
- reg_mprj_slave = 0x00002710;
- if (reg_mprj_slave == 0x2B3D) {
- reg_mprj_datal = 0xAB610000;
+ // sram_offset = 0x11223344;
+ // *((&sram_offset)+1) = 0x11234758;
+
+ // if (sram_offset == 0x11223344){
+ // if (*((&sram_offset)+1) == 0x11234758)
+ // reg_mprj_datal = 0x0000FF00;
+ // }
+
+ // Write software Write & Read Register
+ for(int i = 0; i < number_of_test; i++){
+ *((&sram_offset)+i) = 0x11223344 + i;
}
+
+ // reg_mprj_datal = 0x0000FF00 - (0x100 * number_of_test);
+ for(int i = 0; i < number_of_test; i++){
+ if (*((&sram_offset)+i) != (0x11223344 + i))
+ fail = 1;
+ }
+ if (fail == 0)
+ reg_mprj_datal = 0x0000FF00;
}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 7e118c8..d3afb48 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -49,12 +49,12 @@
$dumpvars(0, wb_port_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (70) begin
+ repeat (100) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("MPRJ_IO value : 0x%0h", mprj_io[31:0]);
+ $display ("MPRJ_IO value : 0x%0h", mprj_io[31:8]);
`ifdef GL
$display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
`else
@@ -67,7 +67,7 @@
initial begin
wait(checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
- wait(result == 8'h12);
+ wait(result == 8'hFF);
$display ("MPRJ_IO value : 0x%0h", mprj_io[31:0]);
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Passed");
