commit 1fa178db9879860e512da854877f23dbf3ba2354
author Sukru Uzun <sukru.uzun@procenne.com> Sun Mar 13 13:50:29 2022 +0300
committer Sukru Uzun <sukru.uzun@procenne.com> Sun Mar 13 13:50:29 2022 +0300
tree fc1e1156b2a9257213fb71703b8d816fdd6350dd
parent ce8efcb69f821adf7527f613068d142d19fc5a90

enable verbose

verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v

diff --git a/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 289a770..7da4327 100644
--- a/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -20,7 +20,7 @@
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
   parameter DELAY = 3 ;
-  parameter VERBOSE = 0 ; //Set to 0 to only display warnings
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
   parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
 
 `ifdef USE_POWER_PINS