mpw_precheck/logs/spdx_compliance_report.log

/root/uetrv-ecore/Makefile
/root/uetrv-ecore/docs/Makefile
/root/uetrv-ecore/docs/environment.yml
/root/uetrv-ecore/docs/source/conf.py
/root/uetrv-ecore/docs/source/index.rst
/root/uetrv-ecore/docs/source/quickstart.rst
/root/uetrv-ecore/gds/(UNNAMED).ext
/root/uetrv-ecore/mag/tmp/extract_BMem.tcl
/root/uetrv-ecore/openlane/Core/config.tcl
/root/uetrv-ecore/openlane/Motor_Top/config.tcl
/root/uetrv-ecore/openlane/Wishbone_InterConnect/config.tcl
/root/uetrv-ecore/openlane/user_proj_example/config.json
/root/uetrv-ecore/openlane/user_proj_example/config.tcl
/root/uetrv-ecore/openlane/user_project_wrapper/config.json
/root/uetrv-ecore/openlane/user_project_wrapper/config.tcl
/root/uetrv-ecore/sdc/Core.sdc
/root/uetrv-ecore/sdc/Motor_Top.sdc
/root/uetrv-ecore/sdc/WB_InterConnect.sdc
/root/uetrv-ecore/sdc/user_proj_example.sdc
/root/uetrv-ecore/sdc/user_project_wrapper.sdc
/root/uetrv-ecore/sdf/Core.sdf
/root/uetrv-ecore/sdf/Motor_Top.sdf
/root/uetrv-ecore/sdf/WB_InterConnect.sdf
/root/uetrv-ecore/sdf/user_proj_example.sdf
/root/uetrv-ecore/sdf/user_project_wrapper.sdf
/root/uetrv-ecore/spef/Core.spef
/root/uetrv-ecore/spef/Motor_Top.spef
/root/uetrv-ecore/spef/WB_InterConnect.spef
/root/uetrv-ecore/spef/user_proj_example.spef
/root/uetrv-ecore/spef/user_project_wrapper.spef
/root/uetrv-ecore/verilog/dv/Makefile
/root/uetrv-ecore/verilog/dv/io_ports/Makefile
/root/uetrv-ecore/verilog/dv/io_ports/io_ports.c
/root/uetrv-ecore/verilog/dv/io_ports/io_ports_tb.v
/root/uetrv-ecore/verilog/dv/la_test1/Makefile
/root/uetrv-ecore/verilog/dv/la_test1/la_test1.c
/root/uetrv-ecore/verilog/dv/la_test1/la_test1_tb.v
/root/uetrv-ecore/verilog/dv/la_test2/Makefile
/root/uetrv-ecore/verilog/dv/la_test2/la_test2.c
/root/uetrv-ecore/verilog/dv/la_test2/la_test2_tb.v
/root/uetrv-ecore/verilog/dv/mprj_stimulus/Makefile
/root/uetrv-ecore/verilog/dv/mprj_stimulus/mprj_stimulus.c
/root/uetrv-ecore/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
/root/uetrv-ecore/verilog/dv/wb_port/Makefile
/root/uetrv-ecore/verilog/dv/wb_port/wb_port.c
/root/uetrv-ecore/verilog/dv/wb_port/wb_port_tb.v
/root/uetrv-ecore/verilog/rtl/Core.v
/root/uetrv-ecore/verilog/rtl/Motor_Top.v
/root/uetrv-ecore/verilog/rtl/WB_InterConnect.v
/root/uetrv-ecore/verilog/rtl/uprj_netlists.v
/root/uetrv-ecore/verilog/rtl/user_proj_example.v
/root/uetrv-ecore/verilog/rtl/user_project_wrapper.v