commit	a73cee2c8c36eb01d8a42b878b89670e69911960	[log] [tgz]
author	EmJunaid <2018ee71@student.uet.edu.pk>	Sun Mar 20 23:54:50 2022 +0500
committer	EmJunaid <2018ee71@student.uet.edu.pk>	Sun Mar 20 23:54:50 2022 +0500
tree	90390b6470d20f93545fe2ac0277b60a0fde432c
parent	2076e1b060ecb77b4ed5adad0227c3288fed871a [diff]

Update for DRC

Intermediate/Core/runs/Core/OPENLANE_VERSION[Deleted - diff]
Intermediate/Core/runs/Core/PDK_SOURCES[Deleted - diff]
Intermediate/Core/runs/Core/cmds.log[Deleted - diff]
Intermediate/Core/runs/Core/config.tcl[Deleted - diff]
Intermediate/Core/runs/Core/logs/cts/11-cts.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/cts/12-write_verilog.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/cts/13-resizer.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/cts/14-write_verilog.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/28-gds_ptrs.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/28-gdsii.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/28-lef.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/28-maglef.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/29-gdsii-klayout.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/30-xor.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/31-ext2spice.feedback.txt[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/31-spice.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/32-write_powered_def.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/34-Core.lef.json[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/34-Core.lef.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/34-Core.lvs.lef.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/34-lef.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/35-drc.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/36-antenna.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/finishing/37-erc_screen.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/floorplan/3-initial_fp.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/floorplan/4-place_io_ol.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/floorplan/5-tap.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/floorplan/6-pdn.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/placement/10-detailed.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/placement/7-global.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/placement/8-resizer.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/placement/9-write_verilog.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/15-diodes.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/16-diode_legalization.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/17-write_verilog.with_diodes.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/18-fill.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/19-global.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/20-write_verilog_global.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/21-detailed.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/22-write_verilog_detailed.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/23-parasitics_extraction.tt.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/24-parasitics_extraction.ss.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/25-parasitics_extraction.ff.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/26-parasitics_sta.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/routing/27-parasitics_multi_corner_sta.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/synthesis/1-synthesis.log[Deleted - diff]
Intermediate/Core/runs/Core/logs/synthesis/2-sta.log[Deleted - diff]
Intermediate/Core/runs/Core/openlane.log[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/11-cts_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.power.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.slew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/cts/13-resizer_sta.worst_slack.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/final_summary_report.csv[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/30-xor.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/Core.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/Core.rpt.debug.gz[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/Core.rpt.error.gz[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/Core.xor.gds[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/Core.xor.xml[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/antenna.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/drc.klayout.xml[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/drc.rdb[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/drc.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/drc.tcl[Deleted - diff]
Intermediate/Core/runs/Core/reports/finishing/drc.tr[Deleted - diff]
Intermediate/Core/runs/Core/reports/floorplan/3-initial_fp_core_area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/floorplan/3-initial_fp_die_area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/manufacturability_report.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/7-global_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/7-global_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/7-global_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/7-global_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/7-global_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/7-global_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.power.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.slew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/placement/8-resizer_sta.worst_slack.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/19-groute_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/19-groute_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/19-groute_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/19-groute_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/19-groute_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/19-groute_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.power.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.slew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/26-parasitics_sta.worst_slack.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.power.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.slew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/27-parasitics_multi_corner_sta.worst_slack.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/detailed.drc[Deleted - diff]
Intermediate/Core/runs/Core/reports/routing/detailed.klayout.xml[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/1-synthesis.chk.rpt.strategy4[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/1-synthesis.stat.rpt.strategy4[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/1-synthesis_dff.stat[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/1-synthesis_pre.stat[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.area.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.clock_skew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.max.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.min.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.power.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.slew.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.tns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.wns.rpt[Deleted - diff]
Intermediate/Core/runs/Core/reports/synthesis/2-synthesis_sta.worst_slack.rpt[Deleted - diff]
Intermediate/Core/runs/Core/results/cts/Core.def[Deleted - diff]
Intermediate/Core/runs/Core/results/cts/Core.resized.v[Deleted - diff]
Intermediate/Core/runs/Core/results/cts/Core.sdc[Deleted - diff]
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Intermediate/Core/runs/Core/results/final/def/Core.def[Deleted - diff]
Intermediate/Core/runs/Core/results/final/gds/Core.gds[Deleted - diff]
Intermediate/Core/runs/Core/results/final/lef/Core.lef[Deleted - diff]
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Intermediate/Core/runs/Core/results/final/maglef/Core.mag[Deleted - diff]
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Intermediate/Core/runs/Core/results/final/verilog/gl/Core.v[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/.magicrc[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.drc.mag[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.gds[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.klayout.gds[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.lef[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.lef.mag[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.lef.spice[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.lyp[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.mag[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.magic.gds[Deleted - diff]
Intermediate/Core/runs/Core/results/finishing/Core.spice[Deleted - diff]
Intermediate/Core/runs/Core/results/floorplan/Core.def[Deleted - diff]
Intermediate/Core/runs/Core/results/placement/Core.def[Deleted - diff]
Intermediate/Core/runs/Core/results/placement/Core.resized.v[Deleted - diff]
Intermediate/Core/runs/Core/results/routing/Core.def[Deleted - diff]
Intermediate/Core/runs/Core/results/routing/Core.ff.spef[Deleted - diff]
Intermediate/Core/runs/Core/results/routing/Core.sdf[Deleted - diff]
Intermediate/Core/runs/Core/results/routing/Core.ss.spef[Deleted - diff]
Intermediate/Core/runs/Core/results/routing/Core.tt.spef[Deleted - diff]
Intermediate/Core/runs/Core/results/synthesis/Core.v[Deleted - diff]
Intermediate/Core/runs/Core/results/synthesis/Core_diodes.v[Deleted - diff]
Intermediate/Core/runs/Core/runtime.yaml[Deleted - diff]
Intermediate/Core/runs/Core/tmp/cts/13-resizer_timing.def[Deleted - diff]
Intermediate/Core/runs/Core/tmp/cts/13-resizer_timing.sdc[Deleted - diff]
Intermediate/Core/runs/Core/tmp/cts/cts.lib[Deleted - diff]
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Intermediate/Core/runs/Core/tmp/dimensions.txt[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/31-powered_def.def[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/31-powered_netlist.v[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/34-setup_file.lef.lvs[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/Core.cdl[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/Core.ext[Deleted - diff]
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Intermediate/Core/runs/Core/tmp/finishing/gds_ptrs.mag[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/sky130_fd_sc_hd__a2111o_1.ext[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/sky130_fd_sc_hd__a2111o_4.ext[Deleted - diff]
Intermediate/Core/runs/Core/tmp/finishing/sky130_fd_sc_hd__a211o_1.ext[Deleted - diff]
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Intermediate/Motor_Top/runs/Motor_Top/tmp/merged_unpadded.lef[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/placement/7-global.def[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/placement/8-resizer.def[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/placement/8-resizer.sdc[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/15-diodes.def[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/18-fill.def[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/19-global.def[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/19-global.guide[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/19-global.v[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/21-detailed.v[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/config.tracks[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/routing/detailed.guide[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/hierarchy.dot[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/merged.lib[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/post_techmap.dot[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/resizer_opt.exclude.list[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/resizer_sky130_fd_sc_hd__tt_025C_1v80.lib[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/synthesis.sdc[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/trimmed.lib[Deleted - diff]
Intermediate/Motor_Top/runs/Motor_Top/tmp/synthesis/trimmed.lib.exclude.list[Deleted - diff]
Makefile[diff]
openlane/Core/config.tcl[Renamed from Intermediate/Core/config.tcl - diff]
openlane/Core/pin_order.cfg[Renamed from Intermediate/Core/pin_order.cfg - diff]
openlane/Motor_Top/config.tcl[Renamed from Intermediate/Motor_Top/config.tcl - diff]
openlane/Motor_Top/pin_order.cfg[Renamed from Intermediate/Motor_Top/pin_order.cfg - diff]
openlane/Wishbone_InterConnect/config.tcl[Renamed from Intermediate/Wishbone_InterConnect/config.tcl - diff]
openlane/Wishbone_InterConnect/pin_order.cfg[Renamed from Intermediate/Wishbone_InterConnect/pin_order.cfg - diff]
openlane/user_proj_example/config.json[Renamed from Intermediate/user_proj_example/config.json - diff]
openlane/user_proj_example/config.tcl[Renamed from Intermediate/user_proj_example/config.tcl - diff]
openlane/user_proj_example/pin_order.cfg[Renamed from Intermediate/user_proj_example/pin_order.cfg - diff]

490 files changed

tree: 90390b6470d20f93545fe2ac0277b60a0fde432c

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.