| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/home/kasirga/c0_hayyan/GL_GECTI/caravel_user_project/openlane/c0_system,c0_system,c0_system,flow completed,0h36m39s0ms,0h22m33s0ms,18849.704142011837,1.69,9424.852071005918,9.5,6572.88,15928,0,0,0,0,0,0,0,57,0,0,-1,1459968,161421,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1224892611.0,0.0,28.97,25.38,8.07,11.16,-1,13558,24665,578,11551,0,0,0,15739,276,9,366,536,2327,729,156,4122,2114,2127,36,938,23314,0,24252,20.0,50.0,50,AREA 0,5,50,1,153.6,153.18,0.19,0.3,sky130_fd_sc_hd,4,4 |
