commit: b063f479d16d3d5e67fbfad0d70fbea1e54bdf13
[log] [tgz]
author: gatecat <gatecat@ds0.me>
Fri Nov 05 18:16:35 2021 +0000
committer: gatecat <gatecat@ds0.me>
Tue Dec 21 13:09:48 2021 +0000
tree: 6546bad6b79e10a471aa6d2e68f288ed7760d695
parent: 769fafe529654763697acd2bd83d54befbe2ed50 [diff]

Add README

Signed-off-by: gatecat <gatecat@ds0.me>

README.md[diff]

1 file changed

tree: 6546bad6b79e10a471aa6d2e68f288ed7760d695

README.md

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

Minerva RV32IM CPU
512 bytes SRAM
(Q)SPI flash for code and data memory using spimemio from picosoc
HyperRAM for RAM extension using a derivative of litehyperbus
8-bit GPIO
UART, timer, and interrupt controller

Built using:

nMigen
Yosys+ABC
Coriolis for PnR; with PDKMaster and flexcell used in place of the standard sky130 cells.