commit: 769fafe529654763697acd2bd83d54befbe2ed50
[log] [tgz]
author: gatecat <gatecat@ds0.me>
Fri Nov 05 18:12:18 2021 +0000
committer: gatecat <gatecat@ds0.me>
Fri Nov 05 18:12:18 2021 +0000
tree: cecdfe4939164d7433a9efbc0d1264a6bb1976a2
parent: dfc479e2bde9546bf63da55866c9fe3959bdc79f [diff]

Remove example project

Signed-off-by: gatecat <gatecat@ds0.me>

def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
openlane/.gitignore[Deleted - diff]
openlane/Makefile[Deleted - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/config.tcl[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/config.json[Deleted - diff]
openlane/user_project_wrapper/config.tcl[Deleted - diff]
openlane/user_project_wrapper/macro.cfg[Deleted - diff]
openlane/user_project_wrapper/pin_order.cfg[Deleted - diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/dv/Makefile[Deleted - diff]
verilog/dv/README.md[Deleted - diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[Deleted - diff]
verilog/rtl/uprj_netlists.v[Deleted - diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[Deleted - diff]

39 files changed

tree: cecdfe4939164d7433a9efbc0d1264a6bb1976a2

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.