qf105: openlane: update configs/verilog
diff --git a/openlane/mkLanaiCPU/config.tcl b/openlane/mkLanaiCPU/config.tcl
index ecf2697..a73a8f9 100755
--- a/openlane/mkLanaiCPU/config.tcl
+++ b/openlane/mkLanaiCPU/config.tcl
@@ -54,8 +54,8 @@
set ::env(DESIGN_IS_CORE) 0
set ::env(USE_ARC_ANTENNA_CHECK) 1
-set ::env(VDD_NETS) [list {VPWR}]
-set ::env(GND_NETS) [list {VGND}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
set ::env(ROUTING_CORES) 12
diff --git a/openlane/mkLanaiCPU/pin_order.cfg b/openlane/mkLanaiCPU/pin_order.cfg
index 438dd45..38d9366 100644
--- a/openlane/mkLanaiCPU/pin_order.cfg
+++ b/openlane/mkLanaiCPU/pin_order.cfg
@@ -4,10 +4,8 @@
CPU
RST_N
-#W
-.*dmem.*
-
#N
+.*dmem.*
.*imem.*
#E
diff --git a/openlane/mkQF100Fabric/config.tcl b/openlane/mkQF100Fabric/config.tcl
index 0c794dd..5430103 100755
--- a/openlane/mkQF100Fabric/config.tcl
+++ b/openlane/mkQF100Fabric/config.tcl
@@ -30,11 +30,11 @@
set ::env(CLOCK_NET) "CLK"
set ::env(CLOCK_PERIOD) "20"
-#set ::env(FP_SIZING) absolute
-#set ::env(DIE_AREA) "0 0 500 500"
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 500 300"
-set ::env(FP_SIZING) relative
-set ::env(FP_CORE_UTIL) "30"
+#set ::env(FP_SIZING) relative
+#set ::env(FP_CORE_UTIL) "30"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -54,8 +54,8 @@
set ::env(RT_MAX_LAYER) {met4}
# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {VPWR}]
-set ::env(GND_NETS) [list {VGND}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
set ::env(DIODE_INSERTION_STRATEGY) 2
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 2
diff --git a/openlane/mkQF100Fabric/pin_order.cfg b/openlane/mkQF100Fabric/pin_order.cfg
index aa43f3c..f4d4fee 100644
--- a/openlane/mkQF100Fabric/pin_order.cfg
+++ b/openlane/mkQF100Fabric/pin_order.cfg
@@ -1,33 +1,10 @@
#BUS_SORT
-#S
+#W
CLK
RST_N
-cpu_cyc_.*
-cpu_stb_.*
-cpu_sel_.*
-cpu_ack_.*
-cpu_err_.*
-cpu_rty_.*
-cpu_adr_.*
-cpu_dat_.*
+cpu.*
#N
-spi_cyc_.*
-spi_stb_.*
-spi_sel_.*
-spi_ack_.*
-spi_err_.*
-spi_rty_.*
-spi_adr_.*
-spi_dat_.*
-
-#W
-gpio_cyc_.*
-gpio_stb_.*
-gpio_sel_.*
-gpio_ack_.*
-gpio_err_.*
-gpio_rty_.*
-gpio_adr_.*
-gpio_dat_.*
+spi.*
+gpio.*
diff --git a/openlane/mkQF100GPIO/config.tcl b/openlane/mkQF100GPIO/config.tcl
index 6209ad5..c5b640b 100755
--- a/openlane/mkQF100GPIO/config.tcl
+++ b/openlane/mkQF100GPIO/config.tcl
@@ -30,8 +30,11 @@
set ::env(CLOCK_NET) "CLK"
set ::env(CLOCK_PERIOD) "10"
-set ::env(FP_SIZING) relative
-set ::env(FP_CORE_UTIL) "40"
+#set ::env(FP_SIZING) relative
+#set ::env(FP_CORE_UTIL) "40"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 200 250"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -51,8 +54,8 @@
set ::env(RT_MAX_LAYER) {met4}
# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {VPWR}]
-set ::env(GND_NETS) [list {VGND}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
#set ::env(DIODE_INSERTION_STRATEGY) 2
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 2
diff --git a/openlane/mkQF100GPIO/pin_order.cfg b/openlane/mkQF100GPIO/pin_order.cfg
index ec85995..c230af8 100644
--- a/openlane/mkQF100GPIO/pin_order.cfg
+++ b/openlane/mkQF100GPIO/pin_order.cfg
@@ -5,7 +5,7 @@
RST_N
slave.*
-#E
+#N
oe.*
out.*
in.*
diff --git a/openlane/mkQF100Memory/config.tcl b/openlane/mkQF100Memory/config.tcl
index 2043294..c525ed2 100755
--- a/openlane/mkQF100Memory/config.tcl
+++ b/openlane/mkQF100Memory/config.tcl
@@ -54,8 +54,8 @@
set ::env(RT_MAX_LAYER) {met4}
# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {VPWR}]
-set ::env(GND_NETS) [list {VGND}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
set ::env(DIODE_INSERTION_STRATEGY) 4
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/mkQF100SPI/config.tcl b/openlane/mkQF100SPI/config.tcl
index 588dbed..4b0d77b 100755
--- a/openlane/mkQF100SPI/config.tcl
+++ b/openlane/mkQF100SPI/config.tcl
@@ -30,8 +30,10 @@
set ::env(CLOCK_NET) "CLK"
set ::env(CLOCK_PERIOD) "10"
-set ::env(FP_SIZING) relateive
-set ::env(FP_CORE_UTIL) "50"
+#set ::env(FP_SIZING) relative
+#set ::env(FP_CORE_UTIL) "50"
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 200 250"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
@@ -51,8 +53,8 @@
set ::env(RT_MAX_LAYER) {met4}
# You can draw more power domains if you need to
-set ::env(VDD_NETS) [list {VPWR}]
-set ::env(GND_NETS) [list {VGND}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
#set ::env(DIODE_INSERTION_STRATEGY) 2
#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 2
diff --git a/openlane/mkQF100SPI/pin_order.cfg b/openlane/mkQF100SPI/pin_order.cfg
index 891f368..0580837 100644
--- a/openlane/mkQF100SPI/pin_order.cfg
+++ b/openlane/mkQF100SPI/pin_order.cfg
@@ -12,5 +12,5 @@
slave_adr_.*
slave_dat_.*
-#E
+#N
spiMaster_.*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 4b136f7..5b6b9d4 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -35,7 +35,6 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/ResetInverter.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v \
$script_dir/../../verilog/rtl/mkQF105.v"
@@ -43,7 +42,7 @@
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "20"
## Internal Macros
### Macro PDN Connections
@@ -59,18 +58,21 @@
$script_dir/../../verilog/rtl/mkLanaiCPU.v \
$script_dir/../../verilog/rtl/mkQF100Fabric.v \
$script_dir/../../verilog/rtl/mkQF100Memory.v \
+ $script_dir/../../verilog/rtl/mkQF100GPIO.v \
$script_dir/../../verilog/rtl/mkQF100SPI.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/mkLanaiCPU.lef \
$script_dir/../../lef/mkQF100Fabric.lef \
$script_dir/../../lef/mkQF100Memory.lef \
+ $script_dir/../../lef/mkQF100GPIO.lef \
$script_dir/../../lef/mkQF100SPI.lef"
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/mkLanaiCPU.gds \
$script_dir/../../gds/mkQF100Fabric.gds \
$script_dir/../../gds/mkQF100Memory.gds \
+ $script_dir/../../gds/mkQF100GPIO.gds \
$script_dir/../../gds/mkQF100SPI.gds"
# set ::env(GLB_RT_MAXLAYER) 5
@@ -80,7 +82,7 @@
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
-set ::env(PL_TARGET_DENSITY) "0.1"
+set ::env(PL_TARGET_DENSITY) "0.10"
# The following is because there are no std cells in the example wrapper project.
#set ::env(SYNTH_TOP_LEVEL) 1
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index edd53fe..a61adab 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,4 +1,5 @@
-qf105.res_cpu 500 500 N # 962x973
-qf105.res_mem 500 1800 N # 348x359
-qf105.res_fabric 1800 500 N # 500x200
-qf105.res_spi 1800 800 N # 146x157
+qf105.res_cpu 500 500 N # 962x973
+qf105.res_mem 500 1600 N # 348x359
+qf105.res_fabric 2000 500 N # 500x300
+qf105.res_spi 2000 1600 N # 200x250
+qf105.res_gpio 2400 1600 N # 200x250
diff --git a/verilog/rtl/mkLanaiCPU.v b/verilog/rtl/mkLanaiCPU.v
index 3b2ccd5..a90a2d2 100644
--- a/verilog/rtl/mkLanaiCPU.v
+++ b/verilog/rtl/mkLanaiCPU.v
@@ -2260,14 +2260,14 @@
(* src = "bazel-out/k8-fastbuild/bin/lanai/Lanai_CPU/mkLanaiCPU.v:70.1-3291.10" *)
module mkLanaiCPU(
`ifdef USE_POWER_PINS
- VPWR,
- VGND,
+ vccd1,
+ vssd1,
`endif
CLK, RST_N, EN_dmem_client_request_get, dmem_client_request_get, RDY_dmem_client_request_get, dmem_client_response_put, EN_dmem_client_response_put, RDY_dmem_client_response_put, EN_imem_client_request_get, imem_client_request_get, RDY_imem_client_request_get, imem_client_response_put, EN_imem_client_response_put, RDY_imem_client_response_put, sysmem_client_cyc_o, sysmem_client_stb_o, sysmem_client_adr_o, sysmem_client_dat_o, sysmem_client_sel_o, sysmem_client_we_o, sysmem_client_ack_i
, sysmem_client_err_i, sysmem_client_rty_i, sysmem_client_dat_i, readPC, RDY_readPC);
`ifdef USE_POWER_PINS
- inout VPWR;
- inout VGND;
+ inout vccd1;
+ inout vssd1;
`endif
reg \$auto$verilog_backend.cc:2083:dump_module$2161 = 0;
(* src = "bazel-out/k8-fastbuild/bin/lanai/Lanai_CPU/mkLanaiCPU.v:2593.3-2655.6" *)
diff --git a/verilog/rtl/mkQF100Fabric.v b/verilog/rtl/mkQF100Fabric.v
index 32ab7ca..1ff30dc 100644
--- a/verilog/rtl/mkQF100Fabric.v
+++ b/verilog/rtl/mkQF100Fabric.v
@@ -5,14 +5,14 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Fabric.v:159.1-903.10" *)
module mkQF100Fabric(
`ifdef USE_POWER_PINS
- VPWR,
- VGND,
+ vccd1,
+ vssd1,
`endif
CLK, RST_N, cpu_cyc_i, cpu_stb_i, cpu_adr_i, cpu_dat_i, cpu_sel_i, cpu_we_i, cpu_ack_o, cpu_err_o, cpu_rty_o, cpu_dat_o, spi_cyc_o, spi_stb_o, spi_adr_o, spi_dat_o, spi_sel_o, spi_we_o, spi_ack_i, spi_err_i, spi_rty_i
, spi_dat_i, gpio_cyc_o, gpio_stb_o, gpio_adr_o, gpio_dat_o, gpio_sel_o, gpio_we_o, gpio_ack_i, gpio_err_i, gpio_rty_i, gpio_dat_i);
`ifdef USE_POWER_PINS
- inout VPWR;
- inout VGND;
+ inout vccd1;
+ inout vssd1;
`endif
reg \$auto$verilog_backend.cc:2083:dump_module$182 = 0;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Fabric.v:827.3-883.6" *)
diff --git a/verilog/rtl/mkQF100GPIO.v b/verilog/rtl/mkQF100GPIO.v
index 2c0ebc3..2b395ba 100644
--- a/verilog/rtl/mkQF100GPIO.v
+++ b/verilog/rtl/mkQF100GPIO.v
@@ -5,13 +5,13 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100GPIO.v:42.1-1159.10" *)
module mkQF100GPIO(
`ifdef USE_POWER_PINS
- VPWR,
- VGND,
+ vccd1,
+ vssd1,
`endif
CLK, RST_N, slave_cyc_i, slave_stb_i, slave_adr_i, slave_dat_i, slave_sel_i, slave_we_i, slave_ack_o, slave_err_o, slave_rty_o, slave_dat_o, oe, out, in);
`ifdef USE_POWER_PINS
- inout VPWR;
- inout VGND;
+ inout vccd1;
+ inout vssd1;
`endif
reg \$auto$verilog_backend.cc:2083:dump_module$360 = 0;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100GPIO.v:936.3-946.6" *)
diff --git a/verilog/rtl/mkQF100Memory.v b/verilog/rtl/mkQF100Memory.v
index 26fc768..7979e8e 100644
--- a/verilog/rtl/mkQF100Memory.v
+++ b/verilog/rtl/mkQF100Memory.v
@@ -2136,13 +2136,13 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:42.1-647.10" *)
module mkQF100Memory(
`ifdef USE_POWER_PINS
- VPWR,
- VGND,
+ vccd1,
+ vssd1,
`endif
CLK, RST_N, memory_imem_request_put, EN_memory_imem_request_put, RDY_memory_imem_request_put, EN_memory_imem_response_get, memory_imem_response_get, RDY_memory_imem_response_get, memory_dmem_request_put, EN_memory_dmem_request_put, RDY_memory_dmem_request_put, EN_memory_dmem_response_get, memory_dmem_response_get, RDY_memory_dmem_response_get);
`ifdef USE_POWER_PINS
- inout VPWR;
- inout VGND;
+ inout vccd1;
+ inout vssd1;
`endif
reg \$auto$verilog_backend.cc:2083:dump_module$280 = 0;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100Memory.v:533.3-564.6" *)
diff --git a/verilog/rtl/mkQF100SPI.v b/verilog/rtl/mkQF100SPI.v
index bdc76a9..d399381 100644
--- a/verilog/rtl/mkQF100SPI.v
+++ b/verilog/rtl/mkQF100SPI.v
@@ -5,13 +5,13 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100SPI.v:43.1-908.10" *)
module mkQF100SPI(
`ifdef USE_POWER_PINS
- VPWR,
- VGND,
+ vccd1,
+ vssd1,
`endif
CLK, RST_N, slave_cyc_i, slave_stb_i, slave_adr_i, slave_dat_i, slave_sel_i, slave_we_i, slave_ack_o, slave_err_o, slave_rty_o, slave_dat_o, spiMaster_sclk, spiMaster_mosi, spiMaster_miso, spiMaster_mosi_oe);
`ifdef USE_POWER_PINS
- inout VPWR;
- inout VGND;
+ inout vccd1;
+ inout vssd1;
`endif
reg \$auto$verilog_backend.cc:2083:dump_module$205 = 0;
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF100SPI.v:710.3-722.6" *)
diff --git a/verilog/rtl/mkQF105.v b/verilog/rtl/mkQF105.v
index 155aaa4..9f9d398 100644
--- a/verilog/rtl/mkQF105.v
+++ b/verilog/rtl/mkQF105.v
@@ -20,13 +20,13 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:36.1-379.10" *)
module mkQF105(
`ifdef USE_POWER_PINS
- VPWR,
- VGND,
+ vccd1,
+ vssd1,
`endif
wb_clk_i, wb_rst_i, la_data_in, la_oenb, la_data_out, io_in, io_out, io_oeb, irq);
`ifdef USE_POWER_PINS
- inout VPWR;
- inout VGND;
+ inout vccd1;
+ inout vssd1;
`endif
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:318.7-319.42" *)
wire _00_;
@@ -268,8 +268,8 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:195.14-220.22" *)
mkLanaiCPU res_cpu (
`ifdef USE_POWER_PINS
- .VPWR(VPWR),
- .VGND(VGND),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
`endif
.CLK(wb_clk_i),
.EN_dmem_client_request_get(\res_cpu$EN_dmem_client_request_get ),
@@ -300,8 +300,8 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:223.17-254.40" *)
mkQF100Fabric res_fabric (
`ifdef USE_POWER_PINS
- .VPWR(VPWR),
- .VGND(VGND),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
`endif
.CLK(wb_clk_i),
.RST_N(\reset_n$RESET_OUT ),
@@ -340,8 +340,8 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:257.15-271.29" *)
mkQF100GPIO res_gpio (
`ifdef USE_POWER_PINS
- .VPWR(VPWR),
- .VGND(VGND),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
`endif
.CLK(wb_clk_i),
.RST_N(\reset_n$RESET_OUT ),
@@ -363,8 +363,8 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:274.17-287.72" *)
mkQF100Memory res_mem (
`ifdef USE_POWER_PINS
- .VPWR(VPWR),
- .VGND(VGND),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
`endif
.CLK(wb_clk_i),
.EN_memory_dmem_request_put(\res_mem$EN_memory_dmem_request_put ),
@@ -385,8 +385,8 @@
(* src = "bazel-out/k8-fastbuild/bin/boards/qf100/QF100/mkQF105.v:290.14-305.29" *)
mkQF100SPI res_spi (
`ifdef USE_POWER_PINS
- .VPWR(VPWR),
- .VGND(VGND),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
`endif
.CLK(wb_clk_i),
.RST_N(\reset_n$RESET_OUT ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index be58eb3..0966905 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -84,8 +84,8 @@
mkQF105 qf105(
`ifdef USE_POWER_PINS
- .VPWR(vccd1), // User area 1 1.8V power
- .VGND(vssd1), // User area 1 digital ground
+ .vccd1(vccd1), // User area 1 1.8V power
+ .vssd1(vssd1), // User area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
