commit	65afea9f33a88905cfb4b15d6e7412f2af06bdce	[log] [tgz]
author	Rameen Anwar <ramianwer1996@gmail.com>	Fri Mar 18 06:03:37 2022 -0700
committer	Rameen Anwar <ramianwer1996@gmail.com>	Fri Mar 18 06:03:37 2022 -0700
tree	1b045c929832d345c0467cb7b62d4c5ce8a2f437
parent	2bf5b4338746cf6a799c7118cb86a6ed3d9acabd [diff]

Placed modified RTL and Gate level netlist in respective folders

3 files changed

tree: 1b045c929832d345c0467cb7b62d4c5ce8a2f437

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md

README.md

Azadi-III

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, QSPI and timer.