updated with MCLk period and gps_engine verilog files

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4f420af..f4eef7e 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -36,23 +36,25 @@
 	$script_dir/../../verilog/rtl/user_proj_example.v"
 	
 set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PORT_MCLK) "mclk"
 set ::env(CLOCK_NET) "wb_clk_i"
 set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD_MCLK) "175"
 
 set ::env(DESIGN_IS_CORE) 0
 set ::env(FP_PDN_CORE_RING) 0
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
 
 set ::env(SYNTH_MAX_FANOUT) 6
 set ::env(FP_CORE_UTIL) 20
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+4) / 100.0 ]
 set ::env(CELL_PAD) 4
 
-set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(DIODE_INSERTION_STRATEGY) 4
 #set ::env(SYNTH_STRATEGY) 2
 #set ::env(SYNTH_STRATEGY) "DELAY 1"
 set ::env(SYNTH_NO_FLAT) 0
@@ -61,4 +63,5 @@
 
 set ::env(MAGIC_DRC_USE_GDS) 1
 set ::env(LVS_INSERT_POWER_PINS) 1
-
+set ::env(RUN_CVC) 1
+set ::env(GLB_RT_ALLOW_CONGESTION) 1