updated code
diff --git a/verilog/rtl/gps_engine/codectrllogic.v b/verilog/rtl/gps_engine/codectrllogic.v
index 293ddd8..3f07daa 100644
--- a/verilog/rtl/gps_engine/codectrllogic.v
+++ b/verilog/rtl/gps_engine/codectrllogic.v
@@ -53,7 +53,9 @@
pnl,
epochrx,
code_sel,
-epoch
+epoch,
+irnss_sel,
+irnss_code
);
input res, nco_cod_clk1p0m, nco_cod_clk2p0m, acq;
@@ -63,6 +65,8 @@
output epochrx;
input [4:0] code_sel;
input epoch;
+input irnss_sel;
+input [10:1] irnss_code;
wire res;
wire nco_cod_clk1p0m;
@@ -92,7 +96,9 @@
code_sel,
pne,
pnp,
- pnl);
+ pnl,
+ irnss_sel,
+ irnss_code);
assign epoch1 = ~((epoch));
always @(negedge res or posedge nco_cod_clk2p0m) begin
diff --git a/verilog/rtl/gps_engine/codegen.v b/verilog/rtl/gps_engine/codegen.v
index c2f8bca..2dae782 100644
--- a/verilog/rtl/gps_engine/codegen.v
+++ b/verilog/rtl/gps_engine/codegen.v
@@ -42,7 +42,9 @@
code_sel,
pne,
pnp,
-pnl
+pnl,
+irnss_sel,
+irnss_code
);
input res, ncoclk, codeclk;
@@ -50,6 +52,8 @@
output epochrx;
input [4:0] code_sel;
output pne, pnp, pnl;
+input irnss_sel;
+input [10:1] irnss_code;
wire res;
wire ncoclk;
@@ -80,7 +84,9 @@
.car_change(car_change),
.epochrx(epochrx),
.code_sel(code_sel),
- .goldcode(prncode));
+ .goldcode(prncode),
+ .irnss_sel(irnss_sel),
+ .irnss_code(irnss_code));
always @(negedge res or posedge codeclk) begin
if(res == 1'b 0) begin
diff --git a/verilog/rtl/gps_engine/defines.v b/verilog/rtl/gps_engine/defines.v
new file mode 100644
index 0000000..9c3120c
--- /dev/null
+++ b/verilog/rtl/gps_engine/defines.v
@@ -0,0 +1,62 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`ifndef __GLOBAL_DEFINE_H
+// Global parameters
+`define __GLOBAL_DEFINE_H
+
+`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
+`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
+`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
+
+`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
+`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
+`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
+
+// Analog pads are only used by the "caravan" module and associated
+// modules such as user_analog_project_wrapper and chip_io_alt.
+
+`define ANALOG_PADS_1 5
+`define ANALOG_PADS_2 6
+
+`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
+
+// Size of soc_mem_synth
+
+// Type and size of soc_mem
+// `define USE_OPENRAM
+`define USE_CUSTOM_DFFRAM
+// don't change the following without double checking addr widths
+`define MEM_WORDS 256
+
+// Number of columns in the custom memory; takes one of three values:
+// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
+`define DFFRAM_WSIZE 4
+`define DFFRAM_USE_LATCH 0
+
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 2
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
+
+// GPIO conrol default mode and enable
+`define DM_INIT 3'b110
+`define OENB_INIT 1'b1
+
+`endif // __GLOBAL_DEFINE_H
diff --git a/verilog/rtl/gps_engine/goldcode.v b/verilog/rtl/gps_engine/goldcode.v
index 2aab9d5..fb7ac19 100644
--- a/verilog/rtl/gps_engine/goldcode.v
+++ b/verilog/rtl/gps_engine/goldcode.v
@@ -39,7 +39,9 @@
code_sel,
goldcode,
gold1,
-gold2
+gold2,
+irnss_sel,
+irnss_code
);
input reset, clk;
@@ -47,6 +49,8 @@
output epochrx;
input [4:0] code_sel;
output goldcode, gold1, gold2;
+input irnss_sel;
+input [10:1] irnss_code;
wire reset;
wire clk;
@@ -84,13 +88,15 @@
epochrx <= 1'b 0;
end
end
+ wire [10:1] code_wire;
+ assign code_wire = irnss_sel==1'b0 ? 10'b 1111111111 : irnss_code;
always @(negedge reset or posedge clk or posedge car_change) begin
if(reset == 1'b 0) begin
- g2codereg <= 10'b 1111111111;
+ g2codereg <= code_wire;
end
else if(car_change == 1'b 1) begin
- g2codereg <= 10'b 1111111111;
+ g2codereg <= code_wire;
end
else begin
g2codereg[1] <= g2codereg[2] ^ g2codereg[3] ^ g2codereg[6] ^ g2codereg[8] ^ g2codereg[9] ^ g2codereg[10];
@@ -106,172 +112,178 @@
end
else begin
// goldcode<='1';
- case(code_sel)
- 5'b 00001 : begin
- g2out <= g2codereg[2] ^ g2codereg[6];
+ if(irnss_sel == 1'b0) begin
+ case(code_sel)
+ 5'b 00001 : begin
+ g2out <= g2codereg[2] ^ g2codereg[6];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00010 : begin
+ g2out <= g2codereg[3] ^ g2codereg[7];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00011 : begin
+ g2out <= g2codereg[4] ^ g2codereg[8];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00100 : begin
+ g2out <= g2codereg[5] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00101 : begin
+ g2out <= g2codereg[1] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00110 : begin
+ g2out <= g2codereg[2] ^ g2codereg[10];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00111 : begin
+ g2out <= g2codereg[1] ^ g2codereg[8];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01000 : begin
+ g2out <= g2codereg[2] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01001 : begin
+ g2out <= g2codereg[3] ^ g2codereg[10];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01010 : begin
+ g2out <= g2codereg[2] ^ g2codereg[3];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01011 : begin
+ g2out <= g2codereg[3] ^ g2codereg[4];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01100 : begin
+ g2out <= g2codereg[5] ^ g2codereg[6];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01101 : begin
+ g2out <= g2codereg[6] ^ g2codereg[7];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01110 : begin
+ g2out <= g2codereg[7] ^ g2codereg[8];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 01111 : begin
+ g2out <= g2codereg[8] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10000 : begin
+ g2out <= g2codereg[9] ^ g2codereg[10];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10001 : begin
+ g2out <= g2codereg[1] ^ g2codereg[4];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10010 : begin
+ g2out <= g2codereg[2] ^ g2codereg[5];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10011 : begin
+ g2out <= g2codereg[3] ^ g2codereg[6];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10100 : begin
+ g2out <= g2codereg[4] ^ g2codereg[7];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10101 : begin
+ g2out <= g2codereg[5] ^ g2codereg[8];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10110 : begin
+ g2out <= g2codereg[6] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 10111 : begin
+ g2out <= g2codereg[1] ^ g2codereg[3];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11000 : begin
+ g2out <= g2codereg[4] ^ g2codereg[6];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11001 : begin
+ g2out <= g2codereg[5] ^ g2codereg[7];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11010 : begin
+ g2out <= g2codereg[6] ^ g2codereg[8];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11011 : begin
+ g2out <= g2codereg[7] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11100 : begin
+ g2out <= g2codereg[8] ^ g2codereg[10];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11101 : begin
+ g2out <= g2codereg[1] ^ g2codereg[6];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11110 : begin
+ g2out <= g2codereg[1] ^ g2codereg[7];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 11111 : begin
+ g2out <= g2codereg[3] ^ g2codereg[8];
+ g1out <= g1codereg[10];
+ goldcode <= g1out ^ g2out;
+ end
+ 5'b 00000 : begin
+ g2out <= g2codereg[4] ^ g2codereg[9];
+ g1out <= g1codereg[10];
+ goldcode <= 1'b 1;
+ end
+ default : begin
+ g2out <= 1'b 1;
+ //edited intially commented originally '0'
+ end
+ endcase
+ end else begin
g1out <= g1codereg[10];
+ g2out <= g2codereg[10];
goldcode <= g1out ^ g2out;
end
- 5'b 00010 : begin
- g2out <= g2codereg[3] ^ g2codereg[7];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 00011 : begin
- g2out <= g2codereg[4] ^ g2codereg[8];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 00100 : begin
- g2out <= g2codereg[5] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 00101 : begin
- g2out <= g2codereg[1] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 00110 : begin
- g2out <= g2codereg[2] ^ g2codereg[10];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 00111 : begin
- g2out <= g2codereg[1] ^ g2codereg[8];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01000 : begin
- g2out <= g2codereg[2] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01001 : begin
- g2out <= g2codereg[3] ^ g2codereg[10];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01010 : begin
- g2out <= g2codereg[2] ^ g2codereg[3];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01011 : begin
- g2out <= g2codereg[3] ^ g2codereg[4];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01100 : begin
- g2out <= g2codereg[5] ^ g2codereg[6];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01101 : begin
- g2out <= g2codereg[6] ^ g2codereg[7];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01110 : begin
- g2out <= g2codereg[7] ^ g2codereg[8];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 01111 : begin
- g2out <= g2codereg[8] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10000 : begin
- g2out <= g2codereg[9] ^ g2codereg[10];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10001 : begin
- g2out <= g2codereg[1] ^ g2codereg[4];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10010 : begin
- g2out <= g2codereg[2] ^ g2codereg[5];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10011 : begin
- g2out <= g2codereg[3] ^ g2codereg[6];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10100 : begin
- g2out <= g2codereg[4] ^ g2codereg[7];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10101 : begin
- g2out <= g2codereg[5] ^ g2codereg[8];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10110 : begin
- g2out <= g2codereg[6] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 10111 : begin
- g2out <= g2codereg[1] ^ g2codereg[3];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11000 : begin
- g2out <= g2codereg[4] ^ g2codereg[6];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11001 : begin
- g2out <= g2codereg[5] ^ g2codereg[7];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11010 : begin
- g2out <= g2codereg[6] ^ g2codereg[8];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11011 : begin
- g2out <= g2codereg[7] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11100 : begin
- g2out <= g2codereg[8] ^ g2codereg[10];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11101 : begin
- g2out <= g2codereg[1] ^ g2codereg[6];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11110 : begin
- g2out <= g2codereg[1] ^ g2codereg[7];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 11111 : begin
- g2out <= g2codereg[3] ^ g2codereg[8];
- g1out <= g1codereg[10];
- goldcode <= g1out ^ g2out;
- end
- 5'b 00000 : begin
- g2out <= g2codereg[4] ^ g2codereg[9];
- g1out <= g1codereg[10];
- goldcode <= 1'b 1;
- end
- default : begin
- g2out <= 1'b 1;
- //edited intially commented originally '0'
- end
- endcase
gold1 <= g1out;
gold2 <= g2out;
end
diff --git a/verilog/rtl/gps_engine/gps_multichannel.v b/verilog/rtl/gps_engine/gps_multichannel.v
index 8cabdfd..4b50c21 100644
--- a/verilog/rtl/gps_engine/gps_multichannel.v
+++ b/verilog/rtl/gps_engine/gps_multichannel.v
@@ -1,35 +1,31 @@
`timescale 1ns / 1ps
module gps_multichannel(
- mclr,
- mclk,
- adc2bit_i,
- adc2bit_q,
- codeout,
- epochrx,
- dll_sel, //Going to be a GPIO
- select_qmaxim,
- wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
- wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o
-);
-input mclr;
-input mclk;
-input [1:0] adc2bit_i;
-input [1:0] adc2bit_q;
-output codeout;
-input dll_sel;
-output epochrx; //Can be given to logic analyzer
-input select_qmaxim;
+ `ifdef USE_POWER_PINS
+ inout vccd1, // User area 1 1.8V supply
+ inout vssd1, // User area 1 digital ground
+ `endif
+
+input mclr,
+input mclk,
+input [1:0] adc2bit_i,
+input [1:0] adc2bit_q,
+output [7:0] codeout,
+input dll_sel,
+output [7:0] epochrx, //Can be given to logic analyzer
+input select_qmaxim,
//wishbone signals
- input wb_clk_i; // master clock input
- input wb_rst_i; // synchronous active high reset
- input [31:0] wb_adr_i; // lower address bits
- input [31:0] wb_dat_i; // databus input
- output [31:0] wb_dat_o; // databus output
- input wb_we_i; // write enable input
- input wb_stb_i; // stobe/core select signal
- input wb_cyc_i; // valid bus cycle input
- output wb_ack_o; // bus cycle acknowledge output
+ input wb_clk_i, // master clock input
+ input wb_rst_i, // synchronous active high reset
+ input [31:0] wb_adr_i, // lower address bits
+ input [31:0] wb_dat_i, // databus input
+ output [31:0] wb_dat_o, // databus output
+ input wb_we_i, // write enable input
+ input wb_stb_i, // stobe/core select signal
+ input wb_cyc_i, // valid bus cycle input
+ output wb_ack_o // bus cycle acknowledge output
+);
+
// Channel 1 GPS signals
@@ -40,26 +36,32 @@
wire dll_sel;
wire fll_enabl = 1'b 1;
wire costas_enabl = 1'b 1;
-wire epochrx;
+wire [7:0] epochrx;
+wire [7:0] codeout;
wire select_qmaxim;
wire ch1_select,ch2_select,ch3_select,ch4_select ;
wire ch5_select,ch6_select,ch7_select,ch8_select ;
+wire all_ch_select ;
wire ch1_wb_stb_i,ch2_wb_stb_i,ch3_wb_stb_i,ch4_wb_stb_i;
wire ch5_wb_stb_i,ch6_wb_stb_i,ch7_wb_stb_i,ch8_wb_stb_i;
wire ch1_wb_ack_o,ch2_wb_ack_o,ch3_wb_ack_o,ch4_wb_ack_o;
wire ch5_wb_ack_o,ch6_wb_ack_o,ch7_wb_ack_o,ch8_wb_ack_o;
+wire [31:0] ch1_wb_dat_o, ch2_wb_dat_o, ch3_wb_dat_o, ch4_wb_dat_o;
+wire [31:0] ch5_wb_dat_o, ch6_wb_dat_o, ch7_wb_dat_o, ch8_wb_dat_o;
// Module Address Select Logic
- assign ch1_select = (wb_adr_i[15:8] == 8'h0A) ;
- assign ch2_select = (wb_adr_i[15:8] == 8'h0B) ;
- assign ch3_select = (wb_adr_i[15:8] == 8'h0C) ;
- assign ch4_select = (wb_adr_i[15:8] == 8'h0D) ;
- assign ch5_select = (wb_adr_i[15:8] == 8'h0E) ;
- assign ch6_select = (wb_adr_i[15:8] == 8'h0F) ;
- assign ch7_select = (wb_adr_i[15:8] == 8'h10) ;
- assign ch8_select = (wb_adr_i[15:8] == 8'h11) ;
+ assign ch1_select = (wb_adr_i[31:8] == 24'h00000A) ;
+ assign ch2_select = (wb_adr_i[31:8] == 24'h00000B) ;
+ assign ch3_select = (wb_adr_i[31:8] == 24'h00000C) ;
+ assign ch4_select = (wb_adr_i[31:8] == 24'h00000D) ;
+ assign ch5_select = (wb_adr_i[31:8] == 24'h00000E) ;
+ assign ch6_select = (wb_adr_i[31:8] == 24'h00000F) ;
+ assign ch7_select = (wb_adr_i[31:8] == 24'h000010) ;
+ assign ch8_select = (wb_adr_i[31:8] == 24'h000011) ;
+
+ assign all_ch_select = {ch8_select,ch7_select,ch6_select,ch5_select,ch4_select,ch3_select,ch2_select,ch1_select};
// Module STROBE Select based on Address Range
assign ch1_wb_stb_i = (wb_stb_i && ch1_select) ;
@@ -78,8 +80,8 @@
.mclk(mclk),
.adc2bit_i(adc2bit_i),
.adc2bit_q(adc2bit_q),
- .epochrx(epochrx),
- .codeout(codeout),
+ .epochrx(epochrx[0]),
+ .codeout(codeout[0]),
.dll_sel1(dll_sel),
.fll_enabl(fll_enabl),
.costas_enabl(costas_enabl),
@@ -88,13 +90,175 @@
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_adr_i[7:0]),
.wb_dat_i(wb_dat_i),
- .wb_dat_o(wb_dat_o),
+ .wb_dat_o(ch1_wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(ch1_wb_stb_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(ch1_wb_ack_o)
);
+gps_single_channel ch2(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[1]),
+ .codeout(codeout[1]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch2_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch2_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch2_wb_ack_o)
+);
+gps_single_channel ch3(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[2]),
+ .codeout(codeout[2]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch3_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch3_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch3_wb_ack_o)
+);
+gps_single_channel ch4(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[3]),
+ .codeout(codeout[3]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch4_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch4_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch4_wb_ack_o)
+);
+gps_single_channel ch5(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[4]),
+ .codeout(codeout[4]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch5_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch5_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch5_wb_ack_o)
+);
+gps_single_channel ch6(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[5]),
+ .codeout(codeout[5]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch6_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch6_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch6_wb_ack_o)
+);
+gps_single_channel ch7(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[6]),
+ .codeout(codeout[6]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch7_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch7_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch7_wb_ack_o)
+);
+gps_single_channel ch8(
+ .mclr(mclr),
+ .mclk(mclk),
+ .adc2bit_i(adc2bit_i),
+ .adc2bit_q(adc2bit_q),
+ .epochrx(epochrx[7]),
+ .codeout(codeout[7]),
+ .dll_sel1(dll_sel),
+ .fll_enabl(fll_enabl),
+ .costas_enabl(costas_enabl),
+ .select_qmaxim(select_qmaxim),
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(wb_adr_i[7:0]),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(ch8_wb_dat_o),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(ch8_wb_stb_i),
+ .wb_cyc_i(wb_cyc_i),
+ .wb_ack_o(ch8_wb_ack_o)
+);
+always @ (all_ch_select,ch1_wb_dat_o,ch2_wb_dat_o,ch3_wb_dat_o,ch4_wb_dat_o,ch5_wb_dat_o,ch6_wb_dat_o,ch7_wb_dat_o,ch8_wb_dat_o)
+begin
+ case(all_ch_select)
+ 8'b00000001 : wb_dat_o <= ch1_wb_dat_o ;
+ 8'b00000010 : wb_dat_o <= ch2_wb_dat_o ;
+ 8'b00000100 : wb_dat_o <= ch3_wb_dat_o ;
+ 8'b00001000 : wb_dat_o <= ch4_wb_dat_o ;
+ 8'b00010000 : wb_dat_o <= ch5_wb_dat_o ;
+ 8'b00100000 : wb_dat_o <= ch6_wb_dat_o ;
+ 8'b01000000 : wb_dat_o <= ch7_wb_dat_o ;
+ 8'b10000000 : wb_dat_o <= ch8_wb_dat_o ;
+ default : wb_dat_o <= 32'd0 ;
+ endcase
+end
+
endmodule
diff --git a/verilog/rtl/gps_engine/gps_single_channel.v b/verilog/rtl/gps_engine/gps_single_channel.v
index 47b8a66..f90341a 100644
--- a/verilog/rtl/gps_engine/gps_single_channel.v
+++ b/verilog/rtl/gps_engine/gps_single_channel.v
@@ -62,6 +62,8 @@
wire dll_sel1;
wire fll_enabl;
wire costas_enabl;
+wire irnss_sel;
+wire [10:1] irnss_code;
wire [29:0] code_frequency ;
@@ -132,6 +134,7 @@
wire [2:0] adc3bit_qsel;
reg enable = 1'b 0;
+reg sat_change;
wire nco_car_clk1p4m;
wire nco_cod_clk1p0m;
@@ -160,6 +163,8 @@
reg count_reset = 1'b 0;
wire [19:0] integmag;
wire start;
+wire [4:0] satellite_id2;
+wire [4:0] satellite_id1;
assign fll_enable = acq & fll_enabl;
assign dll_enable = dll_sel1 & acq;
@@ -188,7 +193,8 @@
.carr_frequency_offset (carr_frequency_offset),
.acq_threshold (acq_threshold),
.sine_lut (sine_lut),
- .satellite_id (satellite_id),
+ .satellite_id1 (satellite_id1),
+ .satellite_id2 (satellite_id2),
.prompt_idata (prompt_idata),
.prompt_qdata (prompt_qdata),
.late_idata (late_idata),
@@ -196,7 +202,10 @@
.early_idata (early_idata),
.early_qdata (early_qdata),
.intg_ready (tr_len_clk1ms),
- .acq_complete (acq)
+ .acq_complete (acq),
+ .irnss_sel(irnss_sel),
+ .irnss_code(irnss_code),
+ .sat_change(sat_change)
);
// 2 to 3 bit conv for I-channel IF Input
@@ -341,7 +350,9 @@
.pnl(pnl1),
.epochrx(epochrx),
.code_sel(satellite_id), // ----- Declare confg_reg_1 in input
- .epoch(tr_epoclk_clk1ms)
+ .epoch(tr_epoclk_clk1ms),
+ .irnss_sel(irnss_sel), //To be declared as inputs
+ .irnss_code(irnss_code)
);
@@ -453,6 +464,25 @@
end
end
+ integer count_sat = 0;
+
+ always @(posedge tr_epoclk_clk1ms or negedge mclr) begin
+ if(mclr==1'b0) begin
+ count_sat = 0 ;
+ sat_change = 1'b0;
+ end
+ else begin
+ if (acq==1'b0 && count_sat<40920) begin
+ count_sat = count_sat + 1;
+ end else if(acq==1'b0 && count_sat==40920) begin
+ sat_change = ~sat_change ;
+ count_sat = 0;
+ end
+ end
+ end
+
+ assign satellite_id = sat_change == 1'b0 ? satellite_id1 : satellite_id2;
+
diff --git a/verilog/rtl/gps_engine/uprj_netlists.v b/verilog/rtl/gps_engine/uprj_netlists.v
new file mode 100644
index 0000000..3537de8
--- /dev/null
+++ b/verilog/rtl/gps_engine/uprj_netlists.v
@@ -0,0 +1,28 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+ // Assume default net type to be wire because GL netlists don't have the wire definitions
+ `default_nettype wire
+ `include "gl/user_project_wrapper.v"
+ `include "gl/user_proj_example.v"
+`else
+ `include "user_project_wrapper.v"
+ `include "user_proj_example.v"
+`endif
\ No newline at end of file
diff --git a/verilog/rtl/gps_engine/wb_interface.v b/verilog/rtl/gps_engine/wb_interface.v
index 5858b25..8205b62 100644
--- a/verilog/rtl/gps_engine/wb_interface.v
+++ b/verilog/rtl/gps_engine/wb_interface.v
@@ -8,7 +8,8 @@
carr_frequency_offset,
acq_threshold,
sine_lut,
- satellite_id,
+ satellite_id1,
+ satellite_id2,
prompt_idata,
prompt_qdata,
late_idata,
@@ -16,7 +17,10 @@
early_idata,
early_qdata,
intg_ready,
- acq_complete
+ acq_complete,
+ irnss_sel,
+ irnss_code,
+ sat_change
);
@@ -37,7 +41,9 @@
output reg [29:0] carr_frequency_offset;
output reg [14:0] acq_threshold;
output reg [23:0] sine_lut;
-output reg [4:0] satellite_id;
+output reg [4:0] satellite_id1;
+output reg [4:0] satellite_id2;
+input sat_change;
input [19:0] prompt_idata ;
input [19:0] prompt_qdata;
input [19:0] late_idata;
@@ -46,6 +52,8 @@
input [19:0] early_qdata;
input intg_ready;
input acq_complete;
+output reg [10:1] irnss_code;
+output reg irnss_sel;
parameter CODE_FREQUENCY_REG_ADDR = 8'h00 ;
parameter CARR_FREQUENCY_REG_ADDR = 8'h04 ;
@@ -60,6 +68,8 @@
parameter EARLY_IDATA_REG_ADDR = 8'h28;
parameter EARLY_QDATA_REG_ADDR = 8'h2C;
parameter STATUS_REG_ADDR = 8'h30;
+parameter IRNSS_REG_ADDR = 8'h34;
+parameter SAT_REG_ADDR = 8'h38;
reg intg_ready_reg ;
reg intg_ready_ff1 ,intg_ready_ff2 ,intg_ready_ff3 ;
@@ -98,8 +108,11 @@
carr_frequency_offset <= #1 30'h00000000;
acq_threshold <= #1 15'h0000;
sine_lut <= #1 24'h000000;
- satellite_id <= #1 5'h00;
+ satellite_id1 <= #1 5'h00;
+ satellite_id2 <= #1 5'h00;
intg_ready_reg <= #1 1'b0;
+ irnss_sel <= #1 1'b0;
+ irnss_code <= #1 10'h000;
end
else begin
if (wb_wacc) begin
@@ -111,9 +124,14 @@
ACQ_THRESHOLD_REG_ADDR : acq_threshold <= #1 wb_dat_i[14:0];
CONFG_REG_ADDR : begin
sine_lut <= #1 wb_dat_i[23:0];
- satellite_id <= #1 wb_dat_i[28:24];
+ satellite_id1 <= #1 wb_dat_i[28:24];
end
STATUS_REG_ADDR : intg_ready_reg <= #1 wb_dat_i[0];
+ IRNSS_REG_ADDR : begin
+ irnss_sel <= #1 wb_dat_i[0];
+ irnss_code <= #1 wb_dat_i[10:1];
+ end
+ SAT_REG_ADDR : satellite_id2 <= #1 wb_dat_i[4:0];
default: ;
endcase
@@ -139,6 +157,7 @@
EARLY_IDATA_REG_ADDR : wb_dat_o <= { {12{1'b0}},early_idata};
EARLY_QDATA_REG_ADDR : wb_dat_o <= { {12{1'b0}},early_qdata};
STATUS_REG_ADDR : wb_dat_o <= { {30{1'b0}},acq_complete,intg_ready_reg};
+ SAT_REG_ADDR : wb_dat_o <= {{26{1'b0}},sat_change,satellite_id2};
default: ;
endcase
end
