Removed a system condition while placing data in wb_dat_o
diff --git a/verilog/rtl/gps_engine/wb_interface.v b/verilog/rtl/gps_engine/wb_interface.v
index fb10b7d..5858b25 100644
--- a/verilog/rtl/gps_engine/wb_interface.v
+++ b/verilog/rtl/gps_engine/wb_interface.v
@@ -138,7 +138,7 @@
LATE_QDATA_REG_ADDR : wb_dat_o <= { {12{1'b0}},late_qdata};
EARLY_IDATA_REG_ADDR : wb_dat_o <= { {12{1'b0}},early_idata};
EARLY_QDATA_REG_ADDR : wb_dat_o <= { {12{1'b0}},early_qdata};
- STATUS_REG_ADDR : wb_dat_o <= { {30{1'b0}},acq_complete,intg_ready_reg};
+ STATUS_REG_ADDR : wb_dat_o <= { {30{1'b0}},acq_complete,intg_ready_reg};
default: ;
endcase
end
