Updated Gate level Netlist

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 5e9fb5e..3d90833 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -641,13 +641,13 @@
     .sr_out(io_out[8]),
     .vccd1(vccd1),
     .vssd1(vssd1));
- LVDT temp3 (.va(analog_io[19]),
+ LVDT temp3 (.Iin(analog_io[28]),
+    .vout(analog_io[21]),
+    .va(analog_io[19]),
     .vb(analog_io[20]),
     .vcap(analog_io[22]),
-    .Iin(analog_io[28]),
-    .vout(analog_io[21]),
-    .vss(vssd1),
-    .vdd(vccd1),
+    .vssa2(vssd1),
+    .vdda2(vccd1),
     .re(io_in[24]),
     .clk(io_in[23]),
     .y1(io_out[26]),