Final RTL

diff --git a/verilog/rtl/gps_engine/gps_multichannel.v b/verilog/rtl/gps_engine/gps_multichannel.v
index 4b50c21..56a419e 100644
--- a/verilog/rtl/gps_engine/gps_multichannel.v
+++ b/verilog/rtl/gps_engine/gps_multichannel.v

@@ -19,7 +19,7 @@
 	input        wb_rst_i,     // synchronous active high reset
 	input  [31:0] wb_adr_i,     // lower address bits
 	input  [31:0] wb_dat_i,     // databus input
-	output [31:0] wb_dat_o,     // databus output
+	output reg [31:0] wb_dat_o,     // databus output
 	input        wb_we_i,      // write enable input
 	input        wb_stb_i,     // stobe/core select signal
 	input        wb_cyc_i,     // valid bus cycle input
@@ -50,6 +50,7 @@
 
 wire [31:0] ch1_wb_dat_o, ch2_wb_dat_o, ch3_wb_dat_o, ch4_wb_dat_o;
 wire [31:0] ch5_wb_dat_o, ch6_wb_dat_o, ch7_wb_dat_o, ch8_wb_dat_o;
+reg [31:0] count32;
 
    // Module Address Select Logic
    assign ch1_select = (wb_adr_i[31:8] == 24'h00000A) ;
@@ -94,7 +95,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch1_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch1_wb_ack_o)
+	.wb_ack_o(ch1_wb_ack_o),
+	.count32(count32)
 );
 
 gps_single_channel ch2(
@@ -116,7 +118,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch2_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch2_wb_ack_o)
+	.wb_ack_o(ch2_wb_ack_o),
+	.count32(count32)
 );
 gps_single_channel ch3(
 	.mclr(mclr),
@@ -137,7 +140,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch3_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch3_wb_ack_o)
+	.wb_ack_o(ch3_wb_ack_o),
+	.count32(count32)
 );
 gps_single_channel ch4(
 	.mclr(mclr),
@@ -158,7 +162,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch4_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch4_wb_ack_o)
+	.wb_ack_o(ch4_wb_ack_o),
+	.count32(count32)
 );
 gps_single_channel ch5(
 	.mclr(mclr),
@@ -179,7 +184,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch5_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch5_wb_ack_o)
+	.wb_ack_o(ch5_wb_ack_o),
+	.count32(count32)
 );
 gps_single_channel ch6(
 	.mclr(mclr),
@@ -200,7 +206,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch6_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch6_wb_ack_o)
+	.wb_ack_o(ch6_wb_ack_o),
+	.count32(count32)
 );
 gps_single_channel ch7(
 	.mclr(mclr),
@@ -221,7 +228,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch7_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch7_wb_ack_o)
+	.wb_ack_o(ch7_wb_ack_o),
+	.count32(count32)
 );
 gps_single_channel ch8(
 	.mclr(mclr),
@@ -242,7 +250,8 @@
 	.wb_we_i(wb_we_i), 
 	.wb_stb_i(ch8_wb_stb_i), 
 	.wb_cyc_i(wb_cyc_i), 
-	.wb_ack_o(ch8_wb_ack_o)
+	.wb_ack_o(ch8_wb_ack_o),
+	.count32(count32)
 );
 
 
@@ -261,4 +270,13 @@
 	endcase
 end
 
+always @(negedge mclk or negedge mclr) begin
+	if (mclr==1'b0) begin
+		count32 <= 32'd0 ;
+	end
+	else begin
+		count32 <= count32 + 32'd1 ;
+	end
+end
+
 endmodule

diff --git a/verilog/rtl/gps_engine/gps_single_channel.v b/verilog/rtl/gps_engine/gps_single_channel.v
index f90341a..0dff273 100644
--- a/verilog/rtl/gps_engine/gps_single_channel.v
+++ b/verilog/rtl/gps_engine/gps_single_channel.v

@@ -28,7 +28,8 @@
 dll_sel1,
 fll_enabl,
 costas_enabl,
-select_qmaxim
+select_qmaxim,
+count32
 );
 
 input mclr, mclk;
@@ -51,6 +52,7 @@
 input fll_enabl;
 input costas_enabl;
 input select_qmaxim; // to be given as GPIO
+input [31:0] count32 ;
 
 wire mclr;
 wire mclk;
@@ -64,6 +66,8 @@
 wire costas_enabl;
 wire irnss_sel;
 wire [10:1] irnss_code;
+wire [31:0] count32 ;
+reg [31:0] timestamp_latch;
 
 
 wire [29:0] code_frequency ;
@@ -85,6 +89,7 @@
 
 
 reg [29:0] coffset; 
+reg sat_change;
 wire [29:0] coffset_costas;
 
 
@@ -134,7 +139,6 @@
 wire [2:0] adc3bit_qsel;
 
 reg enable = 1'b 0;
-reg sat_change;
 
 wire nco_car_clk1p4m;
 wire nco_cod_clk1p0m;
@@ -205,7 +209,8 @@
 	.acq_complete (acq),
   .irnss_sel(irnss_sel),
   .irnss_code(irnss_code),
-  .sat_change(sat_change)
+  .sat_change(sat_change),
+  .timestamp_latch(timestamp_latch)
  ); 
 
 // 2 to 3 bit conv for I-channel IF Input
@@ -465,22 +470,31 @@
   end
 
   integer count_sat = 0;
+  //reg sat_change;
 
   always @(posedge tr_epoclk_clk1ms or negedge mclr) begin
     if(mclr==1'b0) begin
-      count_sat = 0 ;
-      sat_change = 1'b0;
+      count_sat <= 0 ;
+      sat_change <= 1'b0;
     end
     else begin
       if (acq==1'b0 && count_sat<40920) begin
-        count_sat = count_sat + 1;
+        count_sat <= count_sat + 1;
       end else if(acq==1'b0 && count_sat==40920) begin
-        sat_change = ~sat_change ;
-        count_sat = 0;
+        sat_change <= ~sat_change ;
+        count_sat <= 0;
       end
     end
   end
 
+  always @(negedge tr_epoclk_clk1ms or negedge mclr) begin
+    if(mclr==1'b0) begin
+      timestamp_latch <= 32'd0 ;
+    end else begin
+      timestamp_latch <= count32;
+    end
+  end
+
   assign satellite_id = sat_change == 1'b0 ? satellite_id1 : satellite_id2;
 
 

diff --git a/verilog/rtl/gps_engine/wb_interface.v b/verilog/rtl/gps_engine/wb_interface.v
index 8205b62..7e89e06 100644
--- a/verilog/rtl/gps_engine/wb_interface.v
+++ b/verilog/rtl/gps_engine/wb_interface.v

@@ -20,7 +20,8 @@
 	acq_complete,
 	irnss_sel,
 	irnss_code,
-	sat_change
+	sat_change,
+	timestamp_latch
 );
 
 
@@ -54,6 +55,7 @@
 input acq_complete;
 output reg [10:1] irnss_code;
 output reg irnss_sel;
+input [31:0] timestamp_latch ;
 
 parameter CODE_FREQUENCY_REG_ADDR = 8'h00 ;
 parameter CARR_FREQUENCY_REG_ADDR = 8'h04 ;
@@ -70,6 +72,7 @@
 parameter STATUS_REG_ADDR      = 8'h30;
 parameter IRNSS_REG_ADDR       = 8'h34;
 parameter SAT_REG_ADDR         = 8'h38;
+parameter TIMESTAMP_LATCH_ADDR = 8'h3C;
 
 reg intg_ready_reg ;	
 reg intg_ready_ff1 ,intg_ready_ff2 ,intg_ready_ff3 ;	
@@ -158,6 +161,7 @@
 			EARLY_QDATA_REG_ADDR : wb_dat_o <=  { {12{1'b0}},early_qdata};
 			STATUS_REG_ADDR      : wb_dat_o <= { {30{1'b0}},acq_complete,intg_ready_reg};  
 			SAT_REG_ADDR         : wb_dat_o <= {{26{1'b0}},sat_change,satellite_id2};
+			TIMESTAMP_LATCH_ADDR : wb_dat_o <= timestamp_latch ;
 			default: ;
 		endcase
 	end