user_proj_example.v:user IO pin assignment updated , user_project_wrapper.v: analog macro instanciated
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index a027c93..53455b4 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -39,14 +39,14 @@ parameter BITS = 32 )( `ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground + //inout vdda1, // User area 1 3.3V supply + //inout vdda2, // User area 2 3.3V supply + //inout vssa1, // User area 1 analog ground + //inout vssa2, // User area 2 analog ground inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply + //inout vccd2, // User area 2 1.8v supply inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground + //inout vssd2, // User area 2 digital ground `endif // Wishbone Slave ports (WB MI A) @@ -74,27 +74,19 @@ // IRQ output [2:0] irq ); - wire clk; - wire rst; wire [`MPRJ_IO_PADS-1:0] io_in; wire [`MPRJ_IO_PADS-1:0] io_out; wire [`MPRJ_IO_PADS-1:0] io_oeb; - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; - - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; - - wire gps_clk ; + wire mclk ; + wire mclr; wire [1:0] gps_data_i ; wire [1:0] gps_data_q ; wire dll_sel ; wire select_qmaxim ; - wire codeout , epochrx ; + wire [7:0] codeout ; + wire [7:0] epochrx ; // IRQ assign irq = 3'b000; // Unused @@ -102,30 +94,48 @@ //io_oeb is active low signal - assign gps_clk = io_in[18] ; // IO[18] - assign io_oeb[18]= 1'b1; + assign mclk = io_in[29] ; + assign io_oeb[29]= 1'b1; - assign gps_data_i[0] = io_in[19] ; // IO[19] - assign io_oeb[19]= 1'b1; + assign gps_data_i[0] = io_in[30] ; + assign io_oeb[30]= 1'b1; - assign gps_data_i[1] = io_in[20] ; // IO[20] - assign io_oeb[20]= 1'b1; + assign gps_data_i[1] = io_in[31] ; + assign io_oeb[31]= 1'b1; - assign gps_data_q[0] = io_in[21] ; // IO[21] - assign io_oeb[21]= 1'b1; + assign gps_data_q[0] = io_in[32] ; + assign io_oeb[32]= 1'b1; - assign gps_data_q[1] = io_in[22] ; // IO[22] - assign io_oeb[22]= 1'b1; + assign gps_data_q[1] = io_in[33] ; + assign io_oeb[33]= 1'b1; - assign dll_sel = la_data_in[0] ; - assign select_qmaxim = la_data_in[1] ; - assign la_data_out[2] = codeout ; - assign la_data_out[3] = epochrx ; + assign dll_sel = io_in[34] ; + assign io_oeb[34]= 1'b1; + assign select_qmaxim = io_in[35] ; + assign io_oeb[35]= 1'b1; + assign la_data_out[10:3] = codeout ; + assign la_data_out[18:11] = epochrx ; + assign mclr = io_in[36]; + assign io_oeb[36]= 1'b1; - gps_multichannel gps_engine_i ( + assign io_oeb[8] = 1'b0; //Digital Outputs of Analog Macro and LVDT + assign io_oeb[9] = 1'b0; + assign io_oeb[14] = 1'b0; + assign io_oeb[15] = 1'b0; + assign io_oeb[25] = 1'b0; + assign io_oeb[26] = 1'b0; + assign io_oeb[27] = 1'b0; - .mclr (wb_rst_i), - .mclk (gps_clk ), + assign io_oeb[10] = 1'b1; //Digital Inputs of Analog Macro and LVDT + assign io_oeb[12] = 1'b1; + assign io_oeb[17] = 1'b1; + assign io_oeb[18] = 1'b1; + assign io_oeb[23] = 1'b1; + assign io_oeb[24] = 1'b1; + + gps_multichannel gps_engine_i( + .mclr (mclr), + .mclk (mclk), .adc2bit_i (gps_data_i), .adc2bit_q (gps_data_q), .codeout(codeout),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 2a3462b..049507b 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -82,46 +82,89 @@ /* User project is instantiated here */ /*--------------------------------------*/ -user_proj_example mprj ( - `ifdef USE_POWER_PINS - .vdda1(vdda1), // User area 1 3.3V power - .vdda2(vdda2), // User area 2 3.3V power - .vssa1(vssa1), // User area 1 analog ground - .vssa2(vssa2), // User area 2 analog ground - .vccd1(vccd1), // User area 1 1.8V power - .vccd2(vccd2), // User area 2 1.8V power + user_proj_example mprj ( + `ifdef USE_POWER_PINS + .vccd1(vccd1), // User area 1 1.8V power .vssd1(vssd1), // User area 1 digital ground - .vssd2(vssd2), // User area 2 digital ground + `endif + + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + // MGMT SoC Wishbone Slave + + .wbs_cyc_i(wbs_cyc_i), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o), + .wbs_dat_o(wbs_dat_o), + + // Logic Analyzer + + .la_data_in(la_data_in), + .la_data_out(la_data_out), + .la_oenb (la_oenb), + + // IO Pads + + .io_in (io_in), + .io_out(io_out), + .io_oeb(io_oeb), + + // IRQ + .irq(user_irq) + ); + + +wire common; + + +analog_macro temp1 ( + `ifdef USE_POWER_PINS + .vdda1(vdda1), + .vssa1(vssa1), +`endif +.vbiasr(analog_io[11]), +.vinit(analog_io[13]), +.reset(io_in[10]), +.Fvco(io_out[14]), +.v9m(common) + +); + +temp_digital temp2 ( + `ifdef USE_POWER_PINS + .vccd1(vccd1), // User area 1 1.8V power + .vssd1(vssd1), // User area 1 digital ground `endif - - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - - // MGMT SoC Wishbone Slave - - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - - // IO Pads - - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), - - // IRQ - .irq(user_irq) + .counter_clk(common), + .shift_clk(io_in[12]), + .reset_12(io_in[10]), + .sr_out(io_out[8]), + .ref_clk(io_out[9]), + .c_clk(io_out[15]) + +); +LVDT temp3 ( +`ifdef USE_POWER_PINS + .vdda1(vdda1), + .vssa1(vssa1), +`endif + .Iin(analog_io[28]), +.va(analog_io[19]), + .vb(analog_io[20]), +.vcap(analog_io[22]), + .vout(analog_io[21]), + .a2(io_in[18]), +.a1(io_in[17]), + .clk(io_in[23]), + .re(io_in[24]), + .y0(io_out[25]), + .y1(io_out[26]), + .y2(io_out[27]) ); endmodule // user_project_wrapper