ro-powerlines
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 0385fee..4a541b7 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 08e1e8f..d4e18df 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,36 @@ magic tech sky130A -timestamp 1642911889 +timestamp 1642944651 +<< locali >> +rect 247445 329554 247576 329570 +rect 247445 329454 247459 329554 +rect 247560 329454 247576 329554 +rect 247445 329439 247576 329454 +<< viali >> +rect 247701 329822 247772 329890 +rect 247459 329454 247560 329554 +<< metal1 >> +rect 247694 329890 247780 329899 +rect 247694 329822 247701 329890 +rect 247772 329822 247780 329890 +rect 247694 329815 247780 329822 +rect 247445 329554 247576 329570 +rect 247445 329454 247459 329554 +rect 247560 329454 247576 329554 +rect 247445 329439 247576 329454 +<< via1 >> +rect 247701 329822 247772 329890 +rect 247459 329454 247560 329554 << metal2 >> +rect 247049 329859 247236 330039 +rect 247694 329890 247780 329899 +rect 247694 329822 247701 329890 +rect 247772 329822 247780 329890 +rect 247694 329815 247780 329822 +rect 247445 329554 247576 329570 +rect 247445 329454 247459 329554 +rect 247560 329454 247576 329554 +rect 247445 329439 247576 329454 rect 262 -400 318 240 rect 853 -400 909 240 rect 1444 -400 1500 240 @@ -496,6 +525,9 @@ rect 290443 -400 290499 240 rect 291034 -400 291090 240 rect 291625 -400 291681 240 +<< via2 >> +rect 247701 329822 247772 329890 +rect 247459 329454 247560 329554 << metal3 >> rect 8097 351150 10597 352400 rect 34097 351150 36597 352400 @@ -537,6 +569,21 @@ rect -400 340121 850 340471 rect 287117 339172 292400 341209 rect 291150 338992 292400 339172 +rect 247049 330028 247236 330039 +rect 247049 330027 247778 330028 +rect 247049 330024 247782 330027 +rect 247049 329881 247062 330024 +rect 247219 329940 247782 330024 +rect 247219 329881 247236 329940 +rect 247049 329859 247236 329881 +rect 247681 329890 247782 329940 +rect 247681 329822 247701 329890 +rect 247772 329822 247782 329890 +rect 247681 329815 247782 329822 +rect 247445 329554 247576 329570 +rect 247445 329454 247459 329554 +rect 247560 329454 247576 329554 +rect 247445 329439 247576 329454 rect -400 324049 830 324321 rect -400 322156 4976 324049 rect -400 321921 830 322156 @@ -786,6 +833,16 @@ rect -400 772 240 828 rect 291760 772 292400 828 << via3 >> +rect 243932 337228 243984 337283 +rect 243852 334765 243904 334815 +rect 247062 329881 247219 330024 +rect 247459 329454 247560 329554 +rect 245761 318620 245811 318670 +rect 245682 316154 245732 316204 +rect 245602 313769 245652 313819 +rect 245523 311303 245573 311353 +rect 245443 308917 245493 308967 +rect 245363 306451 245413 306501 rect 273813 275847 275123 276989 rect 281123 73748 282980 75451 << metal4 >> @@ -801,7 +858,105 @@ rect 114054 349155 116090 351150 rect 159668 349191 161704 351150 rect 164874 349155 166910 351150 +rect 241132 337306 243344 338090 +rect 243555 337802 243747 337814 +rect 243555 337682 243571 337802 +rect 243704 337737 243747 337802 +rect 243704 337682 244231 337737 +rect 243555 337669 244231 337682 +rect 243555 337668 243747 337669 rect 164365 301000 166665 337301 +rect 241132 337283 244009 337306 +rect 241132 337228 243932 337283 +rect 243984 337228 244009 337283 +rect 241132 337208 244009 337228 +rect 241132 334841 243344 337208 +rect 243506 335283 244150 335311 +rect 243506 335143 243515 335283 +rect 243666 335143 244150 335283 +rect 243506 335128 244150 335143 +rect 241132 334815 243924 334841 +rect 241132 334765 243852 334815 +rect 243904 334765 243924 334815 +rect 241132 334737 243924 334765 +rect 241132 329591 243344 334737 +rect 247049 330024 247236 330039 +rect 247049 329881 247062 330024 +rect 247219 329881 247236 330024 +rect 247049 329859 247236 329881 +rect 241132 329554 247591 329591 +rect 241132 329454 247459 329554 +rect 247560 329454 247591 329554 +rect 241132 329410 247591 329454 +rect 241132 327660 243344 329410 +rect 241132 327511 247307 327660 +rect 241132 325878 243344 327511 +rect 241132 325729 247285 325878 +rect 241132 324107 243344 325729 +rect 241132 323958 247312 324107 +rect 241132 318705 243344 323958 +rect 245408 319188 245640 319191 +rect 245408 319175 246066 319188 +rect 245408 319023 245432 319175 +rect 245588 319023 246066 319175 +rect 245408 319013 246066 319023 +rect 245408 319001 245640 319013 +rect 241132 318670 245856 318705 +rect 241132 318620 245761 318670 +rect 245811 318620 245856 318670 +rect 241132 318570 245856 318620 +rect 241132 316244 243344 318570 +rect 245385 316705 245617 316713 +rect 245385 316692 245985 316705 +rect 245385 316540 245417 316692 +rect 245576 316540 245985 316692 +rect 245385 316529 245985 316540 +rect 245385 316523 245617 316529 +rect 241132 316204 245768 316244 +rect 241132 316154 245682 316204 +rect 245732 316154 245768 316204 +rect 241132 316109 245768 316154 +rect 241132 313866 243344 316109 +rect 245501 314300 245547 314305 +rect 245501 314291 245902 314300 +rect 245207 314266 245902 314291 +rect 245207 314132 245226 314266 +rect 245364 314132 245902 314266 +rect 245207 314114 245902 314132 +rect 245501 314107 245902 314114 +rect 245501 314093 245547 314107 +rect 241132 313819 245684 313866 +rect 241132 313769 245602 313819 +rect 245652 313769 245684 313819 +rect 241132 313740 245684 313769 +rect 241132 311381 243344 313740 +rect 245128 311854 245825 311890 +rect 245128 311699 245151 311854 +rect 245319 311699 245825 311854 +rect 245128 311676 245825 311699 +rect 241132 311353 245610 311381 +rect 241132 311303 245523 311353 +rect 245573 311303 245610 311353 +rect 241132 311275 245610 311303 +rect 241132 308994 243344 311275 +rect 245072 309456 245751 309488 +rect 245072 309309 245095 309456 +rect 245251 309309 245751 309456 +rect 245072 309282 245751 309309 +rect 241132 308967 245508 308994 +rect 241132 308917 245443 308967 +rect 245493 308917 245508 308967 +rect 241132 308897 245508 308917 +rect 241132 306523 243344 308897 +rect 244991 307058 245669 307089 +rect 244991 306904 245010 307058 +rect 245165 306904 245669 307058 +rect 244991 306887 245669 306904 +rect 241132 306501 245439 306523 +rect 241132 306451 245363 306501 +rect 245413 306451 245439 306501 +rect 241132 306426 245439 306451 +rect 241132 301000 243344 306426 rect 11000 299000 280000 301000 rect 164365 282016 166665 299000 rect 164365 281993 166759 282016 @@ -838,6 +993,15 @@ rect 11000 26000 276000 28000 rect 164365 5597 166665 26000 << via4 >> +rect 243571 337682 243704 337802 +rect 243515 335143 243666 335283 +rect 247062 329881 247219 330024 +rect 245432 319023 245588 319175 +rect 245417 316540 245576 316692 +rect 245226 314132 245364 314266 +rect 245151 311699 245319 311854 +rect 245095 309309 245251 309456 +rect 245010 306904 245165 307058 rect 273813 275847 275123 276989 << metal5 >> rect 82797 351150 85297 352400 @@ -854,7 +1018,54 @@ rect 164874 349155 166910 351150 rect 10000 341000 279000 343000 rect 157000 337000 160000 341000 +rect 238022 337829 240372 341000 +rect 238022 337802 243719 337829 +rect 238022 337682 243571 337802 +rect 243704 337682 243719 337802 +rect 238022 337655 243719 337682 rect 157052 281993 159393 337000 +rect 238022 335302 240372 337655 +rect 238022 335283 243683 335302 +rect 238022 335143 243515 335283 +rect 243666 335143 243683 335283 +rect 238022 335126 243683 335143 +rect 238022 330054 240372 335126 +rect 238022 330024 247243 330054 +rect 238022 329881 247062 330024 +rect 247219 329881 247243 330024 +rect 238022 329844 247243 329881 +rect 238022 319187 240372 329844 +rect 238022 319175 245605 319187 +rect 238022 319023 245432 319175 +rect 245588 319023 245605 319175 +rect 238022 319008 245605 319023 +rect 238022 316709 240372 319008 +rect 238022 316692 245596 316709 +rect 238022 316540 245417 316692 +rect 245576 316540 245596 316692 +rect 238022 316527 245596 316540 +rect 238022 314287 240372 316527 +rect 238022 314286 245208 314287 +rect 238022 314266 245383 314286 +rect 238022 314132 245226 314266 +rect 245364 314132 245383 314266 +rect 238022 314115 245383 314132 +rect 238022 311881 240372 314115 +rect 238022 311854 245369 311881 +rect 238022 311699 245151 311854 +rect 245319 311699 245369 311854 +rect 238022 311676 245369 311699 +rect 238022 309474 240372 311676 +rect 238022 309456 245265 309474 +rect 238022 309309 245095 309456 +rect 245251 309309 245265 309456 +rect 238022 309295 245265 309309 +rect 238022 307081 240372 309295 +rect 238022 307058 245191 307081 +rect 238022 306904 245010 307058 +rect 245165 306904 245191 307058 +rect 238022 306879 245191 306904 +rect 238022 306014 240372 306879 rect 157010 281056 159393 281993 rect 157010 277890 159389 281056 rect 255819 277906 272994 277912 @@ -912,7 +1123,7 @@ transform 1 0 37991 0 1 261137 box -415 -1715 4690 2035 use ro_complete ro_complete_0 -timestamp 1642911854 +timestamp 1642943789 transform -1 0 245567 0 -1 235887 box -57 -5330 4455 1440 use divider divider_2 @@ -924,7 +1135,7 @@ transform 1 0 31292 0 1 318138 box -5415 -2690 26430 12835 use ro_complete ro_complete_1 -timestamp 1642911854 +timestamp 1642943789 transform 1 0 247313 0 1 328719 box -57 -5330 4455 1440 use divbuf divbuf_7
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 916e31e..2d7071c 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,2556 +106,2750 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF -C1 divider_1/nor_1/B divider_1/and_0/B 0.31fF -C2 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF -C3 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/D 0.32fF -C4 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF -C5 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF -C6 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF -C7 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF -C8 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF -C9 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF -C10 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF -C11 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF -C12 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF -C13 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C14 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF -C15 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C16 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF -C17 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF -C18 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF -C19 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z4 0.36fF -C20 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Q 0.05fF -C21 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C22 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C23 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF -C24 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C25 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/tspc_r_1/Z4 0.04fF -C26 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF -C27 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF -C28 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF -C29 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF -C30 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/Out 0.11fF -C31 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF -C32 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C33 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C34 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF -C35 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C36 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF -C37 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF -C38 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF -C39 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF -C40 cp_0/a_1710_n2840# cp_0/out 0.61fF -C41 cp_0/a_10_n50# cp_0/vbias 0.19fF -C42 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF -C43 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C44 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C45 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF -C46 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C47 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF -C48 divider_1/nor_1/B divider_1/tspc_1/Z4 0.21fF -C49 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF -C50 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF -C51 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF -C52 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF -C53 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C54 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C55 divider_2/nor_1/A divider_2/tspc_0/Z1 0.03fF -C56 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF -C57 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C58 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF -C59 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C60 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C61 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C62 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C63 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C64 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C65 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF -C66 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.35fF -C67 divider_2/prescaler_0/Out divider_2/clk 0.51fF -C68 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C69 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF -C70 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C71 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C72 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C73 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Q 0.04fF -C74 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF -C75 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF -C76 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C77 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C78 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C79 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C80 divider_1/mc2 divider_1/and_0/A 0.16fF -C81 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C82 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF -C83 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF -C84 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C85 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C86 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF -C87 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF -C88 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C89 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C90 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.15fF -C91 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF -C92 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C93 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z4 0.00fF -C94 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF -C95 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C96 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF -C97 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF -C98 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF -C99 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C100 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C101 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/nand_1/z1 0.01fF -C102 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/Out 0.05fF -C103 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF -C104 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C105 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C106 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C107 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C108 divider_0/nor_1/A divider_0/and_0/B 0.08fF -C109 pd_1/DOWN pd_1/UP 0.46fF -C110 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C111 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C112 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C113 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF -C114 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF -C115 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF -C116 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF -C117 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF -C118 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF -C119 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C120 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/R 0.33fF -C121 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF -C122 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C123 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF -C124 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF -C125 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF -C126 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C127 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF -C128 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C129 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z1 0.71fF -C130 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C131 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF -C132 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C133 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF -C134 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/tspc_2/D 0.04fF -C135 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF -C136 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C137 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF -C138 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z3 0.05fF -C139 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C140 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF -C141 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/Out 0.08fF -C142 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C143 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C144 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF -C145 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C146 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C147 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C148 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF -C149 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.35fF -C150 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF -C151 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C152 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF -C153 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF -C154 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF -C155 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.01fF -C156 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF -C157 divider_2/tspc_0/Z1 divider_2/tspc_0/Z4 0.00fF -C158 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF -C159 divider_1/nor_0/B divider_1/Out 0.22fF -C160 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C161 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C162 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/Out 0.28fF -C163 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C164 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C165 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C166 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C167 divider_0/nor_1/B divider_0/and_0/B 0.31fF -C168 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF -C169 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF -C170 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C171 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF -C172 pd_1/REF pd_1/tspc_r_1/Z1 0.17fF -C173 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF -C174 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF -C175 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF -C176 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF -C177 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C178 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF -C179 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C180 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF -C181 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF -C182 divider_2/and_0/OUT divider_2/and_0/B 0.01fF -C183 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/Out 0.91fF -C184 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C185 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C186 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C187 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C188 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C189 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C190 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF -C191 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF -C192 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF -C193 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C194 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF -C195 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF -C196 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/Out 0.11fF -C197 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C198 divider_2/tspc_1/Z2 divider_2/tspc_1/a_630_n680# 0.01fF -C199 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF -C200 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C201 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.44fF -C202 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT 0.06fF -C203 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT5 0.01fF -C204 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C205 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z1 1.07fF -C206 divider_1/tspc_0/Z1 divider_1/nor_1/A 0.03fF -C207 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C208 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF -C209 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF -C210 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C211 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C212 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C213 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C214 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF -C215 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF -C216 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C217 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C218 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF -C219 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF -C220 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C221 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C222 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C223 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.01fF -C224 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C225 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF -C226 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C227 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF -C228 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C229 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF -C230 divider_1/prescaler_0/Out divider_1/clk 0.51fF -C231 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF -C232 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_1/z1 0.21fF -C233 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C234 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF -C235 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C236 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF -C237 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C238 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C239 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C240 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF -C241 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF -C242 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C243 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF -C244 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF -C245 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF -C246 io_clamp_low[0] io_clamp_high[0] 0.53fF -C247 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C248 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF -C249 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF -C250 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF -C251 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C252 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF -C253 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF -C254 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF -C255 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/nand_1/z1 0.01fF -C256 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/Out 0.05fF -C257 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF -C258 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF -C259 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF -C260 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF -C261 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C262 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF -C263 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C264 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF -C265 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF -C266 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C267 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C268 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF -C269 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/Z3 0.38fF -C270 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C271 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C272 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF -C273 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF -C274 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF -C275 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF -C276 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C277 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C278 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF -C279 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF -C280 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C281 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF -C282 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF -C283 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C284 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF -C285 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF -C286 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C287 pd_1/REF pd_1/tspc_r_1/Z2 0.19fF -C288 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C289 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C290 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C291 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C292 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF -C293 divider_2/tspc_0/Q divider_2/tspc_1/Z1 0.01fF -C294 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C295 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF -C296 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/Out 0.08fF -C297 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF -C298 divbuf_7/IN divbuf_7/OUT5 0.00fF -C299 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF -C300 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C301 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C302 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C303 divider_0/nor_0/B divider_0/Out 0.22fF -C304 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF -C305 io_clamp_high[2] io_analog[6] 0.53fF -C306 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C307 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C308 divbuf_0/OUT divbuf_0/OUT3 0.26fF -C309 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF -C310 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C311 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/Out 0.28fF -C312 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF -C313 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C314 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C315 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C316 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT 1.11fF -C317 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C318 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C319 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C320 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C321 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C322 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF -C323 pd_0/DOWN pd_0/UP 0.46fF -C324 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C325 divider_2/nor_1/A divider_2/mc2 0.04fF -C326 divider_1/tspc_0/Q divider_1/nor_1/B 0.22fF -C327 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C328 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C329 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C330 divider_1/and_0/OUT divider_1/and_0/B 0.01fF -C331 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/Out 0.91fF -C332 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF -C333 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF -C334 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C335 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C336 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C337 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF -C338 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF -C339 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C340 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF -C341 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/nor_1/A 0.23fF -C342 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C343 pll_full_0/pd_0/REF pll_full_0/pd_0/DOWN 1.48fF -C344 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF -C345 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF -C346 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C347 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF -C348 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF -C349 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C350 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C351 pd_0/DOWN pd_0/R 0.36fF -C352 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C353 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C354 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C355 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF -C356 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C357 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF -C358 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF -C359 ro_complete_0/a4 ro_complete_0/cbank_0/switch_1/vin 0.09fF -C360 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C361 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF -C362 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C363 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C364 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C365 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Q 0.20fF -C366 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C367 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C368 ro_complete_0/a5 ro_complete_0/cbank_0/switch_0/vin 0.09fF -C369 divider_2/nor_1/A divider_2/and_0/A 0.01fF -C370 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_1/z1 0.21fF -C371 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C372 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Z3 0.03fF -C373 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C374 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C375 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF -C376 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C377 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C378 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C379 cp_0/a_1710_0# cp_0/out 0.84fF -C380 pd_1/R pd_1/tspc_r_1/Qbar 0.03fF -C381 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C382 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF -C383 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF -C384 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF -C385 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF -C386 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF -C387 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/Out 0.21fF -C388 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF -C389 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C390 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C391 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C392 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF -C393 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C394 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C395 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF -C396 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C397 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/tspc_r_1/Z3 0.11fF -C398 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF -C399 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF -C400 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C401 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF -C402 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF -C403 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C404 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C405 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF -C406 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C407 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF -C408 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C409 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C410 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C411 io_clamp_low[1] io_analog[5] 0.53fF -C412 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C413 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C414 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C415 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a2 0.09fF -C416 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z3 0.16fF -C417 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C418 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF -C419 divbuf_2/OUT divbuf_2/OUT2 0.06fF -C420 divbuf_2/OUT5 divbuf_2/OUT3 0.01fF -C421 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/UP 0.33fF -C422 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C423 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C424 divider_1/tspc_0/Z3 divider_1/tspc_0/a_630_n680# 0.05fF -C425 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF -C426 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C427 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C428 pd_1/R pd_1/tspc_r_0/Z3 0.27fF -C429 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C430 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF -C431 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C432 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C433 divider_2/tspc_0/Z1 divider_2/tspc_0/Z2 1.07fF -C434 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.05fF -C435 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/R 0.29fF -C436 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF -C437 divider_2/nor_1/B divider_2/nor_0/B 0.47fF -C438 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/D 0.03fF -C439 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF -C440 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF -C441 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF -C442 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF -C443 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C444 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C445 divider_0/tspc_0/Z2 divider_0/tspc_0/Z1 1.07fF -C446 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF -C447 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF -C448 pd_1/R pd_1/and_pd_0/Z1 0.02fF -C449 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C450 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C451 divbuf_2/OUT5 divbuf_2/IN 0.00fF -C452 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C453 divider_2/mc2 divider_2/nor_1/B 0.06fF -C454 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z3 0.65fF -C455 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF -C456 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C457 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C458 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C459 divider_1/tspc_0/Z3 divider_1/prescaler_0/Out 0.45fF -C460 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C461 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF -C462 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C463 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C464 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF -C465 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF -C466 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C467 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT5 0.01fF -C468 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C469 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF -C470 divider_0/mc2 divider_0/and_0/out1 0.06fF -C471 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF -C472 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C473 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C474 pd_1/R pd_1/tspc_r_0/Qbar1 0.01fF -C475 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF -C476 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C477 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C478 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C479 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF -C480 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF -C481 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C482 pd_1/tspc_r_0/Z4 pd_1/DIV 0.02fF -C483 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C484 divider_1/tspc_0/Q divider_1/tspc_1/Z4 0.15fF -C485 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF -C486 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C487 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C488 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF -C489 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF -C490 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/Out 0.04fF -C491 divider_2/nor_1/B divider_2/and_0/A 0.26fF -C492 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C493 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C494 divider_1/nor_0/Z1 divider_1/nor_1/B 0.18fF -C495 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF -C496 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF -C497 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C498 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C499 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C500 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF -C501 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF -C502 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF -C503 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C504 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF -C505 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF -C506 divider_0/mc2 divider_0/nor_0/B 0.15fF -C507 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF -C508 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C509 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C510 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C511 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/Out 0.21fF -C512 divider_1/nor_1/A divider_1/and_0/A 0.01fF -C513 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C514 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C515 divbuf_2/OUT divbuf_2/OUT4 1.11fF -C516 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF -C517 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C518 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C519 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF -C520 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF -C521 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF -C522 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C523 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C524 divider_2/and_0/out1 divider_2/and_0/B 0.18fF -C525 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C526 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C527 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C528 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Qbar1 0.20fF -C529 divider_1/tspc_0/Z3 divider_1/nor_1/A 0.38fF -C530 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C531 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF -C532 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF -C533 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z3 0.33fF -C534 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF -C535 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF -C536 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.45fF -C537 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C538 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C539 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C540 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C541 divider_1/mc2 divider_1/nor_1/A 0.04fF -C542 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF -C543 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Q 0.04fF -C544 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C545 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C546 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF -C547 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C548 divider_2/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.01fF -C549 divider_2/and_0/OUT divider_2/clk 0.04fF -C550 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C551 divider_0/tspc_0/Z2 divider_0/nor_1/A 0.23fF -C552 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C553 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF -C554 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF -C555 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/switch_1/vin 0.19fF -C556 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF -C557 divider_2/tspc_0/Q divider_2/tspc_0/a_630_n680# 0.04fF -C558 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF -C559 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z4 0.36fF -C560 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF -C561 divider_1/nor_1/B divider_1/nor_0/B 0.47fF -C562 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/D 0.03fF -C563 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF -C564 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF -C565 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF -C566 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C567 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF -C568 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C569 divider_2/nor_0/B divider_2/and_0/B 0.29fF -C570 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C571 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C572 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C573 divider_1/tspc_1/a_630_n680# divider_1/tspc_0/Q 0.01fF -C574 divider_0/mc2 divider_0/and_0/A 0.16fF -C575 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C576 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C577 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C578 ro_complete_0/a4 ro_complete_0/cbank_0/switch_0/vin 0.12fF -C579 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C580 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C581 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF -C582 divider_2/mc2 divider_2/and_0/B 0.20fF -C583 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C584 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C585 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C586 ro_complete_0/a0 ro_complete_0/cbank_0/switch_4/vin 0.13fF -C587 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/mc2 0.33fF -C588 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C589 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C590 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF -C591 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C592 divider_1/tspc_0/Z3 divider_1/tspc_0/Z2 0.16fF -C593 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF -C594 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF -C595 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF -C596 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C597 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF -C598 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF -C599 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF -C600 divbuf_3/OUT5 divbuf_3/IN 0.00fF -C601 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF -C602 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF -C603 divbuf_6/IN divbuf_6/OUT5 0.00fF -C604 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C605 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C606 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF -C607 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C608 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF -C609 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z3 0.25fF -C610 divider_2/nor_1/A divider_2/tspc_0/a_630_n680# 0.35fF -C611 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/Out 0.11fF -C612 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF -C613 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF -C614 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF -C615 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C616 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C617 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF -C618 io_clamp_high[0] io_analog[4] 0.53fF -C619 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF -C620 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C621 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF -C622 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C623 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/Out 0.04fF -C624 divider_1/nor_1/B divider_1/and_0/A 0.26fF -C625 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF -C626 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF -C627 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF -C628 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF -C629 divider_2/and_0/A divider_2/and_0/B 0.18fF -C630 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF -C631 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C632 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C633 pd_1/R pd_1/tspc_r_1/Z3 0.29fF -C634 pd_1/tspc_r_0/Z1 pd_1/DIV 0.17fF -C635 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF -C636 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C637 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C638 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF -C639 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C640 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF -C641 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C642 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C643 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C644 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF -C645 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF -C646 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF -C647 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_0/z1 0.24fF -C648 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/Out 0.19fF -C649 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF -C650 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C651 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C652 divider_1/mc2 divider_1/nor_1/B 0.06fF -C653 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_0/D 0.16fF -C654 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C655 cp_0/a_1710_n2840# cp_0/upbar 0.29fF -C656 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF -C657 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF -C658 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C659 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C660 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF -C661 divider_1/nor_1/B divider_1/tspc_1/Q 0.51fF -C662 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF -C663 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C664 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF -C665 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF -C666 divider_1/and_0/out1 divider_1/and_0/B 0.18fF -C667 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF -C668 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF -C669 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF -C670 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.26fF -C671 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF -C672 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C673 divider_2/nor_1/A divider_2/prescaler_0/m1_2700_2190# 0.01fF -C674 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF -C675 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF -C676 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C677 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C678 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C679 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C680 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF -C681 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF -C682 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF -C683 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C684 divbuf_1/OUT3 divbuf_1/OUT5 0.01fF -C685 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF -C686 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C687 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C688 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C689 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C690 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C691 pd_1/and_pd_0/Z1 pd_1/UP 0.06fF -C692 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C693 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C694 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Z4 0.08fF -C695 divider_1/and_0/OUT divider_1/clk 0.04fF -C696 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C697 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF -C698 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C699 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C700 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF -C701 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF -C702 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C703 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF -C704 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF -C705 divider_0/nor_1/B divider_0/nor_0/B 0.47fF -C706 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF -C707 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C708 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C709 pd_0/tspc_r_1/Qbar pd_0/UP 0.21fF -C710 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C711 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF -C712 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF -C713 divider_1/nor_0/B divider_1/and_0/B 0.29fF -C714 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C715 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C716 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF -C717 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF -C718 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C719 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C720 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C721 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C722 divider_0/nor_1/A divider_0/and_0/A 0.01fF -C723 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C724 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF -C725 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C726 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C727 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF -C728 divider_2/mc2 divider_2/and_0/OUT 0.05fF -C729 divbuf_1/OUT divbuf_1/OUT4 1.11fF -C730 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF -C731 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF -C732 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT3 5.16fF -C733 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C734 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF -C735 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF -C736 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C737 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF -C738 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF -C739 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C740 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C741 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Z3 0.38fF -C742 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF -C743 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.45fF -C744 filter_0/a_4216_n2998# filter_0/v 0.31fF -C745 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF -C746 divider_2/nor_1/A divider_2/prescaler_0/Out 0.15fF -C747 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF -C748 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C749 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.01fF -C750 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF -C751 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Q 0.05fF -C752 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C753 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF -C754 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C755 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C756 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C757 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C758 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C759 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z4 0.65fF -C760 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C761 divider_2/nor_1/A divider_2/tspc_0/Q 0.55fF -C762 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF -C763 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF -C764 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF -C765 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C766 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C767 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF -C768 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF -C769 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF -C770 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF -C771 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C772 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF -C773 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF -C774 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF -C775 divider_2/tspc_0/Z3 divider_2/prescaler_0/Out 0.45fF -C776 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/Q 0.04fF -C777 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF -C778 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C779 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF -C780 pd_0/and_pd_0/Z1 pd_0/UP 0.06fF -C781 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C782 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C783 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C784 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF -C785 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C786 divider_0/nor_1/B divider_0/and_0/A 0.26fF -C787 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF -C788 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C789 divider_2/tspc_0/Q divider_2/tspc_0/Z3 0.05fF -C790 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF -C791 divider_1/and_0/A divider_1/and_0/B 0.18fF -C792 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C793 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C794 ro_complete_0/cbank_2/v ro_complete_0/cbank_0/v 0.04fF -C795 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C796 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C797 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C798 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C799 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF -C800 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C801 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C802 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C803 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF -C804 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF -C805 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF -C806 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C807 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_0/z1 0.24fF -C808 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/Out 0.19fF -C809 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C810 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.01fF -C811 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C812 ro_complete_0/a3 ro_complete_0/cbank_0/switch_1/vin 0.13fF -C813 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF -C814 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT5 0.02fF -C815 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF -C816 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C817 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF -C818 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C819 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF -C820 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C821 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C822 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C823 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF -C824 divider_1/mc2 divider_1/and_0/B 0.20fF -C825 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C826 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF -C827 pll_full_0/cp_0/a_1710_0# pll_full_0/pd_0/DOWN 0.04fF -C828 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF -C829 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.26fF -C830 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C831 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/UP 0.21fF -C832 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C833 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF -C834 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF -C835 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C836 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C837 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF -C838 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C839 divider_2/nor_1/A divider_2/tspc_0/Z3 0.38fF -C840 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF -C841 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z3 0.20fF -C842 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF -C843 divider_2/tspc_0/Z4 divider_2/prescaler_0/Out 0.12fF -C844 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.64fF -C845 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C846 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT5 0.02fF -C847 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C848 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF -C849 divider_0/tspc_0/Z2 divider_0/tspc_0/a_630_n680# 0.01fF -C850 pd_0/DIV pd_0/R 0.51fF -C851 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C852 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF -C853 divider_0/and_0/OUT divider_0/clk 0.04fF -C854 cp_0/upbar cp_0/down 0.02fF -C855 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C856 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF -C857 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C858 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C859 divider_1/tspc_0/Z4 divider_1/prescaler_0/Out 0.12fF -C860 divbuf_1/OUT divbuf_1/OUT5 43.38fF -C861 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF -C862 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF -C863 divider_2/tspc_2/Z3 divider_2/Out 0.05fF -C864 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF -C865 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT3 0.01fF -C866 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C867 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C868 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C869 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C870 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C871 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C872 divider_0/nor_0/B divider_0/and_0/B 0.29fF -C873 filter_0/a_4216_n5230# filter_0/v 0.19fF -C874 pd_1/tspc_r_1/z5 pd_1/UP 0.03fF -C875 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C876 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C877 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C878 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF -C879 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF -C880 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF -C881 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C882 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF -C883 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF -C884 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF -C885 divider_2/and_0/B divider_2/and_0/Z1 0.07fF -C886 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF -C887 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF -C888 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C889 pd_1/tspc_r_0/Qbar1 pd_1/DIV 0.12fF -C890 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C891 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C892 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C893 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF -C894 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C895 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C896 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C897 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF -C898 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF -C899 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF -C900 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C901 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/a_740_n680# 0.19fF -C902 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C903 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C904 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF -C905 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF -C906 pd_1/R pd_1/UP 0.45fF -C907 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z1 0.09fF -C908 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF -C909 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C910 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF -C911 divider_2/tspc_0/Q divider_2/nor_1/B 0.22fF -C912 divider_2/nor_1/A divider_2/tspc_0/Z4 0.21fF -C913 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.01fF -C914 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF -C915 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C916 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF -C917 divbuf_1/IN divbuf_1/OUT5 0.00fF -C918 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C919 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF -C920 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C921 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C922 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C923 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C924 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C925 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C926 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF -C927 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C928 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF -C929 io_clamp_low[2] io_analog[6] 0.53fF -C930 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C931 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.45fF -C932 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C933 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C934 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF -C935 divider_1/nor_1/A divider_1/prescaler_0/Out 0.15fF -C936 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Q 0.04fF -C937 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF -C938 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF -C939 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C940 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF -C941 divbuf_1/OUT3 divbuf_1/OUT2 1.37fF -C942 divider_2/tspc_0/Z3 divider_2/tspc_0/Z4 0.65fF -C943 divbuf_4/IN divbuf_4/OUT5 0.00fF -C944 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF -C945 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT 0.26fF -C946 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT5 20.26fF -C947 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C948 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C949 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Z1 0.06fF -C950 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C951 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C952 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C953 pd_1/tspc_r_0/Z2 pd_1/DIV 0.19fF -C954 divider_1/tspc_0/Z4 divider_1/nor_1/A 0.21fF -C955 divider_0/and_0/A divider_0/and_0/B 0.18fF -C956 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF -C957 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C958 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C959 pll_full_0/pd_0/REF pll_full_0/pd_0/R 0.61fF -C960 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF -C961 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C962 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C963 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF -C964 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C965 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF -C966 divbuf_5/IN divbuf_5/OUT5 0.00fF -C967 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C968 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C969 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF -C970 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF -C971 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF -C972 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF -C973 cp_0/a_1710_0# cp_0/down 0.32fF -C974 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF -C975 pd_1/R pd_1/and_pd_0/Out1 0.33fF -C976 pd_0/tspc_r_1/z5 pd_0/UP 0.03fF -C977 divider_2/nor_1/A divider_2/nor_1/B 1.21fF -C978 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF -C979 divbuf_2/OUT divbuf_2/a_492_n240# 0.00fF -C980 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C981 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C982 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF -C983 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF -C984 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C985 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C986 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C987 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF -C988 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C989 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C990 divider_1/mc2 divider_1/and_0/OUT 0.05fF -C991 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Q 0.05fF -C992 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C993 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF -C994 divbuf_0/IN divbuf_0/OUT5 0.00fF -C995 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C996 divider_2/tspc_0/Q divider_2/tspc_1/Z3 0.45fF -C997 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C998 divbuf_1/IN divbuf_1/a_492_n240# 0.13fF -C999 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF -C1000 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF -C1001 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C1002 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF -C1003 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C1004 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF -C1005 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C1006 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF -C1007 divider_1/tspc_0/Z2 divider_1/prescaler_0/Out 0.11fF -C1008 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.64fF -C1009 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF -C1010 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF -C1011 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF -C1012 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.01fF -C1013 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF -C1014 pd_1/R pd_1/tspc_r_1/Z2 0.21fF -C1015 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF -C1016 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C1017 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C1018 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C1019 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF -C1020 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF -C1021 vdda1 vssa1 548.48fF -C1022 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C1023 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1024 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF -C1025 divider_1/tspc_2/Z3 divider_1/Out 0.05fF -C1026 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF -C1027 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF -C1028 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C1029 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C1030 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF -C1031 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF -C1032 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z2 0.25fF -C1033 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C1034 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1035 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C1036 divider_2/tspc_0/Q divider_2/tspc_1/Z2 0.14fF -C1037 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF -C1038 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF -C1039 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C1040 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Q 0.20fF -C1041 divider_1/and_0/B divider_1/and_0/Z1 0.07fF -C1042 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C1043 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF -C1044 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF -C1045 divider_2/prescaler_0/tspc_0/Q divider_2/clk 0.05fF -C1046 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF -C1047 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C1048 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C1049 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF -C1050 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C1051 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF -C1052 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C1053 pd_0/R pd_0/REF 0.61fF -C1054 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF -C1055 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C1056 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF -C1057 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C1058 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1059 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1060 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C1061 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C1062 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C1063 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z3 0.06fF -C1064 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1065 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF -C1066 divbuf_2/OUT5 divbuf_2/OUT2 0.02fF -C1067 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF -C1068 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1069 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C1070 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C1071 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C1072 pd_1/R pd_1/DIV 0.51fF -C1073 pd_1/tspc_r_0/Qbar1 pd_1/DOWN 0.11fF -C1074 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1075 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF -C1076 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF -C1077 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF -C1078 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF -C1079 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF -C1080 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF -C1081 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.03fF -C1082 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/UP 0.06fF -C1083 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C1084 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C1085 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1086 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF -C1087 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C1088 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/nor_1/A 0.38fF -C1089 divider_2/nor_1/A divider_2/tspc_1/Z2 0.15fF -C1090 divider_1/nor_1/A divider_1/tspc_0/Z2 0.23fF -C1091 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C1092 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF -C1093 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C1094 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF -C1095 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C1096 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C1097 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C1098 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1099 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF -C1100 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF -C1101 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C1102 divbuf_1/OUT divbuf_1/OUT2 0.06fF -C1103 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF -C1104 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF -C1105 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/tspc_r_1/Qbar 0.05fF -C1106 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF -C1107 divider_1/tspc_0/Z3 divider_1/tspc_0/Q 0.05fF -C1108 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C1109 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF -C1110 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C1111 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C1112 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF -C1113 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1114 divider_2/nor_1/A divider_2/and_0/B 0.08fF -C1115 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF -C1116 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C1117 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C1118 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF -C1119 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF -C1120 divider_2/mc2 divider_2/and_0/out1 0.06fF -C1121 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C1122 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C1123 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C1124 divider_1/nor_1/A divider_1/nor_1/B 1.21fF -C1125 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C1126 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/R 0.21fF -C1127 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF -C1128 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF -C1129 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C1130 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C1131 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF -C1132 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF -C1133 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF -C1134 divider_2/tspc_0/Z2 divider_2/prescaler_0/Out 0.11fF -C1135 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/Q 0.19fF -C1136 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.14fF -C1137 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C1138 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C1139 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_740_n680# 0.08fF -C1140 divider_0/mc2 divider_0/nor_1/A 0.04fF -C1141 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C1142 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C1143 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF -C1144 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C1145 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.05fF -C1146 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF -C1147 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF -C1148 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF -C1149 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/Qbar 0.01fF -C1150 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF -C1151 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF -C1152 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C1153 divbuf_1/OUT divbuf_1/OUT3 0.26fF -C1154 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF -C1155 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C1156 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF -C1157 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.29fF -C1158 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C1159 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C1160 io_clamp_low[2] io_clamp_high[2] 0.53fF -C1161 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1162 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C1163 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF -C1164 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C1165 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C1166 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF -C1167 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF -C1168 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C1169 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1170 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C1171 divider_0/tspc_2/Z3 divider_0/Out 0.05fF -C1172 io_clamp_high[1] io_analog[5] 0.53fF -C1173 divider_2/nor_0/Z1 divider_2/nor_1/B 0.18fF -C1174 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF -C1175 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF -C1176 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF -C1177 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF -C1178 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF -C1179 divider_2/mc2 divider_2/nor_0/B 0.15fF -C1180 divbuf_2/OUT divbuf_2/OUT3 0.26fF -C1181 divbuf_2/OUT5 divbuf_2/OUT4 20.26fF -C1182 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF -C1183 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C1184 divider_2/and_0/out1 divider_2/and_0/A 0.01fF -C1185 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C1186 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF -C1187 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C1188 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C1189 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF -C1190 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF -C1191 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C1192 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.15fF -C1193 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF -C1194 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF -C1195 divider_1/prescaler_0/tspc_0/Q divider_1/clk 0.05fF -C1196 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C1197 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF -C1198 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF -C1199 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C1200 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF -C1201 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C1202 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF -C1203 divider_0/mc2 divider_0/nor_1/B 0.06fF -C1204 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF -C1205 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C1206 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C1207 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C1208 divider_2/nor_1/A divider_2/tspc_0/Z2 0.23fF -C1209 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/pd_0/UP 0.03fF -C1210 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF -C1211 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C1212 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF -C1213 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF -C1214 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF -C1215 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C1216 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C1217 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C1218 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF -C1219 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C1220 divbuf_0/OUT5 divbuf_0/OUT 43.38fF -C1221 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z4 0.00fF -C1222 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF -C1223 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.03fF -C1224 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF -C1225 divider_2/tspc_0/Z3 divider_2/tspc_0/Z2 0.16fF -C1226 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF -C1227 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF -C1228 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C1229 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C1230 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF -C1231 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z4 0.00fF -C1232 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT 0.00fF -C1233 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1234 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C1235 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF -C1236 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF -C1237 pd_1/R pd_1/DOWN 0.36fF -C1238 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C1239 pd_1/and_pd_0/Out1 pd_1/UP 0.33fF -C1240 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1241 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF -C1242 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF -C1243 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z1 0.71fF -C1244 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/mc2 0.33fF -C1245 divider_2/mc2 divider_2/and_0/A 0.16fF -C1246 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF -C1247 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.06fF -C1248 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF -C1249 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C1250 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C1251 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF -C1252 pd_1/tspc_r_0/z5 pd_1/DIV 0.04fF -C1253 divider_1/nor_1/A divider_1/tspc_1/Z2 0.15fF -C1254 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C1255 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Z3 0.38fF -C1256 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_0/D 0.16fF -C1257 divider_2/nor_1/B divider_2/and_0/B 0.31fF -C1258 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF -C1259 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/D 0.32fF -C1260 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF -C1261 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF -C1262 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF -C1263 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C1264 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C1265 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF -C1266 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C1267 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF -C1268 pd_1/REF pd_1/tspc_r_1/z5 0.04fF -C1269 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF -C1270 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C1271 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C1272 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/R 0.30fF -C1273 divider_2/tspc_0/Q divider_2/tspc_1/a_630_n680# 0.01fF -C1274 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Q 0.04fF -C1275 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF -C1276 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF -C1277 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF -C1278 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C1279 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/REF 0.12fF -C1280 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF -C1281 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF -C1282 io_clamp_low[0] io_analog[4] 0.53fF -C1283 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C1284 divider_1/nor_1/A divider_1/and_0/B 0.08fF -C1285 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF -C1286 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/Q 0.19fF -C1287 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.14fF -C1288 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF -C1289 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF -C1290 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF -C1291 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF -C1292 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF -C1293 ro_complete_0/a1 ro_complete_0/cbank_0/switch_3/vin 0.14fF -C1294 ro_complete_0/a3 ro_complete_0/cbank_0/switch_2/vin 0.09fF -C1295 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1296 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF -C1297 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C1298 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF -C1299 pd_1/R pd_1/REF 0.61fF -C1300 pd_0/R pd_0/UP 0.45fF -C1301 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C1302 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C1303 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF -C1304 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.29fF -C1305 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF -C1306 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C1307 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF -C1308 ro_complete_0/a0 ro_complete_0/cbank_0/switch_5/vin 0.09fF -C1309 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C1310 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C1311 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF -C1312 pd_0/and_pd_0/Out1 pd_0/UP 0.33fF -C1313 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C1314 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C1315 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C1316 divider_1/nor_1/A divider_1/tspc_1/Z4 0.02fF -C1317 divider_1/nor_1/B divider_1/tspc_1/Z3 0.38fF -C1318 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF -C1319 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF -C1320 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF -C1321 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF -C1322 divider_1/and_0/out1 divider_1/and_0/A 0.01fF -C1323 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.45fF -C1324 pll_full_0/cp_0/down pll_full_0/cp_0/upbar 0.02fF -C1325 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C1326 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C1327 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1328 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/a_740_n680# 0.33fF -C1329 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF -C1330 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1331 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C1332 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C1333 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF -C1334 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF -C1335 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF -C1336 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF -C1337 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF -C1338 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF -C1339 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF -C1340 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF -C1341 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF -C1342 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C1343 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF -C1344 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1345 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C1346 divider_0/nor_1/B divider_0/nor_1/A 1.21fF -C1347 divider_0/mc2 divider_0/and_0/B 0.20fF -C1348 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF -C1349 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C1350 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C1351 divider_1/mc2 divider_1/and_0/out1 0.06fF -C1352 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF -C1353 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C1354 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C1355 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF -C1356 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C1357 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1358 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF -C1359 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF -C1360 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF -C1361 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C1362 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C1363 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/a_630_n680# 0.05fF -C1364 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C1365 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C1366 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF -C1367 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C1368 divider_1/nor_1/B divider_1/tspc_1/Z2 0.30fF -C1369 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF -C1370 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF -C1371 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF -C1372 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF -C1373 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF -C1374 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF -C1375 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/tspc_2/D 0.04fF -C1376 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF -C1377 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C1378 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C1379 ro_complete_0/cbank_1/v ro_complete_0/cbank_0/v 1.27fF -C1380 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C1381 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C1382 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C1383 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF -C1384 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C1385 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C1386 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C1387 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF -C1388 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF -C1389 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.06fF -C1390 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF -C1391 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF -C1392 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF -C1393 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF -C1394 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF -C1395 divider_2/nor_0/B divider_2/Out 0.22fF -C1396 io_clamp_low[1] io_clamp_high[1] 0.53fF -C1397 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1398 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF -C1399 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C1400 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C1401 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF -C1402 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF -C1403 divider_1/mc2 divider_1/nor_0/B 0.15fF -Xpd_0 VDD gnd pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd -Xpd_1 VDD gnd pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd -Xcp_0 cp_0/vbias vdd gnd cp_0/out cp_0/down cp_0/upbar cp -Xfilter_0 gnd filter_0/v filter +C0 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C1 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C2 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C3 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C4 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF +C5 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C6 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF +C7 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF +C8 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a4 0.12fF +C9 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C10 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C11 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF +C12 divider_1/tspc_2/Z3 divider_1/Out 0.05fF +C13 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C14 divider_2/tspc_0/Z2 divider_2/prescaler_0/Out 0.11fF +C15 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/Q 0.04fF +C16 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF +C17 divider_2/nor_0/Z1 gnd 0.01fF +C18 io_clamp_high[2] io_analog[6] 0.53fF +C19 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C20 divider_1/nor_0/Z1 divider_1/nor_1/B 0.18fF +C21 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C22 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z4 0.14fF +C23 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C24 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C25 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C26 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C27 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C28 gnd pll_full_0/divider_0/tspc_0/Z2 0.16fF +C29 divider_2/nor_1/A divider_2/and_0/A 0.01fF +C30 divider_2/nor_1/Z1 divider_2/nor_1/B 0.06fF +C31 divider_1/tspc_0/Z2 divider_1/prescaler_0/Out 0.11fF +C32 divider_1/tspc_0/Z1 divider_1/nor_1/A 0.03fF +C33 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF +C34 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF +C35 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C36 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF +C37 divider_2/tspc_0/Z3 divider_2/tspc_0/Q 0.05fF +C38 divider_1/and_0/A divider_1/and_0/B 0.18fF +C39 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C40 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF +C41 divider_0/tspc_0/a_630_n680# gnd 0.62fF +C42 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C43 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C44 divider_1/prescaler_0/nand_1/z1 gnd 0.16fF +C45 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C46 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF +C47 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C48 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C49 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C50 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C51 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF +C52 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF +C53 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF +C54 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C55 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C56 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C57 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C58 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF +C59 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C60 divider_2/tspc_1/Z2 divider_2/tspc_1/a_630_n680# 0.01fF +C61 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C62 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C63 divider_1/and_0/Z1 gnd 0.41fF +C64 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C65 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C66 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C67 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C68 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF +C69 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C70 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF +C71 pll_full_0/divider_0/nor_1/A gnd 1.05fF +C72 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C73 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C74 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C75 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF +C76 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF +C77 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/switch_5/vin 0.20fF +C78 divider_1/and_0/OUT gnd 0.28fF +C79 divider_1/nor_1/Z1 gnd 0.01fF +C80 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C81 divider_2/prescaler_0/tspc_0/D gnd 0.05fF +C82 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C83 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C84 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C85 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C86 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C87 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C88 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF +C89 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF +C90 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C91 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C92 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/v 1.30fF +C93 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.64fF +C94 divider_2/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C95 divider_1/tspc_0/Z3 gnd 0.27fF +C96 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C97 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C98 divider_2/and_0/out1 gnd 0.23fF +C99 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF +C100 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z1 1.07fF +C101 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF +C102 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.01fF +C103 divider_0/and_0/OUT divider_0/clk 0.04fF +C104 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C105 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C106 divider_1/nor_1/A divider_1/tspc_0/Z3 0.38fF +C107 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF +C108 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF +C109 divbuf_0/OUT5 divbuf_0/OUT 43.38fF +C110 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C111 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF +C112 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF +C113 ro_complete_1/a0 ro_complete_1/cbank_2/switch_5/vin 0.09fF +C114 divider_0/and_0/OUT gnd 0.28fF +C115 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C116 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C117 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C118 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C119 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C120 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF +C121 cp_0/a_1710_0# cp_0/down 0.32fF +C122 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF +C123 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Z1 0.02fF +C124 pd_1/REF pd_1/tspc_r_1/Qbar1 0.12fF +C125 pll_full_0/divider_0/tspc_1/Z2 gnd 0.16fF +C126 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C127 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C128 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C129 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF +C130 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF +C131 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF +C132 divider_2/and_0/B divider_2/and_0/Z1 0.07fF +C133 divider_1/prescaler_0/tspc_0/Z3 gnd 0.27fF +C134 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C135 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C136 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C137 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C138 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C139 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C140 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF +C141 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C142 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF +C143 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C144 ro_complete_1/a4 ro_complete_1/cbank_1/v 0.05fF +C145 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C146 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF +C147 io_clamp_low[1] io_analog[5] 0.53fF +C148 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C149 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C150 divider_1/tspc_1/Z2 gnd 0.16fF +C151 divider_2/tspc_2/a_630_n680# gnd 0.61fF +C152 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C153 pd_1/DOWN pd_1/tspc_r_1/Qbar 0.02fF +C154 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C155 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C156 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF +C157 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C158 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF +C159 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/Q 0.20fF +C160 divider_1/tspc_1/Z2 divider_1/nor_1/A 0.15fF +C161 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF +C162 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C163 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF +C164 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF +C165 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C166 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C167 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C168 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF +C169 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF +C170 divider_1/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C171 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C172 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C173 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C174 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF +C175 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C176 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF +C177 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF +C178 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF +C179 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C180 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C181 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C182 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF +C183 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C184 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C185 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C186 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF +C187 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C188 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Z3 0.03fF +C189 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF +C190 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.03fF +C191 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF +C192 divider_2/tspc_1/Q divider_2/tspc_1/a_630_n680# 0.04fF +C193 divider_2/mc2 divider_2/nor_0/B 0.15fF +C194 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C195 divbuf_4/IN divbuf_4/OUT5 0.00fF +C196 ro_complete_1/cbank_1/v ro_complete_1/cbank_2/v 1.36fF +C197 divider_2/and_0/out1 divider_2/and_0/A 0.01fF +C198 divider_1/tspc_0/Z2 gnd 0.16fF +C199 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_1/A 0.01fF +C200 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C201 divider_2/prescaler_0/tspc_1/Z3 gnd 0.27fF +C202 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C203 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C204 pd_1/UP pd_1/and_pd_0/Out1 0.33fF +C205 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF +C206 pll_full_0/divider_0/tspc_1/Z4 gnd 0.44fF +C207 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C208 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C209 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF +C210 divider_1/mc2 divider_1/and_0/out1 0.06fF +C211 divider_1/tspc_0/Z2 divider_1/nor_1/A 0.23fF +C212 divider_0/and_0/A divider_0/and_0/B 0.18fF +C213 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF +C214 divider_2/nor_1/B divider_2/and_0/B 0.31fF +C215 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF +C216 divider_1/prescaler_0/tspc_0/D gnd 0.05fF +C217 ro_complete_1/a5 ro_complete_1/cbank_1/switch_0/vin 0.09fF +C218 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/cbank_0/v 1.30fF +C219 divbuf_5/IN divbuf_5/OUT5 0.00fF +C220 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C221 divider_2/prescaler_0/nand_0/z1 gnd 0.16fF +C222 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C223 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C224 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C225 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C226 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C227 gnd pll_full_0/divider_0/tspc_2/Z3 0.27fF +C228 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C229 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z2 0.01fF +C230 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF +C231 divider_1/nor_1/Z1 divider_1/nor_1/B 0.06fF +C232 ro_complete_1/a2 ro_complete_1/cbank_0/switch_3/vin 0.09fF +C233 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF +C234 ro_complete_1/cbank_1/switch_2/vin ro_complete_1/cbank_1/v 1.30fF +C235 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C236 divider_2/clk gnd 0.07fF +C237 pd_1/tspc_r_1/Qbar pd_1/R 0.03fF +C238 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C239 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C240 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C241 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF +C242 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF +C243 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF +C244 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/v 1.30fF +C245 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C246 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF +C247 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C248 divider_0/prescaler_0/tspc_0/D gnd 0.05fF +C249 ro_complete_1/a0 ro_complete_1/cbank_2/v 0.05fF +C250 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C251 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C252 divider_1/prescaler_0/Out gnd 0.46fF +C253 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C254 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C255 pd_1/tspc_r_1/Z3 pd_1/UP 0.03fF +C256 pll_full_0/divider_0/tspc_1/Q gnd 0.33fF +C257 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C258 divider_1/nor_1/A divider_1/prescaler_0/Out 0.15fF +C259 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.14fF +C260 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C261 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF +C262 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF +C263 divider_1/tspc_0/a_630_n680# gnd 0.62fF +C264 divider_0/and_0/out1 gnd 0.23fF +C265 divider_2/prescaler_0/tspc_2/Z3 gnd 0.27fF +C266 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF +C267 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C268 pd_1/DIV pd_1/tspc_r_0/Z3 0.65fF +C269 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C270 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/a_630_n680# 0.19fF +C271 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C272 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF +C273 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C274 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/a5 0.09fF +C275 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF +C276 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF +C277 divider_1/tspc_1/Q gnd 0.33fF +C278 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C279 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C280 divider_2/nor_0/B gnd 1.08fF +C281 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C282 divider_1/tspc_1/Z2 divider_1/nor_1/B 0.30fF +C283 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF +C284 gnd pll_full_0/divider_0/and_0/B 0.66fF +C285 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C286 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C287 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF +C288 divider_1/and_0/B divider_1/and_0/Z1 0.07fF +C289 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C290 ro_complete_1/a3 ro_complete_1/cbank_2/v 0.05fF +C291 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C292 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF +C293 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF +C294 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF +C295 divider_2/prescaler_0/tspc_0/Q divider_2/clk 0.05fF +C296 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C297 divider_2/mc2 gnd 1.36fF +C298 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C299 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C300 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF +C301 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C302 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C303 divider_2/nor_1/A divider_2/tspc_0/a_630_n680# 0.35fF +C304 divider_1/and_0/OUT divider_1/and_0/B 0.01fF +C305 cp_0/a_1710_n2840# cp_0/upbar 0.29fF +C306 pd_1/R pd_1/REF 0.61fF +C307 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C308 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C309 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF +C310 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C311 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C312 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF +C313 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF +C314 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF +C315 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF +C316 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF +C317 divbuf_1/OUT divbuf_1/OUT3 0.26fF +C318 ro_complete_1/a4 ro_complete_1/cbank_1/switch_1/vin 0.09fF +C319 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C320 divider_2/tspc_1/Z2 divider_2/tspc_0/Q 0.14fF +C321 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C322 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C323 divider_0/tspc_2/a_630_n680# gnd 0.61fF +C324 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C325 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C326 divider_2/prescaler_0/tspc_1/Z4 gnd 0.44fF +C327 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF +C328 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C329 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF +C330 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C331 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_0/D 0.16fF +C332 cp_0/upbar cp_0/down 0.02fF +C333 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF +C334 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF +C335 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF +C336 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C337 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C338 ro_complete_1/a3 ro_complete_1/cbank_1/switch_2/vin 0.09fF +C339 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF +C340 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.03fF +C341 divider_2/prescaler_0/tspc_0/Z2 gnd 0.16fF +C342 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C343 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C344 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C345 divider_2/prescaler_0/tspc_1/Q gnd 0.83fF +C346 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C347 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Q 0.20fF +C348 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C349 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C350 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF +C351 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF +C352 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF +C353 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C354 gnd pll_full_0/divider_0/tspc_2/Z4 0.44fF +C355 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF +C356 divider_2/tspc_0/Z3 divider_2/tspc_0/Z1 0.06fF +C357 divider_1/and_0/out1 divider_1/and_0/A 0.01fF +C358 ro_complete_1/a2 ro_complete_1/cbank_2/switch_3/vin 0.09fF +C359 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C360 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/switch_5/vin 0.20fF +C361 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C362 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF +C363 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C364 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C365 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C366 divider_2/nor_1/A divider_2/nor_1/B 1.21fF +C367 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C368 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF +C369 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF +C370 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF +C371 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF +C372 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C373 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C374 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C375 divider_1/tspc_1/Z4 divider_1/tspc_0/Q 0.15fF +C376 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C377 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF +C378 pd_1/REF pd_1/tspc_r_1/z5 0.04fF +C379 pll_full_0/divider_0/tspc_0/a_630_n680# gnd 0.62fF +C380 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF +C381 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C382 divider_1/mc2 divider_1/nor_0/B 0.15fF +C383 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF +C384 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF +C385 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C386 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/REF 0.12fF +C387 divider_2/mc2 divider_2/and_0/A 0.16fF +C388 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF +C389 divider_2/tspc_0/Z4 gnd 0.44fF +C390 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C391 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C392 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C393 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C394 divider_0/clk gnd 0.07fF +C395 divider_2/prescaler_0/tspc_2/Z4 gnd 0.44fF +C396 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C397 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C398 divider_1/tspc_0/a_630_n680# divider_1/nor_1/B 0.01fF +C399 divider_1/tspc_1/Z4 divider_1/tspc_1/Z3 0.65fF +C400 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C401 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C402 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C403 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF +C404 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF +C405 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/Q 0.19fF +C406 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.14fF +C407 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF +C408 ro_complete_1/a5 ro_complete_1/cbank_1/v 0.10fF +C409 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/cbank_0/v 1.30fF +C410 io_clamp_high[0] io_analog[4] 0.53fF +C411 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C412 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C413 divider_1/nor_1/A gnd 1.02fF +C414 divider_0/mc2 divider_0/nor_1/A 0.04fF +C415 divider_2/tspc_2/Z2 gnd 0.16fF +C416 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF +C417 pd_1/DOWN pd_1/tspc_r_0/Qbar1 0.11fF +C418 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C419 pll_full_0/divider_0/nor_1/Z1 gnd 0.01fF +C420 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF +C421 divider_2/nor_1/A divider_2/tspc_0/Z3 0.38fF +C422 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF +C423 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF +C424 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C425 divider_1/tspc_1/Z3 divider_1/tspc_1/Z1 0.06fF +C426 divider_1/tspc_1/Q divider_1/nor_1/B 0.51fF +C427 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF +C428 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF +C429 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF +C430 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C431 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF +C432 divider_2/nor_0/B divider_2/Out 0.22fF +C433 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.29fF +C434 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF +C435 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C436 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C437 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C438 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C439 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C440 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C441 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF +C442 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C443 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF +C444 pd_1/R pd_1/tspc_r_1/Qbar1 0.30fF +C445 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C446 divider_2/nor_0/Z1 divider_2/nor_1/B 0.18fF +C447 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF +C448 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF +C449 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C450 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF +C451 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF +C452 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/Out 0.08fF +C453 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF +C454 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF +C455 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF +C456 ro_complete_1/a2 ro_complete_1/cbank_1/v 0.05fF +C457 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF +C458 divider_0/nor_0/B gnd 1.08fF +C459 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C460 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z3 0.65fF +C461 divider_2/tspc_1/Z3 gnd 0.27fF +C462 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z4 0.12fF +C463 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF +C464 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C465 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C466 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C467 pll_full_0/divider_0/and_0/OUT gnd 0.32fF +C468 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF +C469 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C470 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C471 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C472 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF +C473 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF +C474 divider_1/prescaler_0/tspc_0/Q divider_1/clk 0.05fF +C475 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF +C476 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF +C477 divider_0/tspc_0/Q gnd 0.33fF +C478 ro_complete_1/a3 ro_complete_1/cbank_2/switch_1/vin 0.13fF +C479 divider_1/tspc_1/a_630_n680# gnd 0.62fF +C480 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C481 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF +C482 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C483 divider_2/prescaler_0/tspc_0/Q gnd 0.35fF +C484 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF +C485 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C486 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF +C487 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C488 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C489 filter_0/a_4216_n2998# filter_0/v 0.31fF +C490 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C491 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF +C492 divider_2/nor_1/A divider_2/prescaler_0/Out 0.15fF +C493 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF +C494 ro_complete_1/a2 ro_complete_1/cbank_0/switch_2/vin 0.14fF +C495 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a4 0.09fF +C496 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C497 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C498 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF +C499 ro_complete_1/cbank_1/switch_4/vin ro_complete_1/cbank_1/v 1.30fF +C500 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z4 0.11fF +C501 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C502 divider_2/and_0/A gnd 0.53fF +C503 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF +C504 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF +C505 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C506 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C507 pd_1/tspc_r_0/Qbar1 pd_1/R 0.01fF +C508 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C509 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C510 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C511 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF +C512 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF +C513 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF +C514 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF +C515 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C516 ro_complete_1/cbank_2/switch_2/vin ro_complete_1/cbank_2/v 1.30fF +C517 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C518 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C519 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C520 pd_1/DIV pd_1/tspc_r_0/Z2 0.19fF +C521 pd_0/DOWN pd_0/R 0.36fF +C522 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C523 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C524 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C525 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Z2 0.05fF +C526 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C527 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C528 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C529 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C530 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF +C531 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C532 pd_1/R pd_1/and_pd_0/Z1 0.02fF +C533 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF +C534 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C535 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C536 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF +C537 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C538 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C539 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF +C540 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.06fF +C541 divider_0/nor_0/Z1 gnd 0.01fF +C542 divider_0/tspc_0/Z3 gnd 0.27fF +C543 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C544 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C545 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C546 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C547 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C548 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF +C549 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C550 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF +C551 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF +C552 divbuf_3/IN divbuf_3/OUT5 0.00fF +C553 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/D 0.32fF +C554 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF +C555 divider_0/nor_1/B gnd 1.10fF +C556 divider_1/nor_1/B gnd 1.10fF +C557 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C558 divider_2/Out gnd 0.29fF +C559 pd_1/DOWN pd_1/R 0.36fF +C560 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF +C561 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C562 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C563 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF +C564 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF +C565 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar1 0.11fF +C566 divider_1/nor_1/A divider_1/nor_1/B 1.21fF +C567 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C568 ro_complete_1/a1 ro_complete_1/cbank_2/v 0.05fF +C569 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF +C570 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF +C571 divider_1/tspc_2/Z3 gnd 0.27fF +C572 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C573 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C574 divider_2/nor_1/A divider_2/tspc_0/Z2 0.23fF +C575 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF +C576 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF +C577 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/Z3 0.16fF +C578 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF +C579 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/Q 0.19fF +C580 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/Out 0.11fF +C581 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF +C582 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF +C583 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF +C584 divider_0/tspc_2/Z2 gnd 0.16fF +C585 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C586 divider_2/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C587 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C588 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C589 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C590 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF +C591 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF +C592 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C593 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C594 cp_0/a_10_n50# cp_0/vbias 0.19fF +C595 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF +C596 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF +C597 divider_1/mc2 divider_1/and_0/A 0.16fF +C598 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C599 pll_full_0/divider_0/prescaler_0/tspc_0/D gnd 0.05fF +C600 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF +C601 divider_1/nor_0/B divider_1/Out 0.22fF +C602 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.29fF +C603 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF +C604 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C605 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C606 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF +C607 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF +C608 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C609 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF +C610 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C611 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C612 divider_2/prescaler_0/tspc_2/D gnd 0.05fF +C613 pd_1/tspc_r_0/Qbar pd_1/tspc_r_0/Qbar1 0.01fF +C614 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C615 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C616 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C617 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z2 0.01fF +C618 filter_0/a_4216_n5230# filter_0/v 0.19fF +C619 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF +C620 divider_1/tspc_1/a_630_n680# divider_1/nor_1/B 0.35fF +C621 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_2/a_740_n680# 0.01fF +C622 gnd pll_full_0/divider_0/and_0/out1 0.29fF +C623 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C624 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C625 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF +C626 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF +C627 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C628 ro_complete_1/cbank_1/switch_0/vin ro_complete_1/cbank_1/v 1.45fF +C629 divider_0/tspc_1/Z3 gnd 0.27fF +C630 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C631 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF +C632 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C633 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C634 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF +C635 pd_1/tspc_r_1/Z2 pd_1/REF 0.19fF +C636 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/z5 0.11fF +C637 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF +C638 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF +C639 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF +C640 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C641 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C642 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C643 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C644 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C645 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C646 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C647 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/switch_5/vin 0.20fF +C648 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF +C649 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C650 divider_1/and_0/B gnd 0.45fF +C651 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z2 0.09fF +C652 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF +C653 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C654 divider_0/mc2 divider_0/and_0/B 0.20fF +C655 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C656 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C657 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C658 cp_0/a_1710_n2840# cp_0/out 0.61fF +C659 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF +C660 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C661 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C662 divider_2/nor_1/A divider_2/tspc_0/Q 0.55fF +C663 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C664 divider_1/nor_1/A divider_1/and_0/B 0.08fF +C665 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/Out 0.05fF +C666 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF +C667 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C668 divider_2/prescaler_0/m1_2700_2190# gnd 0.22fF +C669 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C670 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C671 divider_0/and_0/A gnd 0.53fF +C672 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C673 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C674 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C675 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C676 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C677 pd_1/DIV pd_1/tspc_r_0/z5 0.04fF +C678 pd_1/tspc_r_0/Qbar pd_1/DOWN 0.21fF +C679 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C680 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C681 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C682 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C683 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF +C684 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C685 gnd pll_full_0/divider_0/tspc_2/a_630_n680# 0.61fF +C686 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF +C687 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF +C688 divider_1/tspc_0/Q divider_1/tspc_0/Z3 0.05fF +C689 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF +C690 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C691 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF +C692 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/tspc_2/D 0.04fF +C693 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF +C694 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C695 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C696 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C697 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF +C698 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C699 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF +C700 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C701 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C702 pll_full_0/divider_0/tspc_0/Z4 gnd 0.44fF +C703 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF +C704 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF +C705 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C706 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_2/vin 0.20fF +C707 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C708 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF +C709 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C710 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF +C711 divider_1/prescaler_0/tspc_0/Z4 gnd 0.44fF +C712 ro_complete_1/cbank_1/switch_5/vin ro_complete_1/cbank_1/v 1.30fF +C713 divider_1/tspc_2/Z4 gnd 0.44fF +C714 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF +C715 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C716 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C717 divider_2/nor_1/A divider_2/tspc_1/Z2 0.15fF +C718 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF +C719 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_630_n680# 0.05fF +C720 pd_1/tspc_r_1/Qbar pd_1/and_pd_0/Out1 0.05fF +C721 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF +C722 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C723 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/D 0.32fF +C724 divider_1/prescaler_0/tspc_1/Z4 divider_1/prescaler_0/Out 0.28fF +C725 divbuf_1/OUT4 divbuf_1/OUT3 5.16fF +C726 divider_2/nor_1/B divider_2/nor_0/B 0.47fF +C727 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF +C728 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF +C729 divider_0/Out gnd 0.29fF +C730 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C731 divider_2/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C732 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF +C733 divider_1/and_0/OUT divider_1/prescaler_0/m1_2700_2190# 0.14fF +C734 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C735 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C736 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C737 pd_0/R pd_0/UP 0.45fF +C738 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C739 pll_full_0/divider_0/nor_0/Z1 gnd 0.01fF +C740 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C741 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF +C742 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF +C743 pll_full_0/divider_0/prescaler_0/nand_0/z1 gnd 0.16fF +C744 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C745 divider_2/mc2 divider_2/nor_1/B 0.06fF +C746 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF +C747 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF +C748 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF +C749 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/Out 0.11fF +C750 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF +C751 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C752 io_clamp_low[2] io_analog[6] 0.53fF +C753 divider_1/prescaler_0/tspc_1/Z3 gnd 0.27fF +C754 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C755 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C756 divider_2/prescaler_0/nand_1/z1 gnd 0.16fF +C757 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF +C758 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C759 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C760 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF +C761 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF +C762 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C763 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C764 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C765 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C766 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C767 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C768 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF +C769 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C770 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF +C771 gnd pll_full_0/divider_0/clk 0.08fF +C772 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C773 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF +C774 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C775 ro_complete_1/a0 ro_complete_1/cbank_1/switch_5/vin 0.09fF +C776 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C777 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C778 divider_2/and_0/Z1 gnd 0.41fF +C779 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C780 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C781 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C782 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C783 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C784 divider_2/tspc_0/Z4 divider_2/tspc_0/a_630_n680# 0.12fF +C785 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_630_n680# 0.12fF +C786 divider_1/and_0/OUT divider_1/clk 0.04fF +C787 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z3 0.06fF +C788 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C789 divider_0/nor_0/B divider_0/Out 0.22fF +C790 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF +C791 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C792 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C793 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C794 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF +C795 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF +C796 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C797 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C798 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C799 ro_complete_1/a2 ro_complete_1/cbank_2/switch_2/vin 0.14fF +C800 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/REF 0.19fF +C801 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C802 ro_complete_1/cbank_2/switch_4/vin ro_complete_1/cbank_2/v 1.30fF +C803 divider_2/prescaler_0/Out divider_2/clk 0.51fF +C804 divider_0/prescaler_0/tspc_2/D gnd 0.05fF +C805 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C806 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C807 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C808 divider_2/tspc_0/a_630_n680# gnd 0.62fF +C809 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C810 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C811 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C812 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C813 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF +C814 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C815 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF +C816 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF +C817 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C818 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF +C819 divider_1/nor_1/B divider_1/and_0/B 0.31fF +C820 divbuf_2/IN divbuf_2/OUT5 0.00fF +C821 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C822 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/switch_0/vin 0.19fF +C823 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Z3 0.38fF +C824 divider_2/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C825 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C826 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C827 divider_1/tspc_1/Z4 divider_1/tspc_1/Z1 0.00fF +C828 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C829 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C830 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C831 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C832 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF +C833 gnd pll_full_0/divider_0/nor_0/B 1.23fF +C834 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C835 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C836 divider_2/prescaler_0/tspc_0/Q divider_2/prescaler_0/nand_1/z1 0.01fF +C837 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/Out 0.05fF +C838 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF +C839 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C840 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C841 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C842 divider_1/prescaler_0/tspc_2/Z3 gnd 0.27fF +C843 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C844 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C845 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C846 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C847 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF +C848 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.45fF +C849 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF +C850 divider_2/tspc_1/Z1 divider_2/tspc_0/Q 0.01fF +C851 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF +C852 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C853 ro_complete_1/cbank_0/v ro_complete_1/cbank_2/v 0.04fF +C854 divider_2/nor_1/B gnd 1.10fF +C855 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C856 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Q 0.04fF +C857 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z1 0.15fF +C858 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C859 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C860 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C861 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C862 pd_1/REF pd_1/tspc_r_1/Z3 0.65fF +C863 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF +C864 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF +C865 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF +C866 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF +C867 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/tspc_2/D 0.04fF +C868 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C869 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C870 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF +C871 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C872 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF +C873 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF +C874 divider_1/prescaler_0/tspc_0/Z2 gnd 0.16fF +C875 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C876 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C877 divider_2/tspc_1/a_630_n680# gnd 0.62fF +C878 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C879 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C880 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/m1_2700_2190# 0.16fF +C881 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C882 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C883 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF +C884 pll_full_0/divider_0/prescaler_0/tspc_1/Q gnd 0.83fF +C885 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF +C886 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF +C887 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF +C888 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C889 divider_2/prescaler_0/tspc_1/Z4 divider_2/prescaler_0/Out 0.28fF +C890 divider_0/tspc_1/a_630_n680# gnd 0.62fF +C891 ro_complete_1/a4 ro_complete_1/cbank_2/switch_0/vin 0.12fF +C892 divider_1/prescaler_0/tspc_1/Z4 gnd 0.44fF +C893 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF +C894 divider_1/and_0/OUT divider_1/mc2 0.05fF +C895 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C896 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C897 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C898 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C899 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C900 divider_2/tspc_0/Z4 divider_2/tspc_0/Z3 0.65fF +C901 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_0/z1 0.24fF +C902 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C903 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C904 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C905 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C906 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF +C907 gnd pll_full_0/divider_0/tspc_0/Z3 0.27fF +C908 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C909 divider_2/nor_1/A divider_2/and_0/B 0.08fF +C910 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF +C911 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF +C912 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF +C913 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C914 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C915 divider_2/and_0/OUT divider_2/and_0/B 0.01fF +C916 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/Out 0.91fF +C917 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C918 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C919 ro_complete_1/a0 ro_complete_1/cbank_1/v 0.05fF +C920 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C921 divider_2/tspc_0/Z3 gnd 0.27fF +C922 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C923 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C924 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C925 pd_1/tspc_r_1/Qbar pd_1/UP 0.21fF +C926 pll_full_0/divider_0/nor_1/B gnd 1.17fF +C927 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C928 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Qbar1 0.20fF +C929 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.26fF +C930 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C931 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C932 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C933 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF +C934 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/Out 0.11fF +C935 divider_2/tspc_1/Z3 divider_2/tspc_1/a_630_n680# 0.05fF +C936 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF +C937 divbuf_1/OUT divbuf_1/OUT4 1.11fF +C938 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C939 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/switch_4/vin 0.20fF +C940 divider_0/prescaler_0/nand_1/z1 gnd 0.16fF +C941 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C942 ro_complete_1/cbank_2/switch_0/vin ro_complete_1/cbank_2/v 1.44fF +C943 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C944 divider_2/prescaler_0/tspc_1/Z2 gnd 0.17fF +C945 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C946 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C947 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C948 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C949 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C950 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C951 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C952 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF +C953 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF +C954 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF +C955 ro_complete_1/a2 ro_complete_1/cbank_1/switch_3/vin 0.09fF +C956 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF +C957 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF +C958 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF +C959 divider_2/nor_1/B divider_2/and_0/A 0.26fF +C960 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C961 divider_0/and_0/Z1 gnd 0.41fF +C962 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C963 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF +C964 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF +C965 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C966 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C967 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C968 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C969 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C970 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C971 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C972 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C973 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C974 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C975 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C976 gnd pll_full_0/divider_0/tspc_2/Z2 0.16fF +C977 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF +C978 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DIV 0.65fF +C979 divider_2/tspc_0/Z4 divider_2/prescaler_0/Out 0.12fF +C980 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF +C981 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C982 divider_1/prescaler_0/Out divider_1/clk 0.51fF +C983 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_1/z1 0.21fF +C984 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C985 ro_complete_1/a3 ro_complete_1/cbank_1/v 0.05fF +C986 divider_1/prescaler_0/tspc_2/Z4 gnd 0.44fF +C987 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C988 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF +C989 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C990 divider_2/prescaler_0/Out gnd 0.46fF +C991 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF +C992 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF +C993 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C994 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C995 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/DIV 0.02fF +C996 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF +C997 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/switch_4/vin 0.20fF +C998 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF +C999 divider_1/and_0/out1 gnd 0.23fF +C1000 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C1001 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C1002 divider_1/mc2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.33fF +C1003 divider_0/mc2 divider_0/and_0/out1 0.06fF +C1004 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C1005 divider_2/nor_1/A divider_2/tspc_0/Z1 0.03fF +C1006 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF +C1007 pll_full_0/divider_0/tspc_1/Z3 gnd 0.27fF +C1008 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF +C1009 divider_1/prescaler_0/tspc_0/Q divider_1/prescaler_0/nand_1/z1 0.01fF +C1010 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/Out 0.21fF +C1011 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/a1 0.14fF +C1012 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/a3 0.09fF +C1013 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF +C1014 divider_1/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C1015 ro_complete_1/cbank_2/switch_5/vin ro_complete_1/cbank_2/v 1.30fF +C1016 divider_1/tspc_0/Q gnd 0.33fF +C1017 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C1018 divider_2/prescaler_0/tspc_2/Z2 gnd 0.16fF +C1019 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C1020 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C1021 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C1022 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF +C1023 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF +C1024 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF +C1025 pll_full_0/divider_0/prescaler_0/tspc_0/Q gnd 0.35fF +C1026 io_clamp_low[2] io_clamp_high[2] 0.53fF +C1027 divbuf_3/IN divbuf_3/a_492_n240# 0.13fF +C1028 ro_complete_1/cbank_1/switch_1/vin ro_complete_1/cbank_1/v 1.30fF +C1029 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF +C1030 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C1031 io_clamp_high[1] io_analog[5] 0.53fF +C1032 divider_1/tspc_1/Z3 gnd 0.27fF +C1033 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C1034 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C1035 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C1036 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF +C1037 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF +C1038 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/Q 0.04fF +C1039 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C1040 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C1041 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C1042 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C1043 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C1044 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.45fF +C1045 gnd pll_full_0/divider_0/and_0/A 0.69fF +C1046 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF +C1047 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF +C1048 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C1049 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF +C1050 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF +C1051 divbuf_7/IN divbuf_7/OUT5 0.00fF +C1052 divider_1/tspc_2/a_630_n680# gnd 0.61fF +C1053 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C1054 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C1055 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF +C1056 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C1057 divider_2/tspc_0/Z4 divider_2/tspc_0/Z2 0.36fF +C1058 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C1059 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C1060 pll_full_0/divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF +C1061 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C1062 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF +C1063 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF +C1064 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF +C1065 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/switch_1/vin 0.19fF +C1066 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C1067 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C1068 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C1069 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C1070 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C1071 divider_2/and_0/out1 divider_2/and_0/B 0.18fF +C1072 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1073 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C1074 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1075 divider_2/tspc_0/Z2 gnd 0.16fF +C1076 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C1077 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C1078 divider_1/tspc_0/Q divider_1/tspc_1/a_630_n680# 0.01fF +C1079 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C1080 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C1081 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/Out 0.91fF +C1082 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_2/vin 0.20fF +C1083 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF +C1084 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/Out 0.08fF +C1085 divider_0/nor_1/Z1 gnd 0.01fF +C1086 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C1087 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C1088 divider_1/prescaler_0/m1_2700_2190# gnd 0.22fF +C1089 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1090 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C1091 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C1092 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF +C1093 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF +C1094 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C1095 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C1096 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C1097 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF +C1098 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF +C1099 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z3 0.05fF +C1100 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF +C1101 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Q 0.05fF +C1102 gnd pll_full_0/divbuf_0/IN 3.72fF +C1103 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C1104 ro_complete_1/a4 ro_complete_1/cbank_2/v 0.05fF +C1105 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/switch_0/vin 0.19fF +C1106 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C1107 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C1108 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF +C1109 divider_1/prescaler_0/nand_0/z1 gnd 0.16fF +C1110 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C1111 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C1112 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF +C1113 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C1114 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C1115 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.94fF +C1116 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF +C1117 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF +C1118 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1119 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C1120 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C1121 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C1122 divider_1/clk gnd 0.07fF +C1123 pd_0/DIV pd_0/R 0.51fF +C1124 pd_1/R pd_1/and_pd_0/Out1 0.33fF +C1125 pd_1/REF pd_1/tspc_r_1/Z4 0.02fF +C1126 pd_1/tspc_r_1/Qbar1 pd_1/UP 0.11fF +C1127 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C1128 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C1129 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C1130 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Q 0.04fF +C1131 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C1132 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C1133 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_1/z1 0.21fF +C1134 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/Out 0.04fF +C1135 divider_0/mc2 gnd 1.36fF +C1136 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C1137 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/a1 0.14fF +C1138 divider_0/prescaler_0/Out gnd 0.46fF +C1139 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C1140 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/Z3 0.16fF +C1141 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C1142 divider_2/tspc_0/Q gnd 0.33fF +C1143 divider_1/tspc_1/Z4 divider_1/tspc_1/Z2 0.36fF +C1144 divider_1/and_0/OUT divider_1/prescaler_0/tspc_1/Z2 0.06fF +C1145 pd_1/DIV pd_1/tspc_r_0/Qbar1 0.12fF +C1146 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C1147 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C1148 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C1149 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF +C1150 pll_full_0/divider_0/prescaler_0/tspc_2/D gnd 0.05fF +C1151 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF +C1152 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C1153 divider_1/tspc_0/Q divider_1/nor_1/B 0.22fF +C1154 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C1155 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/Out 0.21fF +C1156 ro_complete_1/a5 ro_complete_1/cbank_2/switch_0/vin 0.09fF +C1157 io_clamp_low[0] io_analog[4] 0.53fF +C1158 divider_1/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C1159 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C1160 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C1161 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF +C1162 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C1163 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C1164 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C1165 pd_1/DOWN pd_1/tspc_r_0/Z3 0.03fF +C1166 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF +C1167 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C1168 divider_1/tspc_1/Z2 divider_1/tspc_1/Z1 1.07fF +C1169 divider_1/tspc_1/Z3 divider_1/nor_1/B 0.38fF +C1170 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C1171 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF +C1172 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF +C1173 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF +C1174 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF +C1175 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C1176 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C1177 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1178 divider_1/nor_0/B gnd 1.08fF +C1179 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C1180 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C1181 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C1182 divider_0/mc2 divider_0/nor_0/B 0.15fF +C1183 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1184 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C1185 divider_1/tspc_0/Z4 divider_1/tspc_0/Z1 0.00fF +C1186 pd_1/R pd_1/tspc_r_1/Z3 0.29fF +C1187 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF +C1188 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C1189 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C1190 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1191 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C1192 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF +C1193 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C1194 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z3 0.25fF +C1195 divider_2/tspc_1/Z3 divider_2/tspc_0/Q 0.45fF +C1196 divider_2/nor_1/Z1 gnd 0.01fF +C1197 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C1198 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C1199 divider_2/tspc_1/Z2 gnd 0.16fF +C1200 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF +C1201 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1202 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C1203 pd_0/DOWN pd_0/UP 0.46fF +C1204 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C1205 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C1206 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_0/a_630_n680# 0.19fF +C1207 pd_1/UP pd_1/and_pd_0/Z1 0.06fF +C1208 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C1209 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C1210 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C1211 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF +C1212 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF +C1213 ro_complete_1/cbank_0/switch_4/vin ro_complete_1/a0 0.13fF +C1214 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF +C1215 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF +C1216 divider_2/and_0/OUT divider_2/prescaler_0/tspc_0/D 0.03fF +C1217 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF +C1218 divider_2/prescaler_0/tspc_0/Z3 gnd 0.27fF +C1219 divider_1/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C1220 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C1221 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C1222 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C1223 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Z2 0.06fF +C1224 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C1225 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF +C1226 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C1227 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/Out 0.11fF +C1228 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF +C1229 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C1230 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C1231 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C1232 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/cbank_0/switch_2/vin 0.20fF +C1233 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C1234 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.01fF +C1235 divider_1/and_0/out1 divider_1/and_0/B 0.18fF +C1236 ro_complete_1/a1 ro_complete_1/cbank_1/v 0.05fF +C1237 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C1238 pll_full_0/cp_0/down pll_full_0/cp_0/upbar 0.02fF +C1239 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF +C1240 divider_1/mc2 gnd 1.36fF +C1241 divider_1/prescaler_0/tspc_1/Q gnd 0.83fF +C1242 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF +C1243 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C1244 divider_1/mc2 divider_1/nor_1/A 0.04fF +C1245 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C1246 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C1247 pd_1/DOWN pd_1/UP 0.46fF +C1248 pd_1/tspc_r_0/Z3 pd_1/R 0.27fF +C1249 pll_full_0/divider_0/tspc_1/a_630_n680# gnd 0.62fF +C1250 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF +C1251 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF +C1252 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF +C1253 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF +C1254 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF +C1255 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C1256 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C1257 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C1258 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF +C1259 divider_2/nor_0/B divider_2/and_0/B 0.29fF +C1260 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C1261 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C1262 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C1263 pd_1/DIV pd_1/tspc_r_0/Z1 0.17fF +C1264 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C1265 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C1266 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C1267 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C1268 divider_1/tspc_0/Z4 divider_1/tspc_0/Z3 0.65fF +C1269 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF +C1270 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF +C1271 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C1272 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C1273 ro_complete_1/a4 ro_complete_1/cbank_2/switch_1/vin 0.09fF +C1274 ro_complete_1/cbank_0/switch_3/vin ro_complete_1/cbank_0/v 1.30fF +C1275 divider_2/prescaler_0/tspc_0/Z4 gnd 0.44fF +C1276 divider_2/mc2 divider_2/and_0/B 0.20fF +C1277 divider_0/tspc_0/Z2 gnd 0.16fF +C1278 divider_2/tspc_1/Z4 gnd 0.44fF +C1279 divider_0/mc2 divider_0/nor_1/B 0.06fF +C1280 pd_1/DIV pd_1/R 0.51fF +C1281 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C1282 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF +C1283 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C1284 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Q 0.05fF +C1285 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF +C1286 gnd pll_full_0/divider_0/prescaler_0/nand_1/z1 0.16fF +C1287 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C1288 io_clamp_low[1] io_clamp_high[1] 0.53fF +C1289 divider_2/tspc_0/Z3 divider_2/tspc_0/a_630_n680# 0.05fF +C1290 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF +C1291 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C1292 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C1293 ro_complete_1/a3 ro_complete_1/cbank_2/switch_2/vin 0.09fF +C1294 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/Out 0.04fF +C1295 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C1296 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C1297 divider_1/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C1298 divider_2/tspc_2/Z3 gnd 0.27fF +C1299 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z4 0.08fF +C1300 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C1301 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF +C1302 gnd pll_full_0/divider_0/and_0/Z1 0.32fF +C1303 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF +C1304 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.35fF +C1305 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C1306 ro_complete_1/cbank_0/switch_1/vin ro_complete_1/a3 0.13fF +C1307 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C1308 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C1309 ro_complete_1/cbank_2/switch_1/vin ro_complete_1/cbank_2/v 1.30fF +C1310 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF +C1311 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF +C1312 divider_0/nor_1/A gnd 1.02fF +C1313 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C1314 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF +C1315 divider_1/tspc_2/Z2 gnd 0.16fF +C1316 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF +C1317 pd_1/R pd_1/UP 0.45fF +C1318 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF +C1319 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C1320 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C1321 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF +C1322 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF +C1323 divider_1/nor_1/B divider_1/nor_0/B 0.47fF +C1324 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/Out 0.19fF +C1325 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF +C1326 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF +C1327 ro_complete_1/cbank_1/switch_3/vin ro_complete_1/cbank_1/v 1.30fF +C1328 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C1329 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C1330 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C1331 divider_2/tspc_1/Q gnd 0.33fF +C1332 pd_0/R pd_0/REF 0.61fF +C1333 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C1334 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF +C1335 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C1336 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C1337 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C1338 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF +C1339 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF +C1340 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF +C1341 divbuf_2/IN divbuf_2/a_492_n240# 0.13fF +C1342 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C1343 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF +C1344 divider_2/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.01fF +C1345 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF +C1346 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF +C1347 divider_0/tspc_0/Z4 gnd 0.44fF +C1348 ro_complete_1/cbank_2/switch_3/vin ro_complete_1/cbank_2/switch_4/vin 0.20fF +C1349 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C1350 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C1351 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C1352 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C1353 divider_1/tspc_0/Z4 divider_1/tspc_0/Z2 0.36fF +C1354 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF +C1355 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C1356 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C1357 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF +C1358 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF +C1359 ro_complete_1/cbank_0/switch_0/vin ro_complete_1/cbank_0/v 1.30fF +C1360 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C1361 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C1362 divider_2/and_0/OUT divider_2/clk 0.04fF +C1363 divider_0/tspc_1/Z2 gnd 0.16fF +C1364 ro_complete_1/a5 ro_complete_1/cbank_2/v 0.08fF +C1365 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C1366 divider_1/prescaler_0/tspc_0/Q gnd 0.35fF +C1367 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF +C1368 divider_2/and_0/B gnd 0.45fF +C1369 pd_1/tspc_r_1/Z1 pd_1/REF 0.17fF +C1370 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Z4 0.20fF +C1371 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF +C1372 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C1373 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF +C1374 divider_1/mc2 divider_1/nor_1/B 0.06fF +C1375 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C1376 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C1377 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF +C1378 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF +C1379 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF +C1380 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF +C1381 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C1382 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C1383 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C1384 divider_1/and_0/A gnd 0.53fF +C1385 divider_0/mc2 divider_0/and_0/A 0.16fF +C1386 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C1387 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1388 pd_1/UP pd_1/tspc_r_1/z5 0.03fF +C1389 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C1390 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C1391 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C1392 divider_1/tspc_0/Z2 divider_1/tspc_0/Z1 1.07fF +C1393 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C1394 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C1395 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C1396 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C1397 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C1398 divider_1/nor_1/A divider_1/and_0/A 0.01fF +C1399 ro_complete_1/a2 ro_complete_1/cbank_2/v 0.05fF +C1400 divider_1/tspc_1/Z4 gnd 0.44fF +C1401 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C1402 divider_1/tspc_1/Z4 divider_1/nor_1/A 0.02fF +C1403 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF +C1404 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C1405 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C1406 pd_1/DIV pd_1/tspc_r_0/Z4 0.02fF +C1407 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C1408 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C1409 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C1410 divider_1/tspc_0/Z4 divider_1/prescaler_0/Out 0.12fF +C1411 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF +C1412 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF +C1413 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C1414 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C1415 divider_2/mc2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.33fF +C1416 divider_1/nor_0/B divider_1/and_0/B 0.29fF +C1417 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C1418 ro_complete_1/cbank_0/switch_5/vin ro_complete_1/a0 0.09fF +C1419 divbuf_6/IN divbuf_6/OUT5 0.00fF +C1420 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF +C1421 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF +C1422 divider_2/tspc_2/Z4 gnd 0.44fF +C1423 divider_2/nor_1/A divider_2/mc2 0.04fF +C1424 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF +C1425 pll_full_0/divider_0/tspc_0/Q gnd 0.33fF +C1426 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C1427 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF +C1428 divider_2/mc2 divider_2/and_0/OUT 0.05fF +C1429 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z2 0.01fF +C1430 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.15fF +C1431 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C1432 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C1433 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF +C1434 divider_2/tspc_2/Z3 divider_2/Out 0.05fF +C1435 divider_0/tspc_1/Z4 gnd 0.44fF +C1436 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF +C1437 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C1438 divider_1/Out gnd 0.29fF +C1439 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C1440 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1441 divider_0/nor_1/B divider_0/nor_1/A 1.21fF +C1442 divider_2/tspc_0/Z4 divider_2/tspc_0/Z1 0.00fF +C1443 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/a_630_n680# 0.01fF +C1444 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF +C1445 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF +C1446 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF +C1447 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C1448 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF +C1449 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF +C1450 divider_2/tspc_0/Z3 divider_2/prescaler_0/Out 0.45fF +C1451 divider_2/and_0/A divider_2/and_0/B 0.18fF +C1452 divider_0/tspc_2/Z3 gnd 0.27fF +C1453 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C1454 divider_1/and_0/OUT divider_1/prescaler_0/tspc_0/D 0.03fF +C1455 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF +C1456 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF +C1457 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C1458 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C1459 divider_1/tspc_1/Z4 divider_1/tspc_1/a_630_n680# 0.12fF +C1460 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF +C1461 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C1462 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C1463 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C1464 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF +C1465 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.05fF +C1466 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF +C1467 divider_1/mc2 divider_1/and_0/B 0.20fF +C1468 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF +C1469 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF +C1470 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C1471 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF +C1472 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF +C1473 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF +C1474 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C1475 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C1476 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z1 0.71fF +C1477 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_0/z1 0.24fF +C1478 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/Out 0.19fF +C1479 divider_1/nor_0/Z1 gnd 0.01fF +C1480 divider_1/prescaler_0/tspc_1/Z2 gnd 0.17fF +C1481 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C1482 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C1483 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF +C1484 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF +C1485 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/prescaler_0/tspc_0/Z3 0.05fF +C1486 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C1487 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C1488 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C1489 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C1490 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C1491 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z2 0.14fF +C1492 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF +C1493 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C1494 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF +C1495 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF +C1496 gnd pll_full_0/divider_0/prescaler_0/Out 0.46fF +C1497 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C1498 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C1499 ro_complete_1/a0 ro_complete_1/cbank_2/switch_4/vin 0.13fF +C1500 ro_complete_1/cbank_0/v ro_complete_1/cbank_1/v 1.27fF +C1501 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C1502 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.26fF +C1503 divider_0/tspc_1/Q gnd 0.33fF +C1504 divider_1/prescaler_0/tspc_2/D gnd 0.05fF +C1505 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C1506 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF +C1507 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C1508 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C1509 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF +C1510 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/z5 0.20fF +C1511 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF +C1512 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF +C1513 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C1514 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C1515 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C1516 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C1517 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C1518 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C1519 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C1520 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.01fF +C1521 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF +C1522 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C1523 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Q 0.04fF +C1524 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C1525 divider_2/tspc_0/Z4 divider_2/nor_1/A 0.21fF +C1526 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF +C1527 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C1528 divider_2/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C1529 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C1530 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C1531 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/tspc_0/Z3 0.05fF +C1532 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF +C1533 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF +C1534 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF +C1535 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C1536 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C1537 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF +C1538 divider_1/tspc_0/Z3 divider_1/prescaler_0/Out 0.45fF +C1539 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.64fF +C1540 divider_1/nor_1/B divider_1/and_0/A 0.26fF +C1541 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C1542 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C1543 divider_2/nor_1/A gnd 1.02fF +C1544 ro_complete_1/cbank_0/switch_2/vin ro_complete_1/cbank_0/v 1.30fF +C1545 divider_0/and_0/B gnd 0.45fF +C1546 divider_2/and_0/OUT gnd 0.28fF +C1547 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C1548 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C1549 divider_1/tspc_1/Z4 divider_1/nor_1/B 0.21fF +C1550 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF +C1551 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C1552 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C1553 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C1554 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF +C1555 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF +C1556 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF +C1557 io_clamp_low[0] io_clamp_high[0] 0.53fF +C1558 divider_2/tspc_0/Z3 divider_2/tspc_0/Z2 0.16fF +C1559 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C1560 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C1561 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C1562 divider_1/prescaler_0/tspc_2/Z2 gnd 0.16fF +C1563 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C1564 pd_1/DOWN pd_1/tspc_r_0/z5 0.03fF +C1565 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C1566 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C1567 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C1568 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C1569 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C1570 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C1571 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF +C1572 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF +C1573 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF +C1574 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF +C1575 divider_2/nor_1/B divider_2/tspc_0/Q 0.22fF +C1576 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C1577 divider_1/tspc_0/Z4 gnd 0.44fF +C1578 pll_full_0/pd_0/DIV gnd 0.01fF +C1579 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF +C1580 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C1581 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C1582 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C1583 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C1584 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C1585 cp_0/a_1710_0# cp_0/out 0.84fF +C1586 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF +C1587 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C1588 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C1589 divider_1/tspc_0/Z4 divider_1/nor_1/A 0.21fF +C1590 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C1591 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C1592 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF +C1593 divider_2/mc2 divider_2/and_0/out1 0.06fF +C1594 divider_2/tspc_1/a_630_n680# divider_2/tspc_0/Q 0.01fF +C1595 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF +C1596 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Q 0.04fF +C1597 divider_0/tspc_2/Z4 gnd 0.44fF +Xpd_0 VDD vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd +Xpd_1 VDD vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R pd +Xcp_0 cp_0/vbias vdd vssa1 cp_0/out cp_0/down cp_0/upbar cp +Xfilter_0 vssa1 filter_0/v filter Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 + ro_complete_0/a3 ro_complete_0/a2 ro_complete -Xdivbuf_0 VDD divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 divbuf_0/OUT5 -+ gnd divbuf +Xdivbuf_0 vdda1 divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 ++ divbuf_0/OUT5 vssa1 divbuf Xro_complete_1 ro_complete_1/a0 ro_complete_1/a1 ro_complete_1/a5 ro_complete_1/a4 + ro_complete_1/a3 ro_complete_1/a2 ro_complete -Xdivbuf_1 VDD divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 divbuf_1/OUT5 -+ gnd divbuf -Xdivbuf_2 VDD divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 divbuf_2/OUT5 -+ gnd divbuf -Xdivbuf_3 VDD divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 divbuf_3/OUT5 -+ gnd divbuf -Xdivbuf_4 VDD divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 divbuf_4/OUT5 -+ gnd divbuf -Xdivbuf_5 VDD divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 divbuf_5/OUT5 -+ gnd divbuf -Xdivbuf_6 VDD divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 divbuf_6/OUT5 -+ gnd divbuf -Xdivbuf_7 VDD divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 divbuf_7/OUT5 -+ gnd divbuf +Xdivbuf_1 vdda1 divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 ++ divbuf_1/OUT5 vssa1 divbuf +Xdivbuf_2 vdda1 divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 ++ divbuf_2/OUT5 vssa1 divbuf +Xdivbuf_3 vdda1 divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 ++ divbuf_3/OUT5 vssa1 divbuf +Xdivbuf_4 vdda1 divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 ++ divbuf_4/OUT5 vssa1 divbuf +Xdivbuf_5 vdda1 divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 ++ divbuf_5/OUT5 vssa1 divbuf +Xdivbuf_6 vdda1 divbuf_6/IN divbuf_6/OUT divbuf_6/OUT2 divbuf_6/OUT3 divbuf_6/OUT4 ++ divbuf_6/OUT5 vssa1 divbuf +Xdivbuf_7 vdda1 divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 ++ divbuf_7/OUT5 vssa1 divbuf Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider Xdivider_1 gnd vdd divider_1/Out divider_1/clk divider_1/mc2 divider Xdivider_2 gnd vdd divider_2/Out divider_2/clk divider_2/mc2 divider Xpll_full_0 vdd pll_full -C1404 io_analog[4] vdd 43.96fF -C1405 io_analog[5] vdd 44.13fF -C1406 io_analog[6] vdd 43.46fF -C1407 io_in_3v3[0] vdd 0.61fF -C1408 io_oeb[26] vdd 0.61fF -C1409 io_in[0] vdd 0.61fF -C1410 io_out[26] vdd 0.61fF -C1411 io_out[0] vdd 0.61fF -C1412 io_in[26] vdd 0.61fF -C1413 io_oeb[0] vdd 0.61fF -C1414 io_in_3v3[26] vdd 0.61fF -C1415 io_in_3v3[1] vdd 0.61fF -C1416 io_oeb[25] vdd 0.61fF -C1417 io_in[1] vdd 0.61fF -C1418 io_out[25] vdd 0.61fF -C1419 io_out[1] vdd 0.61fF -C1420 io_in[25] vdd 0.61fF -C1421 io_oeb[1] vdd 0.61fF -C1422 io_in_3v3[25] vdd 0.61fF -C1423 io_in_3v3[2] vdd 0.61fF -C1424 io_oeb[24] vdd 0.61fF -C1425 io_in[2] vdd 0.61fF -C1426 io_out[24] vdd 0.61fF -C1427 io_out[2] vdd 0.61fF -C1428 io_in[24] vdd 0.61fF -C1429 io_oeb[2] vdd 0.61fF -C1430 io_in_3v3[24] vdd 0.61fF -C1431 io_in_3v3[3] vdd 0.61fF -C1432 gpio_noesd[17] vdd 2.32fF -C1433 io_in[3] vdd 0.61fF -C1434 gpio_analog[17] vdd 2.30fF -C1435 io_out[3] vdd 0.61fF -C1436 io_oeb[3] vdd 0.61fF -C1437 io_in_3v3[4] vdd 0.61fF -C1438 io_in[4] vdd 0.61fF -C1439 io_out[4] vdd 0.61fF -C1440 io_oeb[4] vdd 0.61fF -C1441 io_oeb[23] vdd 0.61fF -C1442 io_out[23] vdd 0.61fF -C1443 io_in[23] vdd 0.61fF -C1444 io_in_3v3[23] vdd 0.61fF -C1445 gpio_noesd[16] vdd 2.30fF -C1446 gpio_analog[16] vdd 2.30fF -C1447 io_in_3v3[5] vdd 0.61fF -C1448 io_in[5] vdd 0.61fF -C1449 io_out[5] vdd 0.61fF -C1450 io_oeb[5] vdd 0.61fF -C1451 io_oeb[22] vdd 0.61fF -C1452 io_out[22] vdd 0.61fF -C1453 io_in[22] vdd 0.61fF -C1454 io_in_3v3[22] vdd 0.61fF -C1455 gpio_noesd[15] vdd 2.31fF -C1456 gpio_analog[15] vdd 2.30fF -C1457 io_in_3v3[6] vdd 0.61fF -C1458 io_in[6] vdd 0.61fF -C1459 io_out[6] vdd 0.61fF -C1460 io_oeb[6] vdd 0.61fF -C1461 io_oeb[21] vdd 0.61fF -C1462 io_out[21] vdd 0.61fF -C1463 io_in[21] vdd 0.61fF -C1464 io_in_3v3[21] vdd 0.61fF -C1465 gpio_noesd[14] vdd 2.30fF -C1466 gpio_analog[14] vdd 2.29fF -C1467 vssa1 vdd 5997.40fF -C1468 vssd2 vdd 38.54fF -C1469 vssd1 vdd 13.04fF -C1470 vdda2 vdd 38.30fF -C1471 vdda1 vdd 4568.78fF -C1472 io_oeb[20] vdd 0.61fF -C1473 io_out[20] vdd 0.61fF -C1474 io_in[20] vdd 0.61fF -C1475 io_in_3v3[20] vdd 0.61fF -C1476 gpio_noesd[13] vdd 2.31fF -C1477 gpio_analog[13] vdd 2.30fF -C1478 gpio_analog[0] vdd 0.61fF -C1479 gpio_noesd[0] vdd 0.61fF -C1480 io_in_3v3[7] vdd 0.61fF -C1481 io_in[7] vdd 0.61fF -C1482 io_out[7] vdd 0.61fF -C1483 io_oeb[7] vdd 0.61fF -C1484 io_oeb[19] vdd 0.61fF -C1485 io_out[19] vdd 0.61fF -C1486 io_in[19] vdd 0.61fF -C1487 io_in_3v3[19] vdd 0.61fF -C1488 gpio_noesd[12] vdd 2.32fF -C1489 gpio_analog[12] vdd 2.30fF -C1490 gpio_analog[1] vdd 0.61fF -C1491 gpio_noesd[1] vdd 0.61fF -C1492 io_in_3v3[8] vdd 0.61fF -C1493 io_in[8] vdd 0.61fF -C1494 io_out[8] vdd 0.61fF -C1495 io_oeb[8] vdd 0.61fF -C1496 io_oeb[18] vdd 0.61fF -C1497 io_out[18] vdd 0.61fF -C1498 io_in[18] vdd 0.61fF -C1499 io_in_3v3[18] vdd 0.61fF -C1500 gpio_noesd[11] vdd 2.30fF -C1501 gpio_analog[11] vdd 2.29fF -C1502 gpio_analog[2] vdd 0.61fF -C1503 gpio_noesd[2] vdd 0.61fF -C1504 io_in_3v3[9] vdd 0.61fF -C1505 io_in[9] vdd 0.61fF -C1506 io_out[9] vdd 0.61fF -C1507 io_oeb[9] vdd 0.61fF -C1508 io_oeb[17] vdd 0.61fF -C1509 io_out[17] vdd 0.61fF -C1510 io_in[17] vdd 0.61fF -C1511 io_in_3v3[17] vdd 0.61fF -C1512 gpio_noesd[10] vdd 2.31fF -C1513 gpio_analog[10] vdd 2.29fF -C1514 gpio_analog[3] vdd 0.61fF -C1515 gpio_noesd[3] vdd 0.61fF -C1516 io_in_3v3[10] vdd 0.61fF -C1517 io_in[10] vdd 0.61fF -C1518 io_out[10] vdd 0.61fF -C1519 io_oeb[10] vdd 0.61fF -C1520 io_oeb[16] vdd 0.61fF -C1521 io_out[16] vdd 0.61fF -C1522 io_in[16] vdd 0.61fF -C1523 io_in_3v3[16] vdd 0.61fF -C1524 gpio_noesd[9] vdd 2.28fF -C1525 gpio_analog[9] vdd 2.28fF -C1526 gpio_analog[4] vdd 0.61fF -C1527 gpio_noesd[4] vdd 0.61fF -C1528 io_in_3v3[11] vdd 0.61fF -C1529 io_in[11] vdd 0.61fF -C1530 io_out[11] vdd 0.61fF -C1531 io_oeb[11] vdd 0.61fF -C1532 io_oeb[15] vdd 0.61fF -C1533 io_out[15] vdd 0.61fF -C1534 io_in[15] vdd 0.61fF -C1535 io_in_3v3[15] vdd 0.61fF -C1536 gpio_noesd[8] vdd 2.28fF -C1537 gpio_analog[8] vdd 2.26fF -C1538 gpio_analog[5] vdd 0.61fF -C1539 gpio_noesd[5] vdd 0.61fF -C1540 io_in_3v3[12] vdd 0.61fF -C1541 io_in[12] vdd 0.61fF -C1542 io_out[12] vdd 0.61fF -C1543 io_oeb[12] vdd 0.61fF -C1544 io_oeb[14] vdd 0.61fF -C1545 io_out[14] vdd 0.61fF -C1546 io_in[14] vdd 0.61fF -C1547 io_in_3v3[14] vdd 0.61fF -C1548 gpio_noesd[7] vdd 2.30fF -C1549 gpio_analog[7] vdd 2.28fF -C1550 vssa2 vdd 38.35fF -C1551 gpio_analog[6] vdd 5.71fF -C1552 gpio_noesd[6] vdd 5.70fF -C1553 io_in_3v3[13] vdd 0.61fF -C1554 io_in[13] vdd 0.61fF -C1555 io_out[13] vdd 0.61fF -C1556 io_oeb[13] vdd 0.61fF -C1557 vccd1 vdd 39.84fF -C1558 vccd2 vdd 38.46fF -C1559 io_analog[0] vdd 19.99fF -C1560 io_analog[10] vdd 19.36fF -C1561 io_analog[1] vdd 13.17fF -C1562 io_analog[2] vdd 12.57fF -C1563 io_analog[3] vdd 12.83fF -C1564 io_clamp_high[0] vdd 3.58fF -C1565 io_clamp_low[0] vdd 3.58fF -C1566 io_clamp_high[1] vdd 3.58fF -C1567 io_clamp_low[1] vdd 3.58fF -C1568 io_clamp_high[2] vdd 3.58fF -C1569 io_clamp_low[2] vdd 3.58fF -C1570 io_analog[7] vdd 12.74fF -C1571 io_analog[8] vdd 13.08fF -C1572 io_analog[9] vdd 13.08fF -C1573 user_irq[2] vdd 0.63fF -C1574 user_irq[1] vdd 0.63fF -C1575 user_irq[0] vdd 0.63fF -C1576 user_clock2 vdd 0.63fF -C1577 la_oenb[127] vdd 0.63fF -C1578 la_data_out[127] vdd 0.63fF -C1579 la_data_in[127] vdd 0.63fF -C1580 la_oenb[126] vdd 0.63fF -C1581 la_data_out[126] vdd 0.63fF -C1582 la_data_in[126] vdd 0.63fF -C1583 la_oenb[125] vdd 0.63fF -C1584 la_data_out[125] vdd 0.63fF -C1585 la_data_in[125] vdd 0.63fF -C1586 la_oenb[124] vdd 0.63fF -C1587 la_data_out[124] vdd 0.63fF -C1588 la_data_in[124] vdd 0.63fF -C1589 la_oenb[123] vdd 0.63fF -C1590 la_data_out[123] vdd 0.63fF -C1591 la_data_in[123] vdd 0.63fF -C1592 la_oenb[122] vdd 0.63fF -C1593 la_data_out[122] vdd 0.63fF -C1594 la_data_in[122] vdd 0.63fF -C1595 la_oenb[121] vdd 0.63fF -C1596 la_data_out[121] vdd 0.63fF -C1597 la_data_in[121] vdd 0.63fF -C1598 la_oenb[120] vdd 0.63fF -C1599 la_data_out[120] vdd 0.63fF -C1600 la_data_in[120] vdd 0.63fF -C1601 la_oenb[119] vdd 0.63fF -C1602 la_data_out[119] vdd 0.63fF -C1603 la_data_in[119] vdd 0.63fF -C1604 la_oenb[118] vdd 0.63fF -C1605 la_data_out[118] vdd 0.63fF -C1606 la_data_in[118] vdd 0.63fF -C1607 la_oenb[117] vdd 0.63fF -C1608 la_data_out[117] vdd 0.63fF -C1609 la_data_in[117] vdd 0.63fF -C1610 la_oenb[116] vdd 0.63fF -C1611 la_data_out[116] vdd 0.63fF -C1612 la_data_in[116] vdd 0.63fF -C1613 la_oenb[115] vdd 0.63fF -C1614 la_data_out[115] vdd 0.63fF -C1615 la_data_in[115] vdd 0.63fF -C1616 la_oenb[114] vdd 0.63fF -C1617 la_data_out[114] vdd 0.63fF -C1618 la_data_in[114] vdd 0.63fF -C1619 la_oenb[113] vdd 0.63fF -C1620 la_data_out[113] vdd 0.63fF -C1621 la_data_in[113] vdd 0.63fF -C1622 la_oenb[112] vdd 0.63fF -C1623 la_data_out[112] vdd 0.63fF -C1624 la_data_in[112] vdd 0.63fF -C1625 la_oenb[111] vdd 0.63fF -C1626 la_data_out[111] vdd 0.63fF -C1627 la_data_in[111] vdd 0.63fF -C1628 la_oenb[110] vdd 0.63fF -C1629 la_data_out[110] vdd 0.63fF -C1630 la_data_in[110] vdd 0.63fF -C1631 la_oenb[109] vdd 0.63fF -C1632 la_data_out[109] vdd 0.63fF -C1633 la_data_in[109] vdd 0.63fF -C1634 la_oenb[108] vdd 0.63fF -C1635 la_data_out[108] vdd 0.63fF -C1636 la_data_in[108] vdd 0.63fF -C1637 la_oenb[107] vdd 0.63fF -C1638 la_data_out[107] vdd 0.63fF -C1639 la_data_in[107] vdd 0.63fF -C1640 la_oenb[106] vdd 0.63fF -C1641 la_data_out[106] vdd 0.63fF -C1642 la_data_in[106] vdd 0.63fF -C1643 la_oenb[105] vdd 0.63fF -C1644 la_data_out[105] vdd 0.63fF -C1645 la_data_in[105] vdd 0.63fF -C1646 la_oenb[104] vdd 0.63fF -C1647 la_data_out[104] vdd 0.63fF -C1648 la_data_in[104] vdd 0.63fF -C1649 la_oenb[103] vdd 0.63fF -C1650 la_data_out[103] vdd 0.63fF -C1651 la_data_in[103] vdd 0.63fF -C1652 la_oenb[102] vdd 0.63fF -C1653 la_data_out[102] vdd 0.63fF -C1654 la_data_in[102] vdd 0.63fF -C1655 la_oenb[101] vdd 0.63fF -C1656 la_data_out[101] vdd 0.63fF -C1657 la_data_in[101] vdd 0.63fF -C1658 la_oenb[100] vdd 0.63fF -C1659 la_data_out[100] vdd 0.63fF -C1660 la_data_in[100] vdd 0.63fF -C1661 la_oenb[99] vdd 0.63fF -C1662 la_data_out[99] vdd 0.63fF -C1663 la_data_in[99] vdd 0.63fF -C1664 la_oenb[98] vdd 0.63fF -C1665 la_data_out[98] vdd 0.63fF -C1666 la_data_in[98] vdd 0.63fF -C1667 la_oenb[97] vdd 0.63fF -C1668 la_data_out[97] vdd 0.63fF -C1669 la_data_in[97] vdd 0.63fF -C1670 la_oenb[96] vdd 0.63fF -C1671 la_data_out[96] vdd 0.63fF -C1672 la_data_in[96] vdd 0.63fF -C1673 la_oenb[95] vdd 0.63fF -C1674 la_data_out[95] vdd 0.63fF -C1675 la_data_in[95] vdd 0.63fF -C1676 la_oenb[94] vdd 0.63fF -C1677 la_data_out[94] vdd 0.63fF -C1678 la_data_in[94] vdd 0.63fF -C1679 la_oenb[93] vdd 0.63fF -C1680 la_data_out[93] vdd 0.63fF -C1681 la_data_in[93] vdd 0.63fF -C1682 la_oenb[92] vdd 0.63fF -C1683 la_data_out[92] vdd 0.63fF -C1684 la_data_in[92] vdd 0.63fF -C1685 la_oenb[91] vdd 0.63fF -C1686 la_data_out[91] vdd 0.63fF -C1687 la_data_in[91] vdd 0.63fF -C1688 la_oenb[90] vdd 0.63fF -C1689 la_data_out[90] vdd 0.63fF -C1690 la_data_in[90] vdd 0.63fF -C1691 la_oenb[89] vdd 0.63fF -C1692 la_data_out[89] vdd 0.63fF -C1693 la_data_in[89] vdd 0.63fF -C1694 la_oenb[88] vdd 0.63fF -C1695 la_data_out[88] vdd 0.63fF -C1696 la_data_in[88] vdd 0.63fF -C1697 la_oenb[87] vdd 0.63fF -C1698 la_data_out[87] vdd 0.63fF -C1699 la_data_in[87] vdd 0.63fF -C1700 la_oenb[86] vdd 0.63fF -C1701 la_data_out[86] vdd 0.63fF -C1702 la_data_in[86] vdd 0.63fF -C1703 la_oenb[85] vdd 0.63fF -C1704 la_data_out[85] vdd 0.63fF -C1705 la_data_in[85] vdd 0.63fF -C1706 la_oenb[84] vdd 0.63fF -C1707 la_data_out[84] vdd 0.63fF -C1708 la_data_in[84] vdd 0.63fF -C1709 la_oenb[83] vdd 0.63fF -C1710 la_data_out[83] vdd 0.63fF -C1711 la_data_in[83] vdd 0.63fF -C1712 la_oenb[82] vdd 0.63fF -C1713 la_data_out[82] vdd 0.63fF -C1714 la_data_in[82] vdd 0.63fF -C1715 la_oenb[81] vdd 0.63fF -C1716 la_data_out[81] vdd 0.63fF -C1717 la_data_in[81] vdd 0.63fF -C1718 la_oenb[80] vdd 0.63fF -C1719 la_data_out[80] vdd 0.63fF -C1720 la_data_in[80] vdd 0.63fF -C1721 la_oenb[79] vdd 0.63fF -C1722 la_data_out[79] vdd 0.63fF -C1723 la_data_in[79] vdd 0.63fF -C1724 la_oenb[78] vdd 0.63fF -C1725 la_data_out[78] vdd 0.63fF -C1726 la_data_in[78] vdd 0.63fF -C1727 la_oenb[77] vdd 0.63fF -C1728 la_data_out[77] vdd 0.63fF -C1729 la_data_in[77] vdd 0.63fF -C1730 la_oenb[76] vdd 0.63fF -C1731 la_data_out[76] vdd 0.63fF -C1732 la_data_in[76] vdd 0.63fF -C1733 la_oenb[75] vdd 0.63fF -C1734 la_data_out[75] vdd 0.63fF -C1735 la_data_in[75] vdd 0.63fF -C1736 la_oenb[74] vdd 0.63fF -C1737 la_data_out[74] vdd 0.63fF -C1738 la_data_in[74] vdd 0.63fF -C1739 la_oenb[73] vdd 0.63fF -C1740 la_data_out[73] vdd 0.63fF -C1741 la_data_in[73] vdd 0.63fF -C1742 la_oenb[72] vdd 0.63fF -C1743 la_data_out[72] vdd 0.63fF -C1744 la_data_in[72] vdd 0.63fF -C1745 la_oenb[71] vdd 0.63fF -C1746 la_data_out[71] vdd 0.63fF -C1747 la_data_in[71] vdd 0.63fF -C1748 la_oenb[70] vdd 0.63fF -C1749 la_data_out[70] vdd 0.63fF -C1750 la_data_in[70] vdd 0.63fF -C1751 la_oenb[69] vdd 0.63fF -C1752 la_data_out[69] vdd 0.63fF -C1753 la_data_in[69] vdd 0.63fF -C1754 la_oenb[68] vdd 0.63fF -C1755 la_data_out[68] vdd 0.63fF -C1756 la_data_in[68] vdd 0.63fF -C1757 la_oenb[67] vdd 0.63fF -C1758 la_data_out[67] vdd 0.63fF -C1759 la_data_in[67] vdd 0.63fF -C1760 la_oenb[66] vdd 0.63fF -C1761 la_data_out[66] vdd 0.63fF -C1762 la_data_in[66] vdd 0.63fF -C1763 la_oenb[65] vdd 0.63fF -C1764 la_data_out[65] vdd 0.63fF -C1765 la_data_in[65] vdd 0.63fF -C1766 la_oenb[64] vdd 0.63fF -C1767 la_data_out[64] vdd 0.63fF -C1768 la_data_in[64] vdd 0.63fF -C1769 la_oenb[63] vdd 0.63fF -C1770 la_data_out[63] vdd 0.63fF -C1771 la_data_in[63] vdd 0.63fF -C1772 la_oenb[62] vdd 0.63fF -C1773 la_data_out[62] vdd 0.63fF -C1774 la_data_in[62] vdd 0.63fF -C1775 la_oenb[61] vdd 0.63fF -C1776 la_data_out[61] vdd 0.63fF -C1777 la_data_in[61] vdd 0.63fF -C1778 la_oenb[60] vdd 0.63fF -C1779 la_data_out[60] vdd 0.63fF -C1780 la_data_in[60] vdd 0.63fF -C1781 la_oenb[59] vdd 0.63fF -C1782 la_data_out[59] vdd 0.63fF -C1783 la_data_in[59] vdd 0.63fF -C1784 la_oenb[58] vdd 0.63fF -C1785 la_data_out[58] vdd 0.63fF -C1786 la_data_in[58] vdd 0.63fF -C1787 la_oenb[57] vdd 0.63fF -C1788 la_data_out[57] vdd 0.63fF -C1789 la_data_in[57] vdd 0.63fF -C1790 la_oenb[56] vdd 0.63fF -C1791 la_data_out[56] vdd 0.63fF -C1792 la_data_in[56] vdd 0.63fF -C1793 la_oenb[55] vdd 0.63fF -C1794 la_data_out[55] vdd 0.63fF -C1795 la_data_in[55] vdd 0.63fF -C1796 la_oenb[54] vdd 0.63fF -C1797 la_data_out[54] vdd 0.63fF -C1798 la_data_in[54] vdd 0.63fF -C1799 la_oenb[53] vdd 0.63fF -C1800 la_data_out[53] vdd 0.63fF -C1801 la_data_in[53] vdd 0.63fF -C1802 la_oenb[52] vdd 0.63fF -C1803 la_data_out[52] vdd 0.63fF -C1804 la_data_in[52] vdd 0.63fF -C1805 la_oenb[51] vdd 0.63fF -C1806 la_data_out[51] vdd 0.63fF -C1807 la_data_in[51] vdd 0.63fF -C1808 la_oenb[50] vdd 0.63fF -C1809 la_data_out[50] vdd 0.63fF -C1810 la_data_in[50] vdd 0.63fF -C1811 la_oenb[49] vdd 0.63fF -C1812 la_data_out[49] vdd 0.63fF -C1813 la_data_in[49] vdd 0.63fF -C1814 la_oenb[48] vdd 0.63fF -C1815 la_data_out[48] vdd 0.63fF -C1816 la_data_in[48] vdd 0.63fF -C1817 la_oenb[47] vdd 0.63fF -C1818 la_data_out[47] vdd 0.63fF -C1819 la_data_in[47] vdd 0.63fF -C1820 la_oenb[46] vdd 0.63fF -C1821 la_data_out[46] vdd 0.63fF -C1822 la_data_in[46] vdd 0.63fF -C1823 la_oenb[45] vdd 0.63fF -C1824 la_data_out[45] vdd 0.63fF -C1825 la_data_in[45] vdd 0.63fF -C1826 la_oenb[44] vdd 0.63fF -C1827 la_data_out[44] vdd 0.63fF -C1828 la_data_in[44] vdd 0.63fF -C1829 la_oenb[43] vdd 0.63fF -C1830 la_data_out[43] vdd 0.63fF -C1831 la_data_in[43] vdd 0.63fF -C1832 la_oenb[42] vdd 0.63fF -C1833 la_data_out[42] vdd 0.63fF -C1834 la_data_in[42] vdd 0.63fF -C1835 la_oenb[41] vdd 0.63fF -C1836 la_data_out[41] vdd 0.63fF -C1837 la_data_in[41] vdd 0.63fF -C1838 la_oenb[40] vdd 0.63fF -C1839 la_data_out[40] vdd 0.63fF -C1840 la_data_in[40] vdd 0.63fF -C1841 la_oenb[39] vdd 0.63fF -C1842 la_data_out[39] vdd 0.63fF -C1843 la_data_in[39] vdd 0.63fF -C1844 la_oenb[38] vdd 0.63fF -C1845 la_data_out[38] vdd 0.63fF -C1846 la_data_in[38] vdd 0.63fF -C1847 la_oenb[37] vdd 0.63fF -C1848 la_data_out[37] vdd 0.63fF -C1849 la_data_in[37] vdd 0.63fF -C1850 la_oenb[36] vdd 0.63fF -C1851 la_data_out[36] vdd 0.63fF -C1852 la_data_in[36] vdd 0.63fF -C1853 la_oenb[35] vdd 0.63fF -C1854 la_data_out[35] vdd 0.63fF -C1855 la_data_in[35] vdd 0.63fF -C1856 la_oenb[34] vdd 0.63fF -C1857 la_data_out[34] vdd 0.63fF -C1858 la_data_in[34] vdd 0.63fF -C1859 la_oenb[33] vdd 0.63fF -C1860 la_data_out[33] vdd 0.63fF -C1861 la_data_in[33] vdd 0.63fF -C1862 la_oenb[32] vdd 0.63fF -C1863 la_data_out[32] vdd 0.63fF -C1864 la_data_in[32] vdd 0.63fF -C1865 la_oenb[31] vdd 0.63fF -C1866 la_data_out[31] vdd 0.63fF -C1867 la_data_in[31] vdd 0.63fF -C1868 la_oenb[30] vdd 0.63fF -C1869 la_data_out[30] vdd 0.63fF -C1870 la_data_in[30] vdd 0.63fF -C1871 la_oenb[29] vdd 0.63fF -C1872 la_data_out[29] vdd 0.63fF -C1873 la_data_in[29] vdd 0.63fF -C1874 la_oenb[28] vdd 0.63fF -C1875 la_data_out[28] vdd 0.63fF -C1876 la_data_in[28] vdd 0.63fF -C1877 la_oenb[27] vdd 0.63fF -C1878 la_data_out[27] vdd 0.63fF -C1879 la_data_in[27] vdd 0.63fF -C1880 la_oenb[26] vdd 0.63fF -C1881 la_data_out[26] vdd 0.63fF -C1882 la_data_in[26] vdd 0.63fF -C1883 la_oenb[25] vdd 0.63fF -C1884 la_data_out[25] vdd 0.63fF -C1885 la_data_in[25] vdd 0.63fF -C1886 la_oenb[24] vdd 0.63fF -C1887 la_data_out[24] vdd 0.63fF -C1888 la_data_in[24] vdd 0.63fF -C1889 la_oenb[23] vdd 0.63fF -C1890 la_data_out[23] vdd 0.63fF -C1891 la_data_in[23] vdd 0.63fF -C1892 la_oenb[22] vdd 0.63fF -C1893 la_data_out[22] vdd 0.63fF -C1894 la_data_in[22] vdd 0.63fF -C1895 la_oenb[21] vdd 0.63fF -C1896 la_data_out[21] vdd 0.63fF -C1897 la_data_in[21] vdd 0.63fF -C1898 la_oenb[20] vdd 0.63fF -C1899 la_data_out[20] vdd 0.63fF -C1900 la_data_in[20] vdd 0.63fF -C1901 la_oenb[19] vdd 0.63fF -C1902 la_data_out[19] vdd 0.63fF -C1903 la_data_in[19] vdd 0.63fF -C1904 la_oenb[18] vdd 0.63fF -C1905 la_data_out[18] vdd 0.63fF -C1906 la_data_in[18] vdd 0.63fF -C1907 la_oenb[17] vdd 0.63fF -C1908 la_data_out[17] vdd 0.63fF -C1909 la_data_in[17] vdd 0.63fF -C1910 la_oenb[16] vdd 0.63fF -C1911 la_data_out[16] vdd 0.63fF -C1912 la_data_in[16] vdd 0.63fF -C1913 la_oenb[15] vdd 0.63fF -C1914 la_data_out[15] vdd 0.63fF -C1915 la_data_in[15] vdd 0.63fF -C1916 la_oenb[14] vdd 0.63fF -C1917 la_data_out[14] vdd 0.63fF -C1918 la_data_in[14] vdd 0.63fF -C1919 la_oenb[13] vdd 0.63fF -C1920 la_data_out[13] vdd 0.63fF -C1921 la_data_in[13] vdd 0.63fF -C1922 la_oenb[12] vdd 0.63fF -C1923 la_data_out[12] vdd 0.63fF -C1924 la_data_in[12] vdd 0.63fF -C1925 la_oenb[11] vdd 0.63fF -C1926 la_data_out[11] vdd 0.63fF -C1927 la_data_in[11] vdd 0.63fF -C1928 la_oenb[10] vdd 0.63fF -C1929 la_data_out[10] vdd 0.63fF -C1930 la_data_in[10] vdd 0.63fF -C1931 la_oenb[9] vdd 0.63fF -C1932 la_data_out[9] vdd 0.63fF -C1933 la_data_in[9] vdd 0.63fF -C1934 la_oenb[8] vdd 0.63fF -C1935 la_data_out[8] vdd 0.63fF -C1936 la_data_in[8] vdd 0.63fF -C1937 la_oenb[7] vdd 0.63fF -C1938 la_data_out[7] vdd 0.63fF -C1939 la_data_in[7] vdd 0.63fF -C1940 la_oenb[6] vdd 0.63fF -C1941 la_data_out[6] vdd 0.63fF -C1942 la_data_in[6] vdd 0.63fF -C1943 la_oenb[5] vdd 0.63fF -C1944 la_data_out[5] vdd 0.63fF -C1945 la_data_in[5] vdd 0.63fF -C1946 la_oenb[4] vdd 0.63fF -C1947 la_data_out[4] vdd 0.63fF -C1948 la_data_in[4] vdd 0.63fF -C1949 la_oenb[3] vdd 0.63fF -C1950 la_data_out[3] vdd 0.63fF -C1951 la_data_in[3] vdd 0.63fF -C1952 la_oenb[2] vdd 0.63fF -C1953 la_data_out[2] vdd 0.63fF -C1954 la_data_in[2] vdd 0.63fF -C1955 la_oenb[1] vdd 0.63fF -C1956 la_data_out[1] vdd 0.63fF -C1957 la_data_in[1] vdd 0.63fF -C1958 la_oenb[0] vdd 0.63fF -C1959 la_data_out[0] vdd 0.63fF -C1960 la_data_in[0] vdd 0.63fF -C1961 wbs_dat_o[31] vdd 0.63fF -C1962 wbs_dat_i[31] vdd 0.63fF -C1963 wbs_adr_i[31] vdd 0.63fF -C1964 wbs_dat_o[30] vdd 0.63fF -C1965 wbs_dat_i[30] vdd 0.63fF -C1966 wbs_adr_i[30] vdd 0.63fF -C1967 wbs_dat_o[29] vdd 0.63fF -C1968 wbs_dat_i[29] vdd 0.63fF -C1969 wbs_adr_i[29] vdd 0.63fF -C1970 wbs_dat_o[28] vdd 0.63fF -C1971 wbs_dat_i[28] vdd 0.63fF -C1972 wbs_adr_i[28] vdd 0.63fF -C1973 wbs_dat_o[27] vdd 0.63fF -C1974 wbs_dat_i[27] vdd 0.63fF -C1975 wbs_adr_i[27] vdd 0.63fF -C1976 wbs_dat_o[26] vdd 0.63fF -C1977 wbs_dat_i[26] vdd 0.63fF -C1978 wbs_adr_i[26] vdd 0.63fF -C1979 wbs_dat_o[25] vdd 0.63fF -C1980 wbs_dat_i[25] vdd 0.63fF -C1981 wbs_adr_i[25] vdd 0.63fF -C1982 wbs_dat_o[24] vdd 0.63fF -C1983 wbs_dat_i[24] vdd 0.63fF -C1984 wbs_adr_i[24] vdd 0.63fF -C1985 wbs_dat_o[23] vdd 0.63fF -C1986 wbs_dat_i[23] vdd 0.63fF -C1987 wbs_adr_i[23] vdd 0.63fF -C1988 wbs_dat_o[22] vdd 0.63fF -C1989 wbs_dat_i[22] vdd 0.63fF -C1990 wbs_adr_i[22] vdd 0.63fF -C1991 wbs_dat_o[21] vdd 0.63fF -C1992 wbs_dat_i[21] vdd 0.63fF -C1993 wbs_adr_i[21] vdd 0.63fF -C1994 wbs_dat_o[20] vdd 0.63fF -C1995 wbs_dat_i[20] vdd 0.63fF -C1996 wbs_adr_i[20] vdd 0.63fF -C1997 wbs_dat_o[19] vdd 0.63fF -C1998 wbs_dat_i[19] vdd 0.63fF -C1999 wbs_adr_i[19] vdd 0.63fF -C2000 wbs_dat_o[18] vdd 0.63fF -C2001 wbs_dat_i[18] vdd 0.63fF -C2002 wbs_adr_i[18] vdd 0.63fF -C2003 wbs_dat_o[17] vdd 0.63fF -C2004 wbs_dat_i[17] vdd 0.63fF -C2005 wbs_adr_i[17] vdd 0.63fF -C2006 wbs_dat_o[16] vdd 0.63fF -C2007 wbs_dat_i[16] vdd 0.63fF -C2008 wbs_adr_i[16] vdd 0.63fF -C2009 wbs_dat_o[15] vdd 0.63fF -C2010 wbs_dat_i[15] vdd 0.63fF -C2011 wbs_adr_i[15] vdd 0.63fF -C2012 wbs_dat_o[14] vdd 0.63fF -C2013 wbs_dat_i[14] vdd 0.63fF -C2014 wbs_adr_i[14] vdd 0.63fF -C2015 wbs_dat_o[13] vdd 0.63fF -C2016 wbs_dat_i[13] vdd 0.63fF -C2017 wbs_adr_i[13] vdd 0.63fF -C2018 wbs_dat_o[12] vdd 0.63fF -C2019 wbs_dat_i[12] vdd 0.63fF -C2020 wbs_adr_i[12] vdd 0.63fF -C2021 wbs_dat_o[11] vdd 0.63fF -C2022 wbs_dat_i[11] vdd 0.63fF -C2023 wbs_adr_i[11] vdd 0.63fF -C2024 wbs_dat_o[10] vdd 0.63fF -C2025 wbs_dat_i[10] vdd 0.63fF -C2026 wbs_adr_i[10] vdd 0.63fF -C2027 wbs_dat_o[9] vdd 0.63fF -C2028 wbs_dat_i[9] vdd 0.63fF -C2029 wbs_adr_i[9] vdd 0.63fF -C2030 wbs_dat_o[8] vdd 0.63fF -C2031 wbs_dat_i[8] vdd 0.63fF -C2032 wbs_adr_i[8] vdd 0.63fF -C2033 wbs_dat_o[7] vdd 0.63fF -C2034 wbs_dat_i[7] vdd 0.63fF -C2035 wbs_adr_i[7] vdd 0.63fF -C2036 wbs_dat_o[6] vdd 0.63fF -C2037 wbs_dat_i[6] vdd 0.63fF -C2038 wbs_adr_i[6] vdd 0.63fF -C2039 wbs_dat_o[5] vdd 0.63fF -C2040 wbs_dat_i[5] vdd 0.63fF -C2041 wbs_adr_i[5] vdd 0.63fF -C2042 wbs_dat_o[4] vdd 0.63fF -C2043 wbs_dat_i[4] vdd 0.63fF -C2044 wbs_adr_i[4] vdd 0.63fF -C2045 wbs_sel_i[3] vdd 0.63fF -C2046 wbs_dat_o[3] vdd 0.63fF -C2047 wbs_dat_i[3] vdd 0.63fF -C2048 wbs_adr_i[3] vdd 0.63fF -C2049 wbs_sel_i[2] vdd 0.63fF -C2050 wbs_dat_o[2] vdd 0.63fF -C2051 wbs_dat_i[2] vdd 0.63fF -C2052 wbs_adr_i[2] vdd 0.63fF -C2053 wbs_sel_i[1] vdd 0.63fF -C2054 wbs_dat_o[1] vdd 0.63fF -C2055 wbs_dat_i[1] vdd 0.63fF -C2056 wbs_adr_i[1] vdd 0.63fF -C2057 wbs_sel_i[0] vdd 0.63fF -C2058 wbs_dat_o[0] vdd 0.63fF -C2059 wbs_dat_i[0] vdd 0.63fF -C2060 wbs_adr_i[0] vdd 0.63fF -C2061 wbs_we_i vdd 0.63fF -C2062 wbs_stb_i vdd 0.63fF -C2063 wbs_cyc_i vdd 0.63fF -C2064 wbs_ack_o vdd 0.63fF -C2065 wb_rst_i vdd 0.63fF -C2066 wb_clk_i vdd 0.63fF -C2067 pll_full_0/divider_0/and_0/Z1 vdd 0.65fF -C2068 pll_full_0/divider_0/and_0/B vdd 2.45fF -C2069 pll_full_0/divider_0/and_0/A vdd 2.35fF -C2070 pll_full_0/divider_0/and_0/out1 vdd 2.99fF -C2071 pll_full_0/divider_0/tspc_2/Z4 vdd 0.86fF -C2072 pll_full_0/divbuf_0/IN vdd 9.95fF -C2073 pll_full_0/divider_0/tspc_2/Z3 vdd 2.26fF -C2074 pll_full_0/divider_0/tspc_2/Z2 vdd 1.46fF -C2075 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF -C2076 pll_full_0/divider_0/nor_0/B vdd 6.48fF -C2077 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C2078 pll_full_0/divider_0/tspc_1/Z4 vdd 0.86fF -C2079 pll_full_0/divider_0/tspc_1/Q vdd 3.12fF -C2080 pll_full_0/divider_0/tspc_1/Z3 vdd 2.26fF -C2081 pll_full_0/divider_0/tspc_1/Z2 vdd 1.46fF -C2082 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF -C2083 pll_full_0/divider_0/nor_1/B vdd 7.12fF -C2084 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C2085 pll_full_0/divider_0/tspc_0/Z4 vdd 0.86fF -C2086 pll_full_0/divider_0/tspc_0/Q vdd 3.14fF -C2087 pll_full_0/divider_0/tspc_0/Z3 vdd 2.26fF -C2088 pll_full_0/divider_0/tspc_0/Z2 vdd 1.46fF -C2089 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF -C2090 pll_full_0/divider_0/nor_1/A vdd 7.08fF -C2091 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C2092 pll_full_0/divider_0/clk vdd 31.85fF -C2093 pll_full_0/divider_0/prescaler_0/Out vdd 4.59fF -C2094 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C2095 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C2096 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C2097 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C2098 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C2099 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C2100 pll_full_0/divider_0/and_0/OUT vdd 5.67fF -C2101 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C2102 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C2103 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C2104 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2105 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C2106 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C2107 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C2108 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C2109 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C2110 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2111 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C2112 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C2113 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C2114 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C2115 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.19fF -C2116 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2117 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.47fF **FLOATING -C2118 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C2119 pll_full_0/divider_0/nor_1/Z1 vdd 1.34fF -C2120 pll_full_0/divider_0/nor_0/Z1 vdd 1.34fF -C2121 pll_full_0/divbuf_1/OUT vdd 363.82fF -C2122 pll_full_0/divbuf_1/OUT5 vdd 350.37fF -C2123 pll_full_0/divbuf_1/OUT4 vdd 133.72fF -C2124 pll_full_0/divbuf_1/OUT3 vdd 34.03fF -C2125 pll_full_0/divbuf_1/OUT2 vdd 8.71fF -C2126 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C2127 pll_full_0/divbuf_0/OUT5 vdd 350.37fF -C2128 pll_full_0/divbuf_0/OUT4 vdd 133.72fF -C2129 pll_full_0/divbuf_0/OUT3 vdd 34.03fF -C2130 pll_full_0/divbuf_0/OUT2 vdd 8.71fF -C2131 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C2132 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF -C2133 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C2134 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C2135 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C2136 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C2137 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C2138 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C2139 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C2140 pll_full_0/ro_complete_0/a0 vdd 7.88fF -C2141 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C2142 pll_full_0/ro_complete_0/a1 vdd 5.39fF -C2143 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C2144 pll_full_0/ro_complete_0/a3 vdd 6.85fF -C2145 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C2146 pll_full_0/ro_complete_0/a2 vdd 5.48fF -C2147 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C2148 pll_full_0/ro_complete_0/a4 vdd 5.36fF -C2149 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C2150 pll_full_0/ro_complete_0/a5 vdd 5.19fF -C2151 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF -C2152 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C2153 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C2154 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C2155 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C2156 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C2157 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C2158 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C2159 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING -C2160 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING -C2161 pll_full_0/cp_0/down vdd 1.54fF -C2162 pll_full_0/cp_0/upbar vdd 1.79fF -C2163 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C2164 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C2165 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING -C2166 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING -C2167 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING -C2168 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING -C2169 pll_full_0/pd_0/UP vdd 6.61fF -C2170 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF -C2171 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF -C2172 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF -C2173 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF -C2174 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF -C2175 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF -C2176 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF -C2177 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C2178 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF -C2179 pll_full_0/pd_0/REF vdd 6.44fF -C2180 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF -C2181 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF -C2182 pll_full_0/pd_0/R vdd 3.05fF -C2183 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF -C2184 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF -C2185 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF -C2186 pll_full_0/pd_0/DOWN vdd 7.24fF -C2187 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C2188 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF -C2189 pll_full_0/pd_0/DIV vdd 371.87fF -C2190 divider_2/and_0/Z1 vdd 0.74fF -C2191 divider_2/and_0/B vdd 2.25fF -C2192 divider_2/and_0/A vdd 2.19fF -C2193 divider_2/and_0/out1 vdd 2.93fF -C2194 divider_2/tspc_2/Z4 vdd 0.86fF -C2195 divider_2/Out vdd 1.60fF -C2196 divider_2/tspc_2/Z3 vdd 2.26fF -C2197 divider_2/tspc_2/Z2 vdd 1.46fF -C2198 divider_2/tspc_2/Z1 vdd 0.99fF -C2199 divider_2/nor_0/B vdd 6.33fF -C2200 divider_2/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C2201 divider_2/tspc_1/Z4 vdd 0.86fF -C2202 divider_2/tspc_1/Q vdd 3.12fF -C2203 divider_2/tspc_1/Z3 vdd 2.26fF -C2204 divider_2/tspc_1/Z2 vdd 1.46fF -C2205 divider_2/tspc_1/Z1 vdd 0.99fF -C2206 divider_2/nor_1/B vdd 7.05fF -C2207 divider_2/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C2208 divider_2/tspc_0/Z4 vdd 0.86fF -C2209 divider_2/tspc_0/Q vdd 3.14fF -C2210 divider_2/tspc_0/Z3 vdd 2.26fF -C2211 divider_2/tspc_0/Z2 vdd 1.46fF -C2212 divider_2/tspc_0/Z1 vdd 0.99fF -C2213 divider_2/nor_1/A vdd 7.04fF -C2214 divider_2/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C2215 divider_2/clk vdd 5.63fF -C2216 divider_2/prescaler_0/Out vdd 4.59fF -C2217 divider_2/prescaler_0/nand_1/z1 vdd 0.36fF -C2218 divider_2/prescaler_0/tspc_2/D vdd 2.64fF -C2219 divider_2/prescaler_0/tspc_0/Q vdd 3.64fF -C2220 divider_2/prescaler_0/tspc_1/Q vdd 3.61fF -C2221 divider_2/prescaler_0/nand_0/z1 vdd 0.36fF -C2222 divider_2/prescaler_0/tspc_0/D vdd 3.12fF -C2223 divider_2/and_0/OUT vdd 5.62fF -C2224 divider_2/prescaler_0/tspc_2/Z4 vdd 0.86fF -C2225 divider_2/prescaler_0/tspc_2/Z3 vdd 2.26fF -C2226 divider_2/prescaler_0/tspc_2/Z2 vdd 1.46fF -C2227 divider_2/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2228 divider_2/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C2229 divider_2/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C2230 divider_2/prescaler_0/tspc_1/Z4 vdd 0.86fF -C2231 divider_2/prescaler_0/tspc_1/Z3 vdd 2.26fF -C2232 divider_2/prescaler_0/tspc_1/Z2 vdd 1.48fF -C2233 divider_2/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2234 divider_2/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C2235 divider_2/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C2236 divider_2/prescaler_0/tspc_0/Z4 vdd 0.86fF -C2237 divider_2/prescaler_0/tspc_0/Z3 vdd 2.26fF -C2238 divider_2/prescaler_0/tspc_0/Z2 vdd 1.46fF -C2239 divider_2/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2240 divider_2/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING -C2241 divider_2/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C2242 divider_2/nor_1/Z1 vdd 1.34fF -C2243 divider_2/nor_0/Z1 vdd 1.34fF -C2244 divider_2/mc2 vdd 5.29fF -C2245 divider_1/and_0/Z1 vdd 0.74fF -C2246 divider_1/and_0/B vdd 2.25fF -C2247 divider_1/and_0/A vdd 2.19fF -C2248 divider_1/and_0/out1 vdd 2.93fF -C2249 divider_1/tspc_2/Z4 vdd 0.86fF -C2250 divider_1/Out vdd 1.60fF -C2251 divider_1/tspc_2/Z3 vdd 2.26fF -C2252 divider_1/tspc_2/Z2 vdd 1.46fF -C2253 divider_1/tspc_2/Z1 vdd 0.99fF -C2254 divider_1/nor_0/B vdd 6.33fF -C2255 divider_1/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C2256 divider_1/tspc_1/Z4 vdd 0.86fF -C2257 divider_1/tspc_1/Q vdd 3.12fF -C2258 divider_1/tspc_1/Z3 vdd 2.26fF -C2259 divider_1/tspc_1/Z2 vdd 1.46fF -C2260 divider_1/tspc_1/Z1 vdd 0.99fF -C2261 divider_1/nor_1/B vdd 7.05fF -C2262 divider_1/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C2263 divider_1/tspc_0/Z4 vdd 0.86fF -C2264 divider_1/tspc_0/Q vdd 3.14fF -C2265 divider_1/tspc_0/Z3 vdd 2.26fF -C2266 divider_1/tspc_0/Z2 vdd 1.46fF -C2267 divider_1/tspc_0/Z1 vdd 0.99fF -C2268 divider_1/nor_1/A vdd 7.04fF -C2269 divider_1/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C2270 divider_1/clk vdd 5.63fF -C2271 divider_1/prescaler_0/Out vdd 4.59fF -C2272 divider_1/prescaler_0/nand_1/z1 vdd 0.36fF -C2273 divider_1/prescaler_0/tspc_2/D vdd 2.64fF -C2274 divider_1/prescaler_0/tspc_0/Q vdd 3.64fF -C2275 divider_1/prescaler_0/tspc_1/Q vdd 3.61fF -C2276 divider_1/prescaler_0/nand_0/z1 vdd 0.36fF -C2277 divider_1/prescaler_0/tspc_0/D vdd 3.12fF -C2278 divider_1/and_0/OUT vdd 5.62fF -C2279 divider_1/prescaler_0/tspc_2/Z4 vdd 0.86fF -C2280 divider_1/prescaler_0/tspc_2/Z3 vdd 2.26fF -C2281 divider_1/prescaler_0/tspc_2/Z2 vdd 1.46fF -C2282 divider_1/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2283 divider_1/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C2284 divider_1/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C2285 divider_1/prescaler_0/tspc_1/Z4 vdd 0.86fF -C2286 divider_1/prescaler_0/tspc_1/Z3 vdd 2.26fF -C2287 divider_1/prescaler_0/tspc_1/Z2 vdd 1.48fF -C2288 divider_1/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2289 divider_1/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C2290 divider_1/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C2291 divider_1/prescaler_0/tspc_0/Z4 vdd 0.86fF -C2292 divider_1/prescaler_0/tspc_0/Z3 vdd 2.26fF -C2293 divider_1/prescaler_0/tspc_0/Z2 vdd 1.46fF -C2294 divider_1/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2295 divider_1/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING -C2296 divider_1/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C2297 divider_1/nor_1/Z1 vdd 1.34fF -C2298 divider_1/nor_0/Z1 vdd 1.34fF -C2299 divider_1/mc2 vdd 5.29fF -C2300 divider_0/and_0/Z1 vdd 0.74fF -C2301 divider_0/and_0/B vdd 2.25fF -C2302 divider_0/and_0/A vdd 2.19fF -C2303 divider_0/and_0/out1 vdd 2.93fF -C2304 divider_0/tspc_2/Z4 vdd 0.86fF -C2305 divider_0/Out vdd 1.60fF -C2306 divider_0/tspc_2/Z3 vdd 2.26fF -C2307 divider_0/tspc_2/Z2 vdd 1.46fF -C2308 divider_0/tspc_2/Z1 vdd 0.99fF -C2309 divider_0/nor_0/B vdd 6.33fF -C2310 divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C2311 divider_0/tspc_1/Z4 vdd 0.86fF -C2312 divider_0/tspc_1/Q vdd 3.12fF -C2313 divider_0/tspc_1/Z3 vdd 2.26fF -C2314 divider_0/tspc_1/Z2 vdd 1.46fF -C2315 divider_0/tspc_1/Z1 vdd 0.99fF -C2316 divider_0/nor_1/B vdd 7.05fF -C2317 divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C2318 divider_0/tspc_0/Z4 vdd 0.86fF -C2319 divider_0/tspc_0/Q vdd 3.14fF -C2320 divider_0/tspc_0/Z3 vdd 2.26fF -C2321 divider_0/tspc_0/Z2 vdd 1.46fF -C2322 divider_0/tspc_0/Z1 vdd 0.99fF -C2323 divider_0/nor_1/A vdd 7.04fF -C2324 divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C2325 divider_0/clk vdd 5.63fF -C2326 divider_0/prescaler_0/Out vdd 4.59fF -C2327 divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C2328 divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C2329 divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C2330 divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C2331 divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C2332 divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C2333 divider_0/and_0/OUT vdd 5.62fF -C2334 divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C2335 divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C2336 divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C2337 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2338 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C2339 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C2340 divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C2341 divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C2342 divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C2343 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2344 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C2345 divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C2346 divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C2347 divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C2348 divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF -C2349 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2350 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING -C2351 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C2352 divider_0/nor_1/Z1 vdd 1.34fF -C2353 divider_0/nor_0/Z1 vdd 1.34fF -C2354 divider_0/mc2 vdd 5.29fF -C2355 divbuf_7/OUT vdd 363.82fF -C2356 divbuf_7/OUT5 vdd 350.37fF -C2357 divbuf_7/OUT4 vdd 133.72fF -C2358 divbuf_7/OUT3 vdd 34.03fF -C2359 divbuf_7/OUT2 vdd 8.71fF -C2360 divbuf_7/IN vdd 0.89fF -C2361 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING -C2362 divbuf_6/OUT vdd 363.82fF -C2363 divbuf_6/OUT5 vdd 350.37fF -C2364 divbuf_6/OUT4 vdd 133.72fF -C2365 divbuf_6/OUT3 vdd 34.03fF -C2366 divbuf_6/OUT2 vdd 8.71fF -C2367 divbuf_6/IN vdd 0.89fF -C2368 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING -C2369 divbuf_5/OUT vdd 363.82fF -C2370 divbuf_5/OUT5 vdd 350.37fF -C2371 divbuf_5/OUT4 vdd 133.72fF -C2372 divbuf_5/OUT3 vdd 34.03fF -C2373 divbuf_5/OUT2 vdd 8.71fF -C2374 divbuf_5/IN vdd 0.89fF -C2375 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING -C2376 divbuf_4/OUT vdd 363.82fF -C2377 divbuf_4/OUT5 vdd 350.37fF -C2378 divbuf_4/OUT4 vdd 133.72fF -C2379 divbuf_4/OUT3 vdd 34.03fF -C2380 divbuf_4/OUT2 vdd 8.71fF -C2381 divbuf_4/IN vdd 0.89fF -C2382 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING -C2383 divbuf_3/OUT vdd 363.82fF -C2384 divbuf_3/OUT5 vdd 350.37fF -C2385 divbuf_3/OUT4 vdd 133.72fF -C2386 divbuf_3/OUT3 vdd 34.03fF -C2387 divbuf_3/OUT2 vdd 8.71fF -C2388 divbuf_3/IN vdd 0.89fF -C2389 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING -C2390 divbuf_2/OUT vdd 363.82fF -C2391 divbuf_2/OUT5 vdd 350.37fF -C2392 divbuf_2/OUT4 vdd 133.72fF -C2393 divbuf_2/OUT3 vdd 34.03fF -C2394 divbuf_2/OUT2 vdd 8.71fF -C2395 divbuf_2/IN vdd 0.89fF -C2396 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING -C2397 divbuf_1/OUT vdd 363.82fF -C2398 divbuf_1/OUT5 vdd 350.37fF -C2399 divbuf_1/OUT4 vdd 133.72fF -C2400 divbuf_1/OUT3 vdd 34.03fF -C2401 divbuf_1/OUT2 vdd 8.71fF -C2402 divbuf_1/IN vdd 0.89fF -C2403 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C2404 ro_complete_1/cbank_2/v vdd 17.84fF -C2405 ro_complete_1/cbank_2/switch_5/vin vdd 0.78fF -C2406 ro_complete_1/cbank_2/switch_4/vin vdd 1.50fF -C2407 ro_complete_1/cbank_2/switch_2/vin vdd 1.30fF -C2408 ro_complete_1/cbank_2/switch_3/vin vdd 0.56fF -C2409 ro_complete_1/cbank_2/switch_1/vin vdd 1.14fF -C2410 ro_complete_1/cbank_2/switch_0/vin vdd 1.02fF -C2411 ro_complete_1/cbank_1/v vdd 16.34fF -C2412 ro_complete_1/cbank_1/switch_5/vin vdd 0.78fF -C2413 ro_complete_1/a0 vdd 7.88fF -C2414 ro_complete_1/cbank_1/switch_4/vin vdd 1.50fF -C2415 ro_complete_1/a1 vdd 5.39fF -C2416 ro_complete_1/cbank_1/switch_2/vin vdd 1.30fF -C2417 ro_complete_1/a3 vdd 6.85fF -C2418 ro_complete_1/cbank_1/switch_3/vin vdd 0.56fF -C2419 ro_complete_1/a2 vdd 5.48fF -C2420 ro_complete_1/cbank_1/switch_1/vin vdd 1.14fF -C2421 ro_complete_1/a4 vdd 5.36fF -C2422 ro_complete_1/cbank_1/switch_0/vin vdd 1.02fF -C2423 ro_complete_1/a5 vdd 5.19fF -C2424 ro_complete_1/cbank_0/v vdd 14.98fF -C2425 ro_complete_1/cbank_0/switch_5/vin vdd 0.78fF -C2426 ro_complete_1/cbank_0/switch_4/vin vdd 1.50fF -C2427 ro_complete_1/cbank_0/switch_2/vin vdd 1.30fF -C2428 ro_complete_1/cbank_0/switch_3/vin vdd 0.56fF -C2429 ro_complete_1/cbank_0/switch_1/vin vdd 1.14fF -C2430 ro_complete_1/cbank_0/switch_0/vin vdd 1.02fF -C2431 ro_complete_1/ro_var_extend_0/vcont vdd 0.27fF -C2432 divbuf_0/OUT vdd 363.82fF -C2433 divbuf_0/OUT5 vdd 350.37fF -C2434 divbuf_0/OUT4 vdd 133.72fF -C2435 divbuf_0/OUT3 vdd 34.03fF -C2436 divbuf_0/OUT2 vdd 8.71fF -C2437 divbuf_0/IN vdd 0.89fF -C2438 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C2439 ro_complete_0/cbank_2/v vdd 17.84fF -C2440 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C2441 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C2442 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C2443 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C2444 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C2445 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C2446 ro_complete_0/cbank_1/v vdd 16.34fF -C2447 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C2448 ro_complete_0/a0 vdd 7.88fF -C2449 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C2450 ro_complete_0/a1 vdd 5.39fF -C2451 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C2452 ro_complete_0/a3 vdd 6.85fF -C2453 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C2454 ro_complete_0/a2 vdd 5.48fF -C2455 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C2456 ro_complete_0/a4 vdd 5.36fF -C2457 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C2458 ro_complete_0/a5 vdd 5.19fF -C2459 ro_complete_0/cbank_0/v vdd 14.98fF -C2460 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C2461 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C2462 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C2463 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C2464 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C2465 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C2466 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C2467 filter_0/v vdd 85.69fF -C2468 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING -C2469 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING -C2470 cp_0/down vdd 1.54fF -C2471 cp_0/vbias vdd 2.41fF -C2472 cp_0/out vdd 5.26fF -C2473 cp_0/upbar vdd 1.50fF -C2474 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C2475 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C2476 cp_0/a_7110_0# vdd 0.17fF **FLOATING -C2477 cp_0/a_6370_0# vdd 0.40fF **FLOATING -C2478 cp_0/a_3060_0# vdd 1.65fF **FLOATING -C2479 cp_0/a_1710_0# vdd 5.76fF **FLOATING -C2480 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING -C2481 cp_0/a_10_n50# vdd 2.96fF **FLOATING -C2482 pd_1/UP vdd 2.21fF -C2483 pd_1/and_pd_0/Z1 vdd 0.39fF -C2484 pd_1/and_pd_0/Out1 vdd 2.22fF -C2485 pd_1/tspc_r_1/z5 vdd 1.10fF -C2486 pd_1/tspc_r_1/Z4 vdd 1.07fF -C2487 pd_1/tspc_r_1/Qbar vdd 0.88fF -C2488 pd_1/tspc_r_1/Z2 vdd 1.22fF -C2489 pd_1/tspc_r_1/Z1 vdd 0.67fF -C2490 pd_1/tspc_r_1/Qbar1 vdd 1.34fF -C2491 pd_1/tspc_r_1/Z3 vdd 2.12fF -C2492 pd_1/REF vdd 1.80fF -C2493 pd_1/tspc_r_0/z5 vdd 1.10fF -C2494 pd_1/tspc_r_0/Z4 vdd 1.07fF -C2495 pd_1/R vdd 3.05fF -C2496 pd_1/tspc_r_0/Qbar vdd 0.79fF -C2497 pd_1/tspc_r_0/Z2 vdd 1.22fF -C2498 pd_1/tspc_r_0/Z1 vdd 0.67fF -C2499 pd_1/DOWN vdd 3.08fF -C2500 pd_1/tspc_r_0/Qbar1 vdd 1.34fF -C2501 pd_1/tspc_r_0/Z3 vdd 2.12fF -C2502 pd_1/DIV vdd 1.82fF -C2503 pd_0/UP vdd 2.21fF -C2504 pd_0/and_pd_0/Z1 vdd 0.39fF -C2505 pd_0/and_pd_0/Out1 vdd 2.22fF -C2506 pd_0/tspc_r_1/z5 vdd 1.10fF -C2507 pd_0/tspc_r_1/Z4 vdd 1.07fF -C2508 pd_0/tspc_r_1/Qbar vdd 0.88fF -C2509 pd_0/tspc_r_1/Z2 vdd 1.22fF -C2510 pd_0/tspc_r_1/Z1 vdd 0.67fF -C2511 pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C2512 pd_0/tspc_r_1/Z3 vdd 2.12fF -C2513 pd_0/REF vdd 1.80fF -C2514 pd_0/tspc_r_0/z5 vdd 1.10fF -C2515 pd_0/tspc_r_0/Z4 vdd 1.07fF -C2516 pd_0/R vdd 3.05fF -C2517 pd_0/tspc_r_0/Qbar vdd 0.79fF -C2518 pd_0/tspc_r_0/Z2 vdd 1.22fF -C2519 pd_0/tspc_r_0/Z1 vdd 0.67fF -C2520 pd_0/DOWN vdd 3.08fF -C2521 pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C2522 pd_0/tspc_r_0/Z3 vdd 2.12fF -C2523 pd_0/DIV vdd 1.82fF +C1598 io_analog[4] vdd 43.96fF +C1599 io_analog[5] vdd 44.13fF +C1600 io_analog[6] vdd 43.46fF +C1601 io_in_3v3[0] vdd 0.61fF +C1602 io_oeb[26] vdd 0.61fF +C1603 io_in[0] vdd 0.61fF +C1604 io_out[26] vdd 0.61fF +C1605 io_out[0] vdd 0.61fF +C1606 io_in[26] vdd 0.61fF +C1607 io_oeb[0] vdd 0.61fF +C1608 io_in_3v3[26] vdd 0.61fF +C1609 io_in_3v3[1] vdd 0.61fF +C1610 io_oeb[25] vdd 0.61fF +C1611 io_in[1] vdd 0.61fF +C1612 io_out[25] vdd 0.61fF +C1613 io_out[1] vdd 0.61fF +C1614 io_in[25] vdd 0.61fF +C1615 io_oeb[1] vdd 0.61fF +C1616 io_in_3v3[25] vdd 0.61fF +C1617 io_in_3v3[2] vdd 0.61fF +C1618 io_oeb[24] vdd 0.61fF +C1619 io_in[2] vdd 0.61fF +C1620 io_out[24] vdd 0.61fF +C1621 io_out[2] vdd 0.61fF +C1622 io_in[24] vdd 0.61fF +C1623 io_oeb[2] vdd 0.61fF +C1624 io_in_3v3[24] vdd 0.61fF +C1625 io_in_3v3[3] vdd 0.61fF +C1626 gpio_noesd[17] vdd 2.32fF +C1627 io_in[3] vdd 0.61fF +C1628 gpio_analog[17] vdd 2.30fF +C1629 io_out[3] vdd 0.61fF +C1630 io_oeb[3] vdd 0.61fF +C1631 io_in_3v3[4] vdd 0.61fF +C1632 io_in[4] vdd 0.61fF +C1633 io_out[4] vdd 0.61fF +C1634 io_oeb[4] vdd 0.61fF +C1635 io_oeb[23] vdd 0.61fF +C1636 io_out[23] vdd 0.61fF +C1637 io_in[23] vdd 0.61fF +C1638 io_in_3v3[23] vdd 0.61fF +C1639 gpio_noesd[16] vdd 2.30fF +C1640 gpio_analog[16] vdd 2.30fF +C1641 io_in_3v3[5] vdd 0.61fF +C1642 io_in[5] vdd 0.61fF +C1643 io_out[5] vdd 0.61fF +C1644 io_oeb[5] vdd 0.61fF +C1645 io_oeb[22] vdd 0.61fF +C1646 io_out[22] vdd 0.61fF +C1647 io_in[22] vdd 0.61fF +C1648 io_in_3v3[22] vdd 0.61fF +C1649 gpio_noesd[15] vdd 2.31fF +C1650 gpio_analog[15] vdd 2.30fF +C1651 io_in_3v3[6] vdd 0.61fF +C1652 io_in[6] vdd 0.61fF +C1653 io_out[6] vdd 0.61fF +C1654 io_oeb[6] vdd 0.61fF +C1655 io_oeb[21] vdd 0.61fF +C1656 io_out[21] vdd 0.61fF +C1657 io_in[21] vdd 0.61fF +C1658 io_in_3v3[21] vdd 0.61fF +C1659 gpio_noesd[14] vdd 2.30fF +C1660 gpio_analog[14] vdd 2.29fF +C1661 vssd2 vdd 38.54fF +C1662 vssd1 vdd 13.04fF +C1663 vdda2 vdd 38.30fF +C1664 io_oeb[20] vdd 0.61fF +C1665 io_out[20] vdd 0.61fF +C1666 io_in[20] vdd 0.61fF +C1667 io_in_3v3[20] vdd 0.61fF +C1668 gpio_noesd[13] vdd 2.31fF +C1669 gpio_analog[13] vdd 2.30fF +C1670 gpio_analog[0] vdd 0.61fF +C1671 gpio_noesd[0] vdd 0.61fF +C1672 io_in_3v3[7] vdd 0.61fF +C1673 io_in[7] vdd 0.61fF +C1674 io_out[7] vdd 0.61fF +C1675 io_oeb[7] vdd 0.61fF +C1676 io_oeb[19] vdd 0.61fF +C1677 io_out[19] vdd 0.61fF +C1678 io_in[19] vdd 0.61fF +C1679 io_in_3v3[19] vdd 0.61fF +C1680 gpio_noesd[12] vdd 2.32fF +C1681 gpio_analog[12] vdd 2.30fF +C1682 gpio_analog[1] vdd 0.61fF +C1683 gpio_noesd[1] vdd 0.61fF +C1684 io_in_3v3[8] vdd 0.61fF +C1685 io_in[8] vdd 0.61fF +C1686 io_out[8] vdd 0.61fF +C1687 io_oeb[8] vdd 0.61fF +C1688 io_oeb[18] vdd 0.61fF +C1689 io_out[18] vdd 0.61fF +C1690 io_in[18] vdd 0.61fF +C1691 io_in_3v3[18] vdd 0.61fF +C1692 gpio_noesd[11] vdd 2.30fF +C1693 gpio_analog[11] vdd 2.29fF +C1694 gpio_analog[2] vdd 0.61fF +C1695 gpio_noesd[2] vdd 0.61fF +C1696 io_in_3v3[9] vdd 0.61fF +C1697 io_in[9] vdd 0.61fF +C1698 io_out[9] vdd 0.61fF +C1699 io_oeb[9] vdd 0.61fF +C1700 io_oeb[17] vdd 0.61fF +C1701 io_out[17] vdd 0.61fF +C1702 io_in[17] vdd 0.61fF +C1703 io_in_3v3[17] vdd 0.61fF +C1704 gpio_noesd[10] vdd 2.31fF +C1705 gpio_analog[10] vdd 2.29fF +C1706 gpio_analog[3] vdd 0.61fF +C1707 gpio_noesd[3] vdd 0.61fF +C1708 io_in_3v3[10] vdd 0.61fF +C1709 io_in[10] vdd 0.61fF +C1710 io_out[10] vdd 0.61fF +C1711 io_oeb[10] vdd 0.61fF +C1712 io_oeb[16] vdd 0.61fF +C1713 io_out[16] vdd 0.61fF +C1714 io_in[16] vdd 0.61fF +C1715 io_in_3v3[16] vdd 0.61fF +C1716 gpio_noesd[9] vdd 2.28fF +C1717 gpio_analog[9] vdd 2.28fF +C1718 gpio_analog[4] vdd 0.61fF +C1719 gpio_noesd[4] vdd 0.61fF +C1720 io_in_3v3[11] vdd 0.61fF +C1721 io_in[11] vdd 0.61fF +C1722 io_out[11] vdd 0.61fF +C1723 io_oeb[11] vdd 0.61fF +C1724 io_oeb[15] vdd 0.61fF +C1725 io_out[15] vdd 0.61fF +C1726 io_in[15] vdd 0.61fF +C1727 io_in_3v3[15] vdd 0.61fF +C1728 gpio_noesd[8] vdd 2.28fF +C1729 gpio_analog[8] vdd 2.26fF +C1730 gpio_analog[5] vdd 0.61fF +C1731 gpio_noesd[5] vdd 0.61fF +C1732 io_in_3v3[12] vdd 0.61fF +C1733 io_in[12] vdd 0.61fF +C1734 io_out[12] vdd 0.61fF +C1735 io_oeb[12] vdd 0.61fF +C1736 io_oeb[14] vdd 0.61fF +C1737 io_out[14] vdd 0.61fF +C1738 io_in[14] vdd 0.61fF +C1739 io_in_3v3[14] vdd 0.61fF +C1740 gpio_noesd[7] vdd 2.30fF +C1741 gpio_analog[7] vdd 2.28fF +C1742 vssa2 vdd 38.35fF +C1743 gpio_analog[6] vdd 5.71fF +C1744 gpio_noesd[6] vdd 5.70fF +C1745 io_in_3v3[13] vdd 0.61fF +C1746 io_in[13] vdd 0.61fF +C1747 io_out[13] vdd 0.61fF +C1748 io_oeb[13] vdd 0.61fF +C1749 vccd1 vdd 39.84fF +C1750 vccd2 vdd 38.46fF +C1751 io_analog[0] vdd 19.99fF +C1752 io_analog[10] vdd 19.36fF +C1753 io_analog[1] vdd 13.17fF +C1754 io_analog[2] vdd 12.57fF +C1755 io_analog[3] vdd 12.83fF +C1756 io_clamp_high[0] vdd 3.58fF +C1757 io_clamp_low[0] vdd 3.58fF +C1758 io_clamp_high[1] vdd 3.58fF +C1759 io_clamp_low[1] vdd 3.58fF +C1760 io_clamp_high[2] vdd 3.58fF +C1761 io_clamp_low[2] vdd 3.58fF +C1762 io_analog[7] vdd 12.74fF +C1763 io_analog[8] vdd 13.08fF +C1764 io_analog[9] vdd 13.08fF +C1765 user_irq[2] vdd 0.63fF +C1766 user_irq[1] vdd 0.63fF +C1767 user_irq[0] vdd 0.63fF +C1768 user_clock2 vdd 0.63fF +C1769 la_oenb[127] vdd 0.63fF +C1770 la_data_out[127] vdd 0.63fF +C1771 la_data_in[127] vdd 0.63fF +C1772 la_oenb[126] vdd 0.63fF +C1773 la_data_out[126] vdd 0.63fF +C1774 la_data_in[126] vdd 0.63fF +C1775 la_oenb[125] vdd 0.63fF +C1776 la_data_out[125] vdd 0.63fF +C1777 la_data_in[125] vdd 0.63fF +C1778 la_oenb[124] vdd 0.63fF +C1779 la_data_out[124] vdd 0.63fF +C1780 la_data_in[124] vdd 0.63fF +C1781 la_oenb[123] vdd 0.63fF +C1782 la_data_out[123] vdd 0.63fF +C1783 la_data_in[123] vdd 0.63fF +C1784 la_oenb[122] vdd 0.63fF +C1785 la_data_out[122] vdd 0.63fF +C1786 la_data_in[122] vdd 0.63fF +C1787 la_oenb[121] vdd 0.63fF +C1788 la_data_out[121] vdd 0.63fF +C1789 la_data_in[121] vdd 0.63fF +C1790 la_oenb[120] vdd 0.63fF +C1791 la_data_out[120] vdd 0.63fF +C1792 la_data_in[120] vdd 0.63fF +C1793 la_oenb[119] vdd 0.63fF +C1794 la_data_out[119] vdd 0.63fF +C1795 la_data_in[119] vdd 0.63fF +C1796 la_oenb[118] vdd 0.63fF +C1797 la_data_out[118] vdd 0.63fF +C1798 la_data_in[118] vdd 0.63fF +C1799 la_oenb[117] vdd 0.63fF +C1800 la_data_out[117] vdd 0.63fF +C1801 la_data_in[117] vdd 0.63fF +C1802 la_oenb[116] vdd 0.63fF +C1803 la_data_out[116] vdd 0.63fF +C1804 la_data_in[116] vdd 0.63fF +C1805 la_oenb[115] vdd 0.63fF +C1806 la_data_out[115] vdd 0.63fF +C1807 la_data_in[115] vdd 0.63fF +C1808 la_oenb[114] vdd 0.63fF +C1809 la_data_out[114] vdd 0.63fF +C1810 la_data_in[114] vdd 0.63fF +C1811 la_oenb[113] vdd 0.63fF +C1812 la_data_out[113] vdd 0.63fF +C1813 la_data_in[113] vdd 0.63fF +C1814 la_oenb[112] vdd 0.63fF +C1815 la_data_out[112] vdd 0.63fF +C1816 la_data_in[112] vdd 0.63fF +C1817 la_oenb[111] vdd 0.63fF +C1818 la_data_out[111] vdd 0.63fF +C1819 la_data_in[111] vdd 0.63fF +C1820 la_oenb[110] vdd 0.63fF +C1821 la_data_out[110] vdd 0.63fF +C1822 la_data_in[110] vdd 0.63fF +C1823 la_oenb[109] vdd 0.63fF +C1824 la_data_out[109] vdd 0.63fF +C1825 la_data_in[109] vdd 0.63fF +C1826 la_oenb[108] vdd 0.63fF +C1827 la_data_out[108] vdd 0.63fF +C1828 la_data_in[108] vdd 0.63fF +C1829 la_oenb[107] vdd 0.63fF +C1830 la_data_out[107] vdd 0.63fF +C1831 la_data_in[107] vdd 0.63fF +C1832 la_oenb[106] vdd 0.63fF +C1833 la_data_out[106] vdd 0.63fF +C1834 la_data_in[106] vdd 0.63fF +C1835 la_oenb[105] vdd 0.63fF +C1836 la_data_out[105] vdd 0.63fF +C1837 la_data_in[105] vdd 0.63fF +C1838 la_oenb[104] vdd 0.63fF +C1839 la_data_out[104] vdd 0.63fF +C1840 la_data_in[104] vdd 0.63fF +C1841 la_oenb[103] vdd 0.63fF +C1842 la_data_out[103] vdd 0.63fF +C1843 la_data_in[103] vdd 0.63fF +C1844 la_oenb[102] vdd 0.63fF +C1845 la_data_out[102] vdd 0.63fF +C1846 la_data_in[102] vdd 0.63fF +C1847 la_oenb[101] vdd 0.63fF +C1848 la_data_out[101] vdd 0.63fF +C1849 la_data_in[101] vdd 0.63fF +C1850 la_oenb[100] vdd 0.63fF +C1851 la_data_out[100] vdd 0.63fF +C1852 la_data_in[100] vdd 0.63fF +C1853 la_oenb[99] vdd 0.63fF +C1854 la_data_out[99] vdd 0.63fF +C1855 la_data_in[99] vdd 0.63fF +C1856 la_oenb[98] vdd 0.63fF +C1857 la_data_out[98] vdd 0.63fF +C1858 la_data_in[98] vdd 0.63fF +C1859 la_oenb[97] vdd 0.63fF +C1860 la_data_out[97] vdd 0.63fF +C1861 la_data_in[97] vdd 0.63fF +C1862 la_oenb[96] vdd 0.63fF +C1863 la_data_out[96] vdd 0.63fF +C1864 la_data_in[96] vdd 0.63fF +C1865 la_oenb[95] vdd 0.63fF +C1866 la_data_out[95] vdd 0.63fF +C1867 la_data_in[95] vdd 0.63fF +C1868 la_oenb[94] vdd 0.63fF +C1869 la_data_out[94] vdd 0.63fF +C1870 la_data_in[94] vdd 0.63fF +C1871 la_oenb[93] vdd 0.63fF +C1872 la_data_out[93] vdd 0.63fF +C1873 la_data_in[93] vdd 0.63fF +C1874 la_oenb[92] vdd 0.63fF +C1875 la_data_out[92] vdd 0.63fF +C1876 la_data_in[92] vdd 0.63fF +C1877 la_oenb[91] vdd 0.63fF +C1878 la_data_out[91] vdd 0.63fF +C1879 la_data_in[91] vdd 0.63fF +C1880 la_oenb[90] vdd 0.63fF +C1881 la_data_out[90] vdd 0.63fF +C1882 la_data_in[90] vdd 0.63fF +C1883 la_oenb[89] vdd 0.63fF +C1884 la_data_out[89] vdd 0.63fF +C1885 la_data_in[89] vdd 0.63fF +C1886 la_oenb[88] vdd 0.63fF +C1887 la_data_out[88] vdd 0.63fF +C1888 la_data_in[88] vdd 0.63fF +C1889 la_oenb[87] vdd 0.63fF +C1890 la_data_out[87] vdd 0.63fF +C1891 la_data_in[87] vdd 0.63fF +C1892 la_oenb[86] vdd 0.63fF +C1893 la_data_out[86] vdd 0.63fF +C1894 la_data_in[86] vdd 0.63fF +C1895 la_oenb[85] vdd 0.63fF +C1896 la_data_out[85] vdd 0.63fF +C1897 la_data_in[85] vdd 0.63fF +C1898 la_oenb[84] vdd 0.63fF +C1899 la_data_out[84] vdd 0.63fF +C1900 la_data_in[84] vdd 0.63fF +C1901 la_oenb[83] vdd 0.63fF +C1902 la_data_out[83] vdd 0.63fF +C1903 la_data_in[83] vdd 0.63fF +C1904 la_oenb[82] vdd 0.63fF +C1905 la_data_out[82] vdd 0.63fF +C1906 la_data_in[82] vdd 0.63fF +C1907 la_oenb[81] vdd 0.63fF +C1908 la_data_out[81] vdd 0.63fF +C1909 la_data_in[81] vdd 0.63fF +C1910 la_oenb[80] vdd 0.63fF +C1911 la_data_out[80] vdd 0.63fF +C1912 la_data_in[80] vdd 0.63fF +C1913 la_oenb[79] vdd 0.63fF +C1914 la_data_out[79] vdd 0.63fF +C1915 la_data_in[79] vdd 0.63fF +C1916 la_oenb[78] vdd 0.63fF +C1917 la_data_out[78] vdd 0.63fF +C1918 la_data_in[78] vdd 0.63fF +C1919 la_oenb[77] vdd 0.63fF +C1920 la_data_out[77] vdd 0.63fF +C1921 la_data_in[77] vdd 0.63fF +C1922 la_oenb[76] vdd 0.63fF +C1923 la_data_out[76] vdd 0.63fF +C1924 la_data_in[76] vdd 0.63fF +C1925 la_oenb[75] vdd 0.63fF +C1926 la_data_out[75] vdd 0.63fF +C1927 la_data_in[75] vdd 0.63fF +C1928 la_oenb[74] vdd 0.63fF +C1929 la_data_out[74] vdd 0.63fF +C1930 la_data_in[74] vdd 0.63fF +C1931 la_oenb[73] vdd 0.63fF +C1932 la_data_out[73] vdd 0.63fF +C1933 la_data_in[73] vdd 0.63fF +C1934 la_oenb[72] vdd 0.63fF +C1935 la_data_out[72] vdd 0.63fF +C1936 la_data_in[72] vdd 0.63fF +C1937 la_oenb[71] vdd 0.63fF +C1938 la_data_out[71] vdd 0.63fF +C1939 la_data_in[71] vdd 0.63fF +C1940 la_oenb[70] vdd 0.63fF +C1941 la_data_out[70] vdd 0.63fF +C1942 la_data_in[70] vdd 0.63fF +C1943 la_oenb[69] vdd 0.63fF +C1944 la_data_out[69] vdd 0.63fF +C1945 la_data_in[69] vdd 0.63fF +C1946 la_oenb[68] vdd 0.63fF +C1947 la_data_out[68] vdd 0.63fF +C1948 la_data_in[68] vdd 0.63fF +C1949 la_oenb[67] vdd 0.63fF +C1950 la_data_out[67] vdd 0.63fF +C1951 la_data_in[67] vdd 0.63fF +C1952 la_oenb[66] vdd 0.63fF +C1953 la_data_out[66] vdd 0.63fF +C1954 la_data_in[66] vdd 0.63fF +C1955 la_oenb[65] vdd 0.63fF +C1956 la_data_out[65] vdd 0.63fF +C1957 la_data_in[65] vdd 0.63fF +C1958 la_oenb[64] vdd 0.63fF +C1959 la_data_out[64] vdd 0.63fF +C1960 la_data_in[64] vdd 0.63fF +C1961 la_oenb[63] vdd 0.63fF +C1962 la_data_out[63] vdd 0.63fF +C1963 la_data_in[63] vdd 0.63fF +C1964 la_oenb[62] vdd 0.63fF +C1965 la_data_out[62] vdd 0.63fF +C1966 la_data_in[62] vdd 0.63fF +C1967 la_oenb[61] vdd 0.63fF +C1968 la_data_out[61] vdd 0.63fF +C1969 la_data_in[61] vdd 0.63fF +C1970 la_oenb[60] vdd 0.63fF +C1971 la_data_out[60] vdd 0.63fF +C1972 la_data_in[60] vdd 0.63fF +C1973 la_oenb[59] vdd 0.63fF +C1974 la_data_out[59] vdd 0.63fF +C1975 la_data_in[59] vdd 0.63fF +C1976 la_oenb[58] vdd 0.63fF +C1977 la_data_out[58] vdd 0.63fF +C1978 la_data_in[58] vdd 0.63fF +C1979 la_oenb[57] vdd 0.63fF +C1980 la_data_out[57] vdd 0.63fF +C1981 la_data_in[57] vdd 0.63fF +C1982 la_oenb[56] vdd 0.63fF +C1983 la_data_out[56] vdd 0.63fF +C1984 la_data_in[56] vdd 0.63fF +C1985 la_oenb[55] vdd 0.63fF +C1986 la_data_out[55] vdd 0.63fF +C1987 la_data_in[55] vdd 0.63fF +C1988 la_oenb[54] vdd 0.63fF +C1989 la_data_out[54] vdd 0.63fF +C1990 la_data_in[54] vdd 0.63fF +C1991 la_oenb[53] vdd 0.63fF +C1992 la_data_out[53] vdd 0.63fF +C1993 la_data_in[53] vdd 0.63fF +C1994 la_oenb[52] vdd 0.63fF +C1995 la_data_out[52] vdd 0.63fF +C1996 la_data_in[52] vdd 0.63fF +C1997 la_oenb[51] vdd 0.63fF +C1998 la_data_out[51] vdd 0.63fF +C1999 la_data_in[51] vdd 0.63fF +C2000 la_oenb[50] vdd 0.63fF +C2001 la_data_out[50] vdd 0.63fF +C2002 la_data_in[50] vdd 0.63fF +C2003 la_oenb[49] vdd 0.63fF +C2004 la_data_out[49] vdd 0.63fF +C2005 la_data_in[49] vdd 0.63fF +C2006 la_oenb[48] vdd 0.63fF +C2007 la_data_out[48] vdd 0.63fF +C2008 la_data_in[48] vdd 0.63fF +C2009 la_oenb[47] vdd 0.63fF +C2010 la_data_out[47] vdd 0.63fF +C2011 la_data_in[47] vdd 0.63fF +C2012 la_oenb[46] vdd 0.63fF +C2013 la_data_out[46] vdd 0.63fF +C2014 la_data_in[46] vdd 0.63fF +C2015 la_oenb[45] vdd 0.63fF +C2016 la_data_out[45] vdd 0.63fF +C2017 la_data_in[45] vdd 0.63fF +C2018 la_oenb[44] vdd 0.63fF +C2019 la_data_out[44] vdd 0.63fF +C2020 la_data_in[44] vdd 0.63fF +C2021 la_oenb[43] vdd 0.63fF +C2022 la_data_out[43] vdd 0.63fF +C2023 la_data_in[43] vdd 0.63fF +C2024 la_oenb[42] vdd 0.63fF +C2025 la_data_out[42] vdd 0.63fF +C2026 la_data_in[42] vdd 0.63fF +C2027 la_oenb[41] vdd 0.63fF +C2028 la_data_out[41] vdd 0.63fF +C2029 la_data_in[41] vdd 0.63fF +C2030 la_oenb[40] vdd 0.63fF +C2031 la_data_out[40] vdd 0.63fF +C2032 la_data_in[40] vdd 0.63fF +C2033 la_oenb[39] vdd 0.63fF +C2034 la_data_out[39] vdd 0.63fF +C2035 la_data_in[39] vdd 0.63fF +C2036 la_oenb[38] vdd 0.63fF +C2037 la_data_out[38] vdd 0.63fF +C2038 la_data_in[38] vdd 0.63fF +C2039 la_oenb[37] vdd 0.63fF +C2040 la_data_out[37] vdd 0.63fF +C2041 la_data_in[37] vdd 0.63fF +C2042 la_oenb[36] vdd 0.63fF +C2043 la_data_out[36] vdd 0.63fF +C2044 la_data_in[36] vdd 0.63fF +C2045 la_oenb[35] vdd 0.63fF +C2046 la_data_out[35] vdd 0.63fF +C2047 la_data_in[35] vdd 0.63fF +C2048 la_oenb[34] vdd 0.63fF +C2049 la_data_out[34] vdd 0.63fF +C2050 la_data_in[34] vdd 0.63fF +C2051 la_oenb[33] vdd 0.63fF +C2052 la_data_out[33] vdd 0.63fF +C2053 la_data_in[33] vdd 0.63fF +C2054 la_oenb[32] vdd 0.63fF +C2055 la_data_out[32] vdd 0.63fF +C2056 la_data_in[32] vdd 0.63fF +C2057 la_oenb[31] vdd 0.63fF +C2058 la_data_out[31] vdd 0.63fF +C2059 la_data_in[31] vdd 0.63fF +C2060 la_oenb[30] vdd 0.63fF +C2061 la_data_out[30] vdd 0.63fF +C2062 la_data_in[30] vdd 0.63fF +C2063 la_oenb[29] vdd 0.63fF +C2064 la_data_out[29] vdd 0.63fF +C2065 la_data_in[29] vdd 0.63fF +C2066 la_oenb[28] vdd 0.63fF +C2067 la_data_out[28] vdd 0.63fF +C2068 la_data_in[28] vdd 0.63fF +C2069 la_oenb[27] vdd 0.63fF +C2070 la_data_out[27] vdd 0.63fF +C2071 la_data_in[27] vdd 0.63fF +C2072 la_oenb[26] vdd 0.63fF +C2073 la_data_out[26] vdd 0.63fF +C2074 la_data_in[26] vdd 0.63fF +C2075 la_oenb[25] vdd 0.63fF +C2076 la_data_out[25] vdd 0.63fF +C2077 la_data_in[25] vdd 0.63fF +C2078 la_oenb[24] vdd 0.63fF +C2079 la_data_out[24] vdd 0.63fF +C2080 la_data_in[24] vdd 0.63fF +C2081 la_oenb[23] vdd 0.63fF +C2082 la_data_out[23] vdd 0.63fF +C2083 la_data_in[23] vdd 0.63fF +C2084 la_oenb[22] vdd 0.63fF +C2085 la_data_out[22] vdd 0.63fF +C2086 la_data_in[22] vdd 0.63fF +C2087 la_oenb[21] vdd 0.63fF +C2088 la_data_out[21] vdd 0.63fF +C2089 la_data_in[21] vdd 0.63fF +C2090 la_oenb[20] vdd 0.63fF +C2091 la_data_out[20] vdd 0.63fF +C2092 la_data_in[20] vdd 0.63fF +C2093 la_oenb[19] vdd 0.63fF +C2094 la_data_out[19] vdd 0.63fF +C2095 la_data_in[19] vdd 0.63fF +C2096 la_oenb[18] vdd 0.63fF +C2097 la_data_out[18] vdd 0.63fF +C2098 la_data_in[18] vdd 0.63fF +C2099 la_oenb[17] vdd 0.63fF +C2100 la_data_out[17] vdd 0.63fF +C2101 la_data_in[17] vdd 0.63fF +C2102 la_oenb[16] vdd 0.63fF +C2103 la_data_out[16] vdd 0.63fF +C2104 la_data_in[16] vdd 0.63fF +C2105 la_oenb[15] vdd 0.63fF +C2106 la_data_out[15] vdd 0.63fF +C2107 la_data_in[15] vdd 0.63fF +C2108 la_oenb[14] vdd 0.63fF +C2109 la_data_out[14] vdd 0.63fF +C2110 la_data_in[14] vdd 0.63fF +C2111 la_oenb[13] vdd 0.63fF +C2112 la_data_out[13] vdd 0.63fF +C2113 la_data_in[13] vdd 0.63fF +C2114 la_oenb[12] vdd 0.63fF +C2115 la_data_out[12] vdd 0.63fF +C2116 la_data_in[12] vdd 0.63fF +C2117 la_oenb[11] vdd 0.63fF +C2118 la_data_out[11] vdd 0.63fF +C2119 la_data_in[11] vdd 0.63fF +C2120 la_oenb[10] vdd 0.63fF +C2121 la_data_out[10] vdd 0.63fF +C2122 la_data_in[10] vdd 0.63fF +C2123 la_oenb[9] vdd 0.63fF +C2124 la_data_out[9] vdd 0.63fF +C2125 la_data_in[9] vdd 0.63fF +C2126 la_oenb[8] vdd 0.63fF +C2127 la_data_out[8] vdd 0.63fF +C2128 la_data_in[8] vdd 0.63fF +C2129 la_oenb[7] vdd 0.63fF +C2130 la_data_out[7] vdd 0.63fF +C2131 la_data_in[7] vdd 0.63fF +C2132 la_oenb[6] vdd 0.63fF +C2133 la_data_out[6] vdd 0.63fF +C2134 la_data_in[6] vdd 0.63fF +C2135 la_oenb[5] vdd 0.63fF +C2136 la_data_out[5] vdd 0.63fF +C2137 la_data_in[5] vdd 0.63fF +C2138 la_oenb[4] vdd 0.63fF +C2139 la_data_out[4] vdd 0.63fF +C2140 la_data_in[4] vdd 0.63fF +C2141 la_oenb[3] vdd 0.63fF +C2142 la_data_out[3] vdd 0.63fF +C2143 la_data_in[3] vdd 0.63fF +C2144 la_oenb[2] vdd 0.63fF +C2145 la_data_out[2] vdd 0.63fF +C2146 la_data_in[2] vdd 0.63fF +C2147 la_oenb[1] vdd 0.63fF +C2148 la_data_out[1] vdd 0.63fF +C2149 la_data_in[1] vdd 0.63fF +C2150 la_oenb[0] vdd 0.63fF +C2151 la_data_out[0] vdd 0.63fF +C2152 la_data_in[0] vdd 0.63fF +C2153 wbs_dat_o[31] vdd 0.63fF +C2154 wbs_dat_i[31] vdd 0.63fF +C2155 wbs_adr_i[31] vdd 0.63fF +C2156 wbs_dat_o[30] vdd 0.63fF +C2157 wbs_dat_i[30] vdd 0.63fF +C2158 wbs_adr_i[30] vdd 0.63fF +C2159 wbs_dat_o[29] vdd 0.63fF +C2160 wbs_dat_i[29] vdd 0.63fF +C2161 wbs_adr_i[29] vdd 0.63fF +C2162 wbs_dat_o[28] vdd 0.63fF +C2163 wbs_dat_i[28] vdd 0.63fF +C2164 wbs_adr_i[28] vdd 0.63fF +C2165 wbs_dat_o[27] vdd 0.63fF +C2166 wbs_dat_i[27] vdd 0.63fF +C2167 wbs_adr_i[27] vdd 0.63fF +C2168 wbs_dat_o[26] vdd 0.63fF +C2169 wbs_dat_i[26] vdd 0.63fF +C2170 wbs_adr_i[26] vdd 0.63fF +C2171 wbs_dat_o[25] vdd 0.63fF +C2172 wbs_dat_i[25] vdd 0.63fF +C2173 wbs_adr_i[25] vdd 0.63fF +C2174 wbs_dat_o[24] vdd 0.63fF +C2175 wbs_dat_i[24] vdd 0.63fF +C2176 wbs_adr_i[24] vdd 0.63fF +C2177 wbs_dat_o[23] vdd 0.63fF +C2178 wbs_dat_i[23] vdd 0.63fF +C2179 wbs_adr_i[23] vdd 0.63fF +C2180 wbs_dat_o[22] vdd 0.63fF +C2181 wbs_dat_i[22] vdd 0.63fF +C2182 wbs_adr_i[22] vdd 0.63fF +C2183 wbs_dat_o[21] vdd 0.63fF +C2184 wbs_dat_i[21] vdd 0.63fF +C2185 wbs_adr_i[21] vdd 0.63fF +C2186 wbs_dat_o[20] vdd 0.63fF +C2187 wbs_dat_i[20] vdd 0.63fF +C2188 wbs_adr_i[20] vdd 0.63fF +C2189 wbs_dat_o[19] vdd 0.63fF +C2190 wbs_dat_i[19] vdd 0.63fF +C2191 wbs_adr_i[19] vdd 0.63fF +C2192 wbs_dat_o[18] vdd 0.63fF +C2193 wbs_dat_i[18] vdd 0.63fF +C2194 wbs_adr_i[18] vdd 0.63fF +C2195 wbs_dat_o[17] vdd 0.63fF +C2196 wbs_dat_i[17] vdd 0.63fF +C2197 wbs_adr_i[17] vdd 0.63fF +C2198 wbs_dat_o[16] vdd 0.63fF +C2199 wbs_dat_i[16] vdd 0.63fF +C2200 wbs_adr_i[16] vdd 0.63fF +C2201 wbs_dat_o[15] vdd 0.63fF +C2202 wbs_dat_i[15] vdd 0.63fF +C2203 wbs_adr_i[15] vdd 0.63fF +C2204 wbs_dat_o[14] vdd 0.63fF +C2205 wbs_dat_i[14] vdd 0.63fF +C2206 wbs_adr_i[14] vdd 0.63fF +C2207 wbs_dat_o[13] vdd 0.63fF +C2208 wbs_dat_i[13] vdd 0.63fF +C2209 wbs_adr_i[13] vdd 0.63fF +C2210 wbs_dat_o[12] vdd 0.63fF +C2211 wbs_dat_i[12] vdd 0.63fF +C2212 wbs_adr_i[12] vdd 0.63fF +C2213 wbs_dat_o[11] vdd 0.63fF +C2214 wbs_dat_i[11] vdd 0.63fF +C2215 wbs_adr_i[11] vdd 0.63fF +C2216 wbs_dat_o[10] vdd 0.63fF +C2217 wbs_dat_i[10] vdd 0.63fF +C2218 wbs_adr_i[10] vdd 0.63fF +C2219 wbs_dat_o[9] vdd 0.63fF +C2220 wbs_dat_i[9] vdd 0.63fF +C2221 wbs_adr_i[9] vdd 0.63fF +C2222 wbs_dat_o[8] vdd 0.63fF +C2223 wbs_dat_i[8] vdd 0.63fF +C2224 wbs_adr_i[8] vdd 0.63fF +C2225 wbs_dat_o[7] vdd 0.63fF +C2226 wbs_dat_i[7] vdd 0.63fF +C2227 wbs_adr_i[7] vdd 0.63fF +C2228 wbs_dat_o[6] vdd 0.63fF +C2229 wbs_dat_i[6] vdd 0.63fF +C2230 wbs_adr_i[6] vdd 0.63fF +C2231 wbs_dat_o[5] vdd 0.63fF +C2232 wbs_dat_i[5] vdd 0.63fF +C2233 wbs_adr_i[5] vdd 0.63fF +C2234 wbs_dat_o[4] vdd 0.63fF +C2235 wbs_dat_i[4] vdd 0.63fF +C2236 wbs_adr_i[4] vdd 0.63fF +C2237 wbs_sel_i[3] vdd 0.63fF +C2238 wbs_dat_o[3] vdd 0.63fF +C2239 wbs_dat_i[3] vdd 0.63fF +C2240 wbs_adr_i[3] vdd 0.63fF +C2241 wbs_sel_i[2] vdd 0.63fF +C2242 wbs_dat_o[2] vdd 0.63fF +C2243 wbs_dat_i[2] vdd 0.63fF +C2244 wbs_adr_i[2] vdd 0.63fF +C2245 wbs_sel_i[1] vdd 0.63fF +C2246 wbs_dat_o[1] vdd 0.63fF +C2247 wbs_dat_i[1] vdd 0.63fF +C2248 wbs_adr_i[1] vdd 0.63fF +C2249 wbs_sel_i[0] vdd 0.63fF +C2250 wbs_dat_o[0] vdd 0.63fF +C2251 wbs_dat_i[0] vdd 0.63fF +C2252 wbs_adr_i[0] vdd 0.63fF +C2253 wbs_we_i vdd 0.63fF +C2254 wbs_stb_i vdd 0.63fF +C2255 wbs_cyc_i vdd 0.63fF +C2256 wbs_ack_o vdd 0.63fF +C2257 wb_rst_i vdd 0.63fF +C2258 wb_clk_i vdd 0.63fF +C2259 m2_494098_659718# vdd 0.80fF **FLOATING +C2260 pll_full_0/divider_0/and_0/Z1 vdd 0.33fF +C2261 pll_full_0/divider_0/and_0/B vdd 1.79fF +C2262 pll_full_0/divider_0/and_0/A vdd 1.66fF +C2263 pll_full_0/divider_0/and_0/out1 vdd 2.71fF +C2264 pll_full_0/divider_0/tspc_2/Z4 vdd 0.42fF +C2265 pll_full_0/divbuf_0/IN vdd 6.23fF +C2266 pll_full_0/divider_0/tspc_2/Z3 vdd 2.00fF +C2267 pll_full_0/divider_0/tspc_2/Z2 vdd 1.29fF +C2268 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF +C2269 pll_full_0/divider_0/nor_0/B vdd 5.25fF +C2270 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2271 pll_full_0/divider_0/tspc_1/Z4 vdd 0.42fF +C2272 pll_full_0/divider_0/tspc_1/Q vdd 2.79fF +C2273 pll_full_0/divider_0/tspc_1/Z3 vdd 2.00fF +C2274 pll_full_0/divider_0/tspc_1/Z2 vdd 1.29fF +C2275 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF +C2276 pll_full_0/divider_0/nor_1/B vdd 5.95fF +C2277 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2278 pll_full_0/divider_0/tspc_0/Z4 vdd 0.42fF +C2279 pll_full_0/divider_0/tspc_0/Q vdd 2.81fF +C2280 pll_full_0/divider_0/tspc_0/Z3 vdd 2.00fF +C2281 pll_full_0/divider_0/tspc_0/Z2 vdd 1.30fF +C2282 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF +C2283 pll_full_0/divider_0/nor_1/A vdd 6.02fF +C2284 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2285 pll_full_0/divider_0/clk vdd 31.77fF +C2286 pll_full_0/divider_0/prescaler_0/Out vdd 4.13fF +C2287 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.20fF +C2288 gnd vdd 91.98fF +C2289 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.59fF +C2290 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.30fF +C2291 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 2.78fF +C2292 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.20fF +C2293 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.07fF +C2294 pll_full_0/divider_0/and_0/OUT vdd 5.35fF +C2295 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2296 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2297 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2298 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2299 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2300 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2301 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2302 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2303 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2304 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2305 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2306 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2307 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2308 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2309 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2310 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2311 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2312 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2313 pll_full_0/divider_0/nor_1/Z1 vdd 1.33fF +C2314 pll_full_0/divider_0/nor_0/Z1 vdd 1.33fF +C2315 pll_full_0/divbuf_1/OUT vdd 363.82fF +C2316 pll_full_0/divbuf_1/OUT5 vdd 350.37fF +C2317 pll_full_0/divbuf_1/OUT4 vdd 133.72fF +C2318 pll_full_0/divbuf_1/OUT3 vdd 34.03fF +C2319 pll_full_0/divbuf_1/OUT2 vdd 8.71fF +C2320 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C2321 pll_full_0/divbuf_0/OUT5 vdd 350.37fF +C2322 pll_full_0/divbuf_0/OUT4 vdd 133.72fF +C2323 pll_full_0/divbuf_0/OUT3 vdd 34.03fF +C2324 pll_full_0/divbuf_0/OUT2 vdd 8.71fF +C2325 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C2326 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF +C2327 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C2328 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C2329 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C2330 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C2331 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C2332 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C2333 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C2334 pll_full_0/ro_complete_0/a0 vdd 7.88fF +C2335 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C2336 pll_full_0/ro_complete_0/a1 vdd 5.39fF +C2337 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C2338 pll_full_0/ro_complete_0/a3 vdd 6.85fF +C2339 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C2340 pll_full_0/ro_complete_0/a2 vdd 5.48fF +C2341 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C2342 pll_full_0/ro_complete_0/a4 vdd 5.36fF +C2343 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C2344 pll_full_0/ro_complete_0/a5 vdd 5.19fF +C2345 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF +C2346 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C2347 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C2348 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C2349 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C2350 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C2351 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C2352 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C2353 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING +C2354 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING +C2355 pll_full_0/cp_0/down vdd 1.54fF +C2356 pll_full_0/cp_0/upbar vdd 1.79fF +C2357 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C2358 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C2359 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING +C2360 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING +C2361 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING +C2362 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING +C2363 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF +C2364 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF +C2365 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF +C2366 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF +C2367 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF +C2368 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF +C2369 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF +C2370 pll_full_0/pd_0/UP vdd 6.61fF +C2371 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C2372 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF +C2373 pll_full_0/pd_0/REF vdd 6.44fF +C2374 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF +C2375 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF +C2376 pll_full_0/pd_0/R vdd 3.05fF +C2377 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF +C2378 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF +C2379 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF +C2380 pll_full_0/pd_0/DOWN vdd 7.24fF +C2381 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C2382 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF +C2383 pll_full_0/pd_0/DIV vdd 371.86fF +C2384 divider_2/and_0/Z1 vdd 0.33fF +C2385 divider_2/and_0/B vdd 1.79fF +C2386 divider_2/and_0/A vdd 1.66fF +C2387 divider_2/and_0/out1 vdd 2.71fF +C2388 divider_2/tspc_2/Z4 vdd 0.42fF +C2389 divider_2/Out vdd 1.31fF +C2390 divider_2/tspc_2/Z3 vdd 2.00fF +C2391 divider_2/tspc_2/Z2 vdd 1.29fF +C2392 divider_2/tspc_2/Z1 vdd 0.99fF +C2393 divider_2/nor_0/B vdd 5.25fF +C2394 divider_2/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2395 divider_2/tspc_1/Z4 vdd 0.42fF +C2396 divider_2/tspc_1/Q vdd 2.79fF +C2397 divider_2/tspc_1/Z3 vdd 2.00fF +C2398 divider_2/tspc_1/Z2 vdd 1.29fF +C2399 divider_2/tspc_1/Z1 vdd 0.99fF +C2400 divider_2/nor_1/B vdd 5.95fF +C2401 divider_2/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2402 divider_2/tspc_0/Z4 vdd 0.42fF +C2403 divider_2/tspc_0/Q vdd 2.81fF +C2404 divider_2/tspc_0/Z3 vdd 2.00fF +C2405 divider_2/tspc_0/Z2 vdd 1.30fF +C2406 divider_2/tspc_0/Z1 vdd 0.99fF +C2407 divider_2/nor_1/A vdd 6.02fF +C2408 divider_2/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2409 divider_2/clk vdd 5.56fF +C2410 divider_2/prescaler_0/Out vdd 4.13fF +C2411 divider_2/prescaler_0/nand_1/z1 vdd 0.20fF +C2412 divider_2/prescaler_0/tspc_2/D vdd 2.59fF +C2413 divider_2/prescaler_0/tspc_0/Q vdd 3.30fF +C2414 divider_2/prescaler_0/tspc_1/Q vdd 2.78fF +C2415 divider_2/prescaler_0/nand_0/z1 vdd 0.20fF +C2416 divider_2/prescaler_0/tspc_0/D vdd 3.07fF +C2417 divider_2/and_0/OUT vdd 5.35fF +C2418 divider_2/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2419 divider_2/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2420 divider_2/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2421 divider_2/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2422 divider_2/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2423 divider_2/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2424 divider_2/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2425 divider_2/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2426 divider_2/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2427 divider_2/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2428 divider_2/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2429 divider_2/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2430 divider_2/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2431 divider_2/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2432 divider_2/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2433 divider_2/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2434 divider_2/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2435 divider_2/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2436 divider_2/nor_1/Z1 vdd 1.33fF +C2437 divider_2/nor_0/Z1 vdd 1.33fF +C2438 divider_2/mc2 vdd 3.93fF +C2439 divider_1/and_0/Z1 vdd 0.33fF +C2440 divider_1/and_0/B vdd 1.79fF +C2441 divider_1/and_0/A vdd 1.66fF +C2442 divider_1/and_0/out1 vdd 2.71fF +C2443 divider_1/tspc_2/Z4 vdd 0.42fF +C2444 divider_1/Out vdd 1.31fF +C2445 divider_1/tspc_2/Z3 vdd 2.00fF +C2446 divider_1/tspc_2/Z2 vdd 1.29fF +C2447 divider_1/tspc_2/Z1 vdd 0.99fF +C2448 divider_1/nor_0/B vdd 5.25fF +C2449 divider_1/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2450 divider_1/tspc_1/Z4 vdd 0.42fF +C2451 divider_1/tspc_1/Q vdd 2.79fF +C2452 divider_1/tspc_1/Z3 vdd 2.00fF +C2453 divider_1/tspc_1/Z2 vdd 1.29fF +C2454 divider_1/tspc_1/Z1 vdd 0.99fF +C2455 divider_1/nor_1/B vdd 5.95fF +C2456 divider_1/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2457 divider_1/tspc_0/Z4 vdd 0.42fF +C2458 divider_1/tspc_0/Q vdd 2.81fF +C2459 divider_1/tspc_0/Z3 vdd 2.00fF +C2460 divider_1/tspc_0/Z2 vdd 1.30fF +C2461 divider_1/tspc_0/Z1 vdd 0.99fF +C2462 divider_1/nor_1/A vdd 6.02fF +C2463 divider_1/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2464 divider_1/clk vdd 5.56fF +C2465 divider_1/prescaler_0/Out vdd 4.13fF +C2466 divider_1/prescaler_0/nand_1/z1 vdd 0.20fF +C2467 divider_1/prescaler_0/tspc_2/D vdd 2.59fF +C2468 divider_1/prescaler_0/tspc_0/Q vdd 3.30fF +C2469 divider_1/prescaler_0/tspc_1/Q vdd 2.78fF +C2470 divider_1/prescaler_0/nand_0/z1 vdd 0.20fF +C2471 divider_1/prescaler_0/tspc_0/D vdd 3.07fF +C2472 divider_1/and_0/OUT vdd 5.35fF +C2473 divider_1/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2474 divider_1/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2475 divider_1/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2476 divider_1/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2477 divider_1/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2478 divider_1/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2479 divider_1/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2480 divider_1/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2481 divider_1/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2482 divider_1/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2483 divider_1/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2484 divider_1/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2485 divider_1/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2486 divider_1/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2487 divider_1/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2488 divider_1/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2489 divider_1/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2490 divider_1/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2491 divider_1/nor_1/Z1 vdd 1.33fF +C2492 divider_1/nor_0/Z1 vdd 1.33fF +C2493 divider_1/mc2 vdd 3.93fF +C2494 divider_0/and_0/Z1 vdd 0.33fF +C2495 divider_0/and_0/B vdd 1.79fF +C2496 divider_0/and_0/A vdd 1.66fF +C2497 divider_0/and_0/out1 vdd 2.71fF +C2498 divider_0/tspc_2/Z4 vdd 0.42fF +C2499 divider_0/Out vdd 1.31fF +C2500 divider_0/tspc_2/Z3 vdd 2.00fF +C2501 divider_0/tspc_2/Z2 vdd 1.29fF +C2502 divider_0/tspc_2/Z1 vdd 0.99fF +C2503 divider_0/nor_0/B vdd 5.25fF +C2504 divider_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2505 divider_0/tspc_1/Z4 vdd 0.42fF +C2506 divider_0/tspc_1/Q vdd 2.79fF +C2507 divider_0/tspc_1/Z3 vdd 2.00fF +C2508 divider_0/tspc_1/Z2 vdd 1.29fF +C2509 divider_0/tspc_1/Z1 vdd 0.99fF +C2510 divider_0/nor_1/B vdd 5.95fF +C2511 divider_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2512 divider_0/tspc_0/Z4 vdd 0.42fF +C2513 divider_0/tspc_0/Q vdd 2.81fF +C2514 divider_0/tspc_0/Z3 vdd 2.00fF +C2515 divider_0/tspc_0/Z2 vdd 1.30fF +C2516 divider_0/tspc_0/Z1 vdd 0.99fF +C2517 divider_0/nor_1/A vdd 6.02fF +C2518 divider_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2519 divider_0/clk vdd 5.56fF +C2520 divider_0/prescaler_0/Out vdd 4.13fF +C2521 divider_0/prescaler_0/nand_1/z1 vdd 0.20fF +C2522 divider_0/prescaler_0/tspc_2/D vdd 2.59fF +C2523 divider_0/prescaler_0/tspc_0/Q vdd 3.30fF +C2524 divider_0/prescaler_0/tspc_1/Q vdd 2.78fF +C2525 divider_0/prescaler_0/nand_0/z1 vdd 0.20fF +C2526 divider_0/prescaler_0/tspc_0/D vdd 3.07fF +C2527 divider_0/and_0/OUT vdd 5.35fF +C2528 divider_0/prescaler_0/tspc_2/Z4 vdd 0.42fF +C2529 divider_0/prescaler_0/tspc_2/Z3 vdd 2.00fF +C2530 divider_0/prescaler_0/tspc_2/Z2 vdd 1.30fF +C2531 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C2532 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 0.53fF **FLOATING +C2533 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 1.89fF **FLOATING +C2534 divider_0/prescaler_0/tspc_1/Z4 vdd 0.42fF +C2535 divider_0/prescaler_0/tspc_1/Z3 vdd 2.00fF +C2536 divider_0/prescaler_0/tspc_1/Z2 vdd 1.31fF +C2537 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C2538 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 0.53fF **FLOATING +C2539 divider_0/prescaler_0/m1_2700_2190# vdd 3.99fF **FLOATING +C2540 divider_0/prescaler_0/tspc_0/Z4 vdd 0.42fF +C2541 divider_0/prescaler_0/tspc_0/Z3 vdd 2.00fF +C2542 divider_0/prescaler_0/tspc_0/Z2 vdd 1.30fF +C2543 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C2544 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 0.53fF **FLOATING +C2545 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 1.89fF **FLOATING +C2546 divider_0/nor_1/Z1 vdd 1.33fF +C2547 divider_0/nor_0/Z1 vdd 1.33fF +C2548 divider_0/mc2 vdd 3.93fF +C2549 divbuf_7/OUT vdd 363.82fF +C2550 divbuf_7/OUT5 vdd 350.37fF +C2551 divbuf_7/OUT4 vdd 133.72fF +C2552 divbuf_7/OUT3 vdd 34.03fF +C2553 divbuf_7/OUT2 vdd 8.71fF +C2554 divbuf_7/IN vdd 0.89fF +C2555 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING +C2556 divbuf_6/OUT vdd 363.82fF +C2557 divbuf_6/OUT5 vdd 350.37fF +C2558 divbuf_6/OUT4 vdd 133.72fF +C2559 divbuf_6/OUT3 vdd 34.03fF +C2560 divbuf_6/OUT2 vdd 8.71fF +C2561 divbuf_6/IN vdd 0.89fF +C2562 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING +C2563 divbuf_5/OUT vdd 363.82fF +C2564 divbuf_5/OUT5 vdd 350.37fF +C2565 divbuf_5/OUT4 vdd 133.72fF +C2566 divbuf_5/OUT3 vdd 34.03fF +C2567 divbuf_5/OUT2 vdd 8.71fF +C2568 divbuf_5/IN vdd 0.89fF +C2569 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING +C2570 divbuf_4/OUT vdd 363.82fF +C2571 divbuf_4/OUT5 vdd 350.37fF +C2572 divbuf_4/OUT4 vdd 133.72fF +C2573 divbuf_4/OUT3 vdd 34.03fF +C2574 divbuf_4/OUT2 vdd 8.71fF +C2575 divbuf_4/IN vdd 0.89fF +C2576 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING +C2577 divbuf_3/OUT vdd 363.82fF +C2578 divbuf_3/OUT5 vdd 350.37fF +C2579 divbuf_3/OUT4 vdd 133.72fF +C2580 divbuf_3/OUT3 vdd 34.03fF +C2581 divbuf_3/OUT2 vdd 8.71fF +C2582 divbuf_3/IN vdd 0.89fF +C2583 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING +C2584 divbuf_2/OUT vdd 363.82fF +C2585 divbuf_2/OUT5 vdd 350.37fF +C2586 divbuf_2/OUT4 vdd 133.72fF +C2587 divbuf_2/OUT3 vdd 34.03fF +C2588 divbuf_2/OUT2 vdd 8.71fF +C2589 divbuf_2/IN vdd 0.89fF +C2590 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING +C2591 divbuf_1/OUT vdd 363.82fF +C2592 divbuf_1/OUT5 vdd 350.37fF +C2593 divbuf_1/OUT4 vdd 133.72fF +C2594 divbuf_1/OUT3 vdd 34.03fF +C2595 divbuf_1/OUT2 vdd 8.71fF +C2596 divbuf_1/IN vdd 0.89fF +C2597 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C2598 ro_complete_1/cbank_2/v vdd 17.84fF +C2599 ro_complete_1/cbank_2/switch_5/vin vdd 0.78fF +C2600 ro_complete_1/cbank_2/switch_4/vin vdd 1.50fF +C2601 ro_complete_1/cbank_2/switch_2/vin vdd 1.30fF +C2602 ro_complete_1/cbank_2/switch_3/vin vdd 0.56fF +C2603 ro_complete_1/cbank_2/switch_1/vin vdd 1.14fF +C2604 ro_complete_1/cbank_2/switch_0/vin vdd 1.02fF +C2605 ro_complete_1/cbank_1/v vdd 16.34fF +C2606 ro_complete_1/cbank_1/switch_5/vin vdd 0.78fF +C2607 ro_complete_1/a0 vdd 7.88fF +C2608 ro_complete_1/cbank_1/switch_4/vin vdd 1.50fF +C2609 ro_complete_1/a1 vdd 5.39fF +C2610 ro_complete_1/cbank_1/switch_2/vin vdd 1.30fF +C2611 ro_complete_1/a3 vdd 6.85fF +C2612 ro_complete_1/cbank_1/switch_3/vin vdd 0.56fF +C2613 ro_complete_1/a2 vdd 5.48fF +C2614 ro_complete_1/cbank_1/switch_1/vin vdd 1.14fF +C2615 ro_complete_1/a4 vdd 5.36fF +C2616 ro_complete_1/cbank_1/switch_0/vin vdd 1.02fF +C2617 ro_complete_1/a5 vdd 5.19fF +C2618 ro_complete_1/cbank_0/v vdd 14.98fF +C2619 ro_complete_1/cbank_0/switch_5/vin vdd 0.78fF +C2620 ro_complete_1/cbank_0/switch_4/vin vdd 1.50fF +C2621 ro_complete_1/cbank_0/switch_2/vin vdd 1.30fF +C2622 ro_complete_1/cbank_0/switch_3/vin vdd 0.56fF +C2623 ro_complete_1/cbank_0/switch_1/vin vdd 1.14fF +C2624 ro_complete_1/cbank_0/switch_0/vin vdd 1.02fF +C2625 ro_complete_1/ro_var_extend_0/vcont vdd 0.27fF +C2626 divbuf_0/OUT vdd 363.82fF +C2627 divbuf_0/OUT5 vdd 350.37fF +C2628 divbuf_0/OUT4 vdd 133.72fF +C2629 divbuf_0/OUT3 vdd 34.03fF +C2630 divbuf_0/OUT2 vdd 8.71fF +C2631 divbuf_0/IN vdd 0.89fF +C2632 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C2633 ro_complete_0/cbank_2/v vdd 17.84fF +C2634 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C2635 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C2636 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C2637 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C2638 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C2639 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C2640 ro_complete_0/cbank_1/v vdd 16.38fF +C2641 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C2642 ro_complete_0/a0 vdd 7.88fF +C2643 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C2644 ro_complete_0/a1 vdd 5.39fF +C2645 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C2646 ro_complete_0/a3 vdd 6.85fF +C2647 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C2648 ro_complete_0/a2 vdd 5.48fF +C2649 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C2650 ro_complete_0/a4 vdd 5.36fF +C2651 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C2652 ro_complete_0/a5 vdd 5.19fF +C2653 ro_complete_0/cbank_0/v vdd 14.98fF +C2654 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C2655 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C2656 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C2657 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C2658 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C2659 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C2660 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C2661 filter_0/v vdd 85.69fF +C2662 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING +C2663 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING +C2664 cp_0/down vdd 1.54fF +C2665 cp_0/vbias vdd 2.41fF +C2666 cp_0/out vdd 5.26fF +C2667 cp_0/upbar vdd 1.50fF +C2668 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C2669 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C2670 cp_0/a_7110_0# vdd 0.17fF **FLOATING +C2671 cp_0/a_6370_0# vdd 0.40fF **FLOATING +C2672 cp_0/a_3060_0# vdd 1.65fF **FLOATING +C2673 cp_0/a_1710_0# vdd 5.76fF **FLOATING +C2674 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING +C2675 cp_0/a_10_n50# vdd 2.96fF **FLOATING +C2676 pd_1/and_pd_0/Z1 vdd 0.39fF +C2677 pd_1/and_pd_0/Out1 vdd 2.22fF +C2678 pd_1/tspc_r_1/z5 vdd 1.10fF +C2679 pd_1/tspc_r_1/Z4 vdd 1.07fF +C2680 pd_1/tspc_r_1/Qbar vdd 0.88fF +C2681 pd_1/tspc_r_1/Z2 vdd 1.22fF +C2682 pd_1/tspc_r_1/Z1 vdd 0.67fF +C2683 pd_1/UP vdd 2.21fF +C2684 pd_1/tspc_r_1/Qbar1 vdd 1.34fF +C2685 pd_1/tspc_r_1/Z3 vdd 2.12fF +C2686 pd_1/REF vdd 1.80fF +C2687 pd_1/tspc_r_0/z5 vdd 1.10fF +C2688 pd_1/tspc_r_0/Z4 vdd 1.07fF +C2689 pd_1/R vdd 3.05fF +C2690 pd_1/tspc_r_0/Qbar vdd 0.79fF +C2691 pd_1/tspc_r_0/Z2 vdd 1.22fF +C2692 pd_1/tspc_r_0/Z1 vdd 0.67fF +C2693 pd_1/DOWN vdd 3.08fF +C2694 pd_1/tspc_r_0/Qbar1 vdd 1.34fF +C2695 pd_1/tspc_r_0/Z3 vdd 2.12fF +C2696 pd_1/DIV vdd 1.82fF +C2697 pd_0/and_pd_0/Z1 vdd 0.39fF +C2698 pd_0/and_pd_0/Out1 vdd 2.22fF +C2699 pd_0/tspc_r_1/z5 vdd 1.10fF +C2700 pd_0/tspc_r_1/Z4 vdd 1.07fF +C2701 pd_0/tspc_r_1/Qbar vdd 0.88fF +C2702 pd_0/tspc_r_1/Z2 vdd 1.22fF +C2703 pd_0/tspc_r_1/Z1 vdd 0.67fF +C2704 pd_0/UP vdd 2.21fF +C2705 pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C2706 pd_0/tspc_r_1/Z3 vdd 2.12fF +C2707 pd_0/REF vdd 1.80fF +C2708 pd_0/tspc_r_0/z5 vdd 1.10fF +C2709 pd_0/tspc_r_0/Z4 vdd 1.07fF +C2710 pd_0/R vdd 3.05fF +C2711 pd_0/tspc_r_0/Qbar vdd 0.79fF +C2712 pd_0/tspc_r_0/Z2 vdd 1.22fF +C2713 pd_0/tspc_r_0/Z1 vdd 0.67fF +C2714 pd_0/DOWN vdd 3.08fF +C2715 pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C2716 pd_0/tspc_r_0/Z3 vdd 2.12fF +C2717 pd_0/DIV vdd 1.82fF .ends