pin extension
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index 73e05fd..072b453 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 2cd68ab..18b6423 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1642812614 +timestamp 1642892036 << metal2 >> rect 262 -400 318 240 rect 853 -400 909 240 @@ -516,7 +516,21 @@ rect 232697 351150 235197 352400 rect 255297 351170 257697 352400 rect 260297 351170 262697 352400 +rect 8376 349233 10412 351150 +rect 34331 349233 36367 351150 +rect 60339 349338 62375 351150 +rect 82963 349244 84999 351150 +rect 88168 349208 90204 351150 +rect 108814 349155 110850 351150 +rect 114054 349155 116090 351150 +rect 159668 349191 161704 351150 +rect 164874 349155 166910 351150 +rect 206890 349311 208926 351150 +rect 232866 349389 234902 351150 +rect 255440 349320 257476 351170 +rect 260451 349303 262487 351170 rect 283297 351150 285797 352400 +rect 283588 349206 285624 351150 rect -400 340121 850 342621 rect 291150 338992 292400 341492 rect -400 321921 830 324321 @@ -688,6 +702,12 @@ rect 113797 351150 116297 352400 rect 159497 351150 161997 352400 rect 164647 351150 167147 352400 +rect 82963 349244 84999 351150 +rect 88168 349208 90204 351150 +rect 108814 349155 110850 351150 +rect 114054 349155 116090 351150 +rect 159668 349191 161704 351150 +rect 164874 349155 166910 351150 << metal5 >> rect 82797 351150 85297 352400 rect 87947 351150 90447 352400 @@ -695,6 +715,12 @@ rect 113797 351150 116297 352400 rect 159497 351150 161997 352400 rect 164647 351150 167147 352400 +rect 82963 349244 84999 351150 +rect 88168 349208 90204 351150 +rect 108814 349155 110850 351150 +rect 114054 349155 116090 351150 +rect 159668 349191 161704 351150 +rect 164874 349155 166910 351150 << comment >> rect -50 352000 292050 352050 rect -50 0 0 352000 @@ -708,30 +734,26 @@ timestamp 1642811007 transform 1 0 183060 0 1 147974 box -5415 -2690 26430 12835 -use ro_div_new ro_div_new_0 -timestamp 1642812614 -transform 1 0 167071 0 1 205717 -box 0 -19 9875 6770 use pd pd_0 timestamp 1642811703 transform 1 0 103126 0 1 258815 box -215 -855 1685 810 -use filter filter_0 -timestamp 1640983258 -transform 1 0 77692 0 1 317254 -box -1800 -11005 6240 390 use divider divider_0 timestamp 1642812614 transform 1 0 166638 0 1 265093 box -490 -235 4690 2150 -use divbuf divbuf_6 -timestamp 1641017053 -transform 1 0 245858 0 1 309157 -box -460 -1085 31200 495 use divbuf divbuf_7 timestamp 1641017053 transform 1 0 245779 0 1 306691 box -460 -1085 31200 495 +use filter filter_0 +timestamp 1640983258 +transform 1 0 77692 0 1 317254 +box -1800 -11005 6240 390 +use divbuf divbuf_6 +timestamp 1641017053 +transform 1 0 245858 0 1 309157 +box -460 -1085 31200 495 use divbuf divbuf_5 timestamp 1641017053 transform 1 0 245938 0 1 311543
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 44f1e20..561133c 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1143 +106,857 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF -C1 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C2 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF -C3 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C4 ro_div_new_0/divider_0/tspc_0/Z2 ro_div_new_0/divider_0/tspc_0/Z4 0.36fF -C5 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF -C6 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF -C7 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF -C8 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C9 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF -C10 divider_0/mc2 divider_0/nor_1/B 0.06fF -C11 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF -C12 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF -C13 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C14 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_1/Z4 0.00fF -C15 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Z2 0.01fF -C16 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C17 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF -C18 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF -C19 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF -C20 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF -C21 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF -C22 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF -C23 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF -C24 pd_0/REF pd_0/tspc_r_1/z5 0.04fF -C25 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF -C26 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF -C27 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C28 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/nor_0/B 0.06fF -C29 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF -C30 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C31 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF -C32 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C33 divbuf_7/OUT4 divbuf_7/OUT 1.11fF -C34 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin 0.09fF -C35 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF -C36 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF -C37 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_0/Q 0.45fF -C38 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.21fF -C39 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/and_0/A 0.01fF -C40 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF -C41 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF -C42 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF -C43 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF -C44 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF -C45 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF -C46 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF -C47 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/a3 0.13fF -C48 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF -C49 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF -C50 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF -C51 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/A 0.16fF -C52 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C53 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C54 ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF -C55 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF -C56 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C57 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z4 0.12fF -C58 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z2 1.07fF -C59 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z3 0.38fF -C60 divbuf_2/OUT5 divbuf_2/OUT 43.38fF -C61 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF -C62 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C63 divbuf_5/OUT5 divbuf_5/OUT 43.38fF -C64 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF -C65 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF -C66 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z4 0.04fF -C67 io_clamp_low[0] io_analog[4] 0.53fF -C68 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C69 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/divider_0/clk 1.27fF -C70 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF -C71 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C72 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF -C73 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF -C74 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF -C75 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF -C76 cp_0/out cp_0/a_1710_n2840# 0.61fF -C77 ro_div_new_0/divider_0/tspc_0/Z1 ro_div_new_0/divider_0/nor_1/A 0.03fF -C78 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Z1 0.06fF -C79 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF -C80 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF -C81 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT5 0.02fF -C82 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/nor_0/B 0.22fF -C83 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C84 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C85 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/Out 0.08fF -C86 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C87 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF -C88 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF -C89 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C90 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF -C91 divider_0/mc2 divider_0/and_0/A 0.16fF -C92 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C93 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/divider_0/clk 0.10fF -C94 divider_0/and_0/out1 divider_0/and_0/B 0.18fF -C95 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF -C96 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/out1 0.31fF -C97 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF -C98 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF -C99 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF -C100 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C101 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF -C102 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C103 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT2 0.42fF -C104 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF -C105 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF -C106 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF -C107 filter_0/a_4216_n2998# filter_0/v 0.31fF -C108 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/Z3 0.16fF -C109 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C110 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C111 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/and_0/B 0.29fF -C112 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF -C113 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF -C114 divbuf_6/IN divbuf_6/OUT5 0.00fF -C115 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF -C116 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF -C117 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C118 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF -C119 pd_0/R pd_0/and_pd_0/Z1 0.02fF -C120 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF -C121 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF -C122 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF -C123 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF -C124 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF -C125 divbuf_1/IN divbuf_1/OUT5 0.00fF -C126 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF -C127 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF -C128 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF -C129 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF -C130 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF -C131 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF -C132 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C133 divider_0/nor_1/B divider_0/nor_1/A 1.21fF -C134 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF -C135 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF -C136 ro_div_new_0/divider_0/tspc_0/Z1 ro_div_new_0/divider_0/tspc_0/Z2 1.07fF -C137 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF -C138 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF -C139 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.04fF -C140 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF -C141 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF -C142 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF -C143 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF -C144 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF -C145 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF -C146 pd_0/DIV pd_0/R 0.51fF -C147 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C148 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF -C149 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF -C150 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF -C151 ro_div_new_0/divider_0/tspc_2/Z2 ro_div_new_0/divider_0/tspc_2/Z3 0.16fF -C152 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z4 0.22fF -C153 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF -C154 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF -C155 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF -C156 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF -C157 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF -C158 io_clamp_low[1] io_clamp_high[1] 0.53fF -C159 pll_full_0/divbuf_0/a_492_n240# pll_full_0/pd_0/DIV 0.00fF -C160 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF -C161 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF -C162 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF -C163 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF -C164 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_1/Z4 0.65fF -C165 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C166 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF -C167 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C168 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF -C169 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C170 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF -C171 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF -C172 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF -C173 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF -C174 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF -C175 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF -C176 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF -C177 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF -C178 cp_0/down cp_0/upbar 0.02fF -C179 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z2 0.14fF -C180 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C181 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF -C182 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C183 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF -C184 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C185 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C186 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF -C187 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF -C188 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C189 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/clk 0.04fF -C190 divbuf_2/OUT5 divbuf_2/a_492_n240# 0.01fF -C191 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF -C192 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF -C193 pd_0/DOWN pd_0/UP 0.46fF -C194 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF -C195 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C196 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF -C197 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF -C198 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF -C199 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/and_0/B 0.18fF -C200 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_1/Q 0.05fF -C201 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/clk 0.45fF -C202 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF -C203 divbuf_0/a_492_n240# divbuf_0/OUT5 0.01fF -C204 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF -C205 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF -C206 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF -C207 divbuf_6/OUT2 divbuf_6/OUT 0.06fF -C208 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF -C209 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF -C210 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C211 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF -C212 divider_0/nor_1/A divider_0/and_0/A 0.01fF -C213 divbuf_1/OUT2 divbuf_1/OUT 0.06fF -C214 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF -C215 divbuf_3/OUT3 divbuf_3/OUT 0.26fF -C216 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF -C217 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C218 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C219 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF -C220 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF -C221 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF -C222 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF -C223 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF -C224 divider_0/nor_0/B divider_0/and_0/B 0.29fF -C225 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF -C226 cp_0/upbar cp_0/a_1710_n2840# 0.29fF -C227 divbuf_0/OUT divbuf_0/OUT4 1.11fF -C228 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF -C229 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF -C230 divbuf_4/OUT3 divbuf_4/OUT 0.26fF -C231 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF -C232 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C233 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF -C234 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF -C235 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF -C236 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/a_630_n680# 0.35fF -C237 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/divider_0/clk 0.05fF -C238 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF -C239 ro_div_new_0/divider_0/tspc_2/Z2 ro_div_new_0/divider_0/tspc_2/Z4 0.36fF -C240 ro_div_new_0/divider_0/tspc_2/Z3 ro_div_new_0/divider_0/Out 0.05fF -C241 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF -C242 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF -C243 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF -C244 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF -C245 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF -C246 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF -C247 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF -C248 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF -C249 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C250 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a2 0.09fF -C251 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF -C252 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF -C253 ro_div_new_0/divider_0/and_0/A ro_div_new_0/divider_0/and_0/B 0.18fF -C254 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF -C255 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF -C256 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF -C257 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF -C258 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF -C259 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF -C260 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF -C261 ro_div_new_0/divider_0/prescaler_0/tspc_0/D ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.24fF -C262 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/Out 0.19fF -C263 ro_div_new_0/ro_complete_0/cbank_2/v ro_div_new_0/divider_0/clk 1.36fF -C264 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C265 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF -C266 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C267 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF -C268 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF -C269 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF -C270 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF -C271 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF -C272 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C273 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/divider_0/clk 1.30fF -C274 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF -C275 ro_div_new_0/divider_0/prescaler_0/tspc_0/D ro_div_new_0/divider_0/clk 0.26fF -C276 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C277 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF -C278 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF -C279 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF -C280 pd_0/R pd_0/REF 0.61fF -C281 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/DOWN 0.03fF -C282 divider_0/nor_1/B divider_0/and_0/B 0.31fF -C283 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF -C284 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF -C285 ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin ro_div_new_0/divider_0/clk 1.30fF -C286 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF -C287 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C288 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF -C289 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF -C290 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF -C291 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF -C292 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF -C293 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF -C294 divbuf_6/OUT4 divbuf_6/OUT 1.11fF -C295 pll_full_0/pd_0/REF pll_full_0/pd_0/DOWN 1.48fF -C296 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF -C297 divider_0/and_0/OUT divider_0/clk 0.04fF -C298 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Z4 0.65fF -C299 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF -C300 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C301 divbuf_3/OUT5 divbuf_3/OUT 43.38fF -C302 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF -C303 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF -C304 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/a_630_n680# 0.05fF -C305 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_0/Q 0.01fF -C306 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C307 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C308 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C309 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF -C310 divbuf_4/OUT5 divbuf_4/OUT 43.38fF -C311 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF -C312 pll_full_0/pd_0/UP pll_full_0/pd_0/DOWN 4.58fF -C313 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF -C314 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/a4 0.12fF -C315 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF -C316 divbuf_0/OUT divbuf_0/OUT5 43.38fF -C317 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF -C318 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF -C319 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF -C320 io_clamp_low[0] io_clamp_high[0] 0.53fF -C321 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF -C322 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF -C323 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF -C324 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C325 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C326 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF -C327 ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin ro_div_new_0/ro_complete_0/a0 0.09fF -C328 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF -C329 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/clk 0.01fF -C330 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF -C331 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF -C332 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF -C333 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF -C334 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF -C335 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF -C336 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.27fF -C337 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF -C338 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF -C339 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF -C340 divider_0/tspc_2/Z3 divider_0/Out 0.05fF -C341 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C342 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/prescaler_0/Out 0.15fF -C343 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C344 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/clk 0.45fF -C345 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF -C346 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF -C347 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF -C348 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF -C349 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C350 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF -C351 pll_full_0/pd_0/REF pll_full_0/pd_0/R 0.61fF -C352 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C353 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF -C354 divider_0/and_0/A divider_0/and_0/B 0.18fF -C355 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.05fF -C356 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/nor_1/A 1.21fF -C357 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C358 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/nor_0/B 0.35fF -C359 divbuf_2/OUT5 divbuf_2/IN 0.00fF -C360 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF -C361 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF -C362 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF -C363 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C364 divbuf_5/IN divbuf_5/OUT5 0.00fF -C365 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF -C366 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C367 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF -C368 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF -C369 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF -C370 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_1/B 0.06fF -C371 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF -C372 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF -C373 io_clamp_high[2] io_analog[6] 0.53fF -C374 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/a_630_n680# 0.01fF -C375 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF -C376 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF -C377 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C378 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C379 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF -C380 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF -C381 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF -C382 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF -C383 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF -C384 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C385 pll_full_0/pd_0/REF pll_full_0/divbuf_1/OUT5 0.00fF -C386 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF -C387 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_0/Q 0.22fF -C388 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/Out 0.11fF -C389 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF -C390 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF -C391 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C392 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C393 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C394 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF -C395 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF -C396 divbuf_1/OUT3 divbuf_1/OUT2 1.37fF -C397 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C398 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C399 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF -C400 ro_div_new_0/divider_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/Out 0.11fF -C401 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/clk 0.64fF -C402 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF -C403 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C404 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C405 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF -C406 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF -C407 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF -C408 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF -C409 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/a1 0.14fF -C410 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF -C411 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin ro_div_new_0/ro_complete_0/a3 0.09fF -C412 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF -C413 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF -C414 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C415 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF -C416 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF -C417 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF -C418 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF -C419 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF -C420 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF -C421 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_1/A 0.04fF -C422 ro_div_new_0/divider_0/tspc_0/Z1 ro_div_new_0/divider_0/tspc_0/Z3 0.06fF -C423 divbuf_1/OUT3 divbuf_1/OUT 0.26fF -C424 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF -C425 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/tspc_1/Z4 0.12fF -C426 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF -C427 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C428 ro_div_new_0/divider_0/and_0/B ro_div_new_0/divider_0/and_0/Z1 0.07fF -C429 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF -C430 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C431 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C432 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF -C433 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF -C434 pll_full_0/pd_0/R pll_full_0/pd_0/DOWN 0.36fF -C435 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF -C436 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF -C437 ro_complete_0/a5 ro_complete_0/cbank_0/switch_0/vin 0.09fF -C438 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.44fF -C439 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF -C440 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_0/Q 0.55fF -C441 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/clk 0.12fF -C442 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF -C443 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF -C444 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF -C445 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF -C446 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/switch_1/vin 0.19fF -C447 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C448 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF -C449 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF -C450 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF -C451 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/nor_1/A 0.01fF -C452 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z2 0.30fF -C453 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C454 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z2 0.01fF -C455 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/clk 0.60fF -C456 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C457 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C458 divbuf_2/OUT2 divbuf_2/OUT 0.06fF -C459 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C460 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF -C461 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C462 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF -C463 divbuf_5/OUT2 divbuf_5/OUT 0.06fF -C464 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF -C465 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z1 0.09fF -C466 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF -C467 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF -C468 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C469 io_clamp_low[1] io_analog[5] 0.53fF -C470 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_1/a_630_n680# 0.04fF -C471 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_0/Z2 0.23fF -C472 ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin ro_div_new_0/divider_0/clk 1.30fF -C473 divbuf_1/a_492_n240# divbuf_1/OUT5 0.01fF -C474 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/A 0.01fF -C475 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT5 0.01fF -C476 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF -C477 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF -C478 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF -C479 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF -C480 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF -C481 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF -C482 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF -C483 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF -C484 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF -C485 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF -C486 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C487 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C488 pll_full_0/pd_0/UP pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C489 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF -C490 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.13fF -C491 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF -C492 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF -C493 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C494 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C495 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF -C496 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/nor_1/B 0.18fF -C497 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF -C498 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF -C499 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/and_0/OUT 0.05fF -C500 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/clk 0.12fF -C501 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF -C502 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/switch_1/vin 0.20fF -C503 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF -C504 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C505 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF -C506 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF -C507 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF -C508 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF -C509 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/a1 0.14fF -C510 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF -C511 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF -C512 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF -C513 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_1/Z2 0.15fF -C514 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z4 0.21fF -C515 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C516 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF -C517 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF -C518 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF -C519 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF -C520 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF -C521 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/a4 0.12fF -C522 pd_0/R pd_0/and_pd_0/Out1 0.33fF -C523 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF -C524 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF -C525 pll_full_0/pd_0/R pll_full_0/pd_0/DIV 0.51fF -C526 divider_0/mc2 divider_0/nor_1/A 0.04fF -C527 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C528 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF -C529 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF -C530 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF -C531 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF -C532 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF -C533 divbuf_0/OUT2 divbuf_0/OUT5 0.02fF -C534 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF -C535 divbuf_7/OUT3 divbuf_7/OUT 0.26fF -C536 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF -C537 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C538 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Z3 0.38fF -C539 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF -C540 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF -C541 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C542 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF -C543 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_0/Q 0.14fF -C544 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF -C545 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF -C546 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF -C547 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF -C548 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF -C549 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF -C550 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C551 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF -C552 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF -C553 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF -C554 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF -C555 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_1/Z3 0.06fF -C556 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Q 0.51fF -C557 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF -C558 divider_0/and_0/B divider_0/and_0/Z1 0.07fF -C559 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF -C560 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/Z1 0.04fF -C561 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/Out 0.04fF -C562 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z2 0.40fF -C563 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/clk 0.05fF -C564 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF -C565 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF -C566 divbuf_2/OUT4 divbuf_2/OUT 1.11fF -C567 divbuf_5/OUT4 divbuf_5/OUT 1.11fF -C568 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C569 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C570 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF -C571 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF -C572 pd_0/R pd_0/tspc_r_1/Z2 0.21fF -C573 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF -C574 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF -C575 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_1/Z4 0.02fF -C576 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT4 20.26fF -C577 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C578 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C579 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF -C580 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF -C581 pd_0/UP pd_0/and_pd_0/Z1 0.06fF -C582 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF -C583 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF -C584 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/and_0/B 0.31fF -C585 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Z4 0.12fF -C586 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.21fF -C587 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.03fF -C588 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF -C589 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF -C590 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C591 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C592 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF -C593 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF -C594 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF -C595 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C596 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.09fF -C597 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF -C598 divider_0/and_0/out1 divider_0/and_0/A 0.01fF -C599 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF -C600 ro_div_new_0/divider_0/tspc_1/Z4 ro_div_new_0/divider_0/tspc_0/Q 0.15fF -C601 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT5 43.38fF -C602 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C603 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C604 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF -C605 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF -C606 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF -C607 divbuf_2/OUT2 divbuf_2/a_492_n240# 0.42fF -C608 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF -C609 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF -C610 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF -C611 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF -C612 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF -C613 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF -C614 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF -C615 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF -C616 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF -C617 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT5 0.02fF -C618 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF -C619 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF -C620 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C621 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF -C622 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF -C623 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF -C624 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF -C625 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF -C626 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF -C627 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_2/Z4 0.02fF -C628 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin ro_div_new_0/divider_0/clk 1.30fF -C629 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF -C630 divbuf_3/IN divbuf_3/OUT5 0.00fF -C631 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF -C632 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF -C633 divbuf_7/OUT5 divbuf_7/OUT 43.38fF -C634 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF -C635 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DOWN 0.11fF -C636 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF -C637 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.19fF -C638 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF -C639 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/and_0/B 0.08fF -C640 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/tspc_0/Q 0.19fF -C641 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/clk 0.14fF -C642 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF -C643 divbuf_4/IN divbuf_4/OUT5 0.00fF -C644 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF -C645 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF -C646 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z1 0.17fF -C647 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF -C648 divider_0/nor_1/B divider_0/nor_0/B 0.47fF -C649 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF -C650 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF -C651 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF -C652 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF -C653 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C654 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/B 0.20fF -C655 ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin ro_div_new_0/divider_0/clk 1.45fF -C656 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z3 0.06fF -C657 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/Out 0.22fF -C658 ro_div_new_0/divider_0/prescaler_0/tspc_2/D ro_div_new_0/divider_0/clk 0.29fF -C659 divbuf_0/a_492_n240# divbuf_0/OUT2 0.42fF -C660 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF -C661 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C662 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF -C663 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF -C664 cp_0/out cp_0/a_1710_0# 0.84fF -C665 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF -C666 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF -C667 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF -C668 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF -C669 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF -C670 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF -C671 io_clamp_high[0] io_analog[4] 0.53fF -C672 ro_div_new_0/divider_0/tspc_1/Z2 ro_div_new_0/divider_0/tspc_1/Z4 0.36fF -C673 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/and_0/OUT 0.06fF -C674 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF -C675 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF -C676 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/Z1 0.36fF -C677 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF -C678 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF -C679 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C680 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF -C681 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF -C682 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF -C683 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF -C684 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C685 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF -C686 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF -C687 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF -C688 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF -C689 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF -C690 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF -C691 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z1 0.01fF -C692 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.05fF -C693 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF -C694 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF -C695 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF -C696 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C697 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C698 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF -C699 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C700 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF -C701 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF -C702 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF -C703 divider_0/mc2 divider_0/and_0/B 0.20fF -C704 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF -C705 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C706 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF -C707 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF -C708 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF -C709 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C710 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF -C711 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF -C712 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF -C713 ro_div_new_0/divider_0/tspc_0/Z1 ro_div_new_0/divider_0/tspc_0/Z4 0.00fF -C714 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C715 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.11fF -C716 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 ro_div_new_0/divider_0/clk 0.11fF -C717 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/and_0/A 0.80fF -C718 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF -C719 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/switch_1/vin 0.19fF -C720 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF -C721 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF -C722 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF -C723 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF -C724 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF -C725 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF -C726 pd_0/UP pd_0/tspc_r_1/z5 0.03fF -C727 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF -C728 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/DIV 0.12fF -C729 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF -C730 ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C731 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.45fF -C732 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.15fF -C733 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/and_0/OUT 0.06fF -C734 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF -C735 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF -C736 divbuf_3/OUT2 divbuf_3/OUT 0.06fF -C737 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF -C738 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C739 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF -C740 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF -C741 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF -C742 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.32fF -C743 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF -C744 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF -C745 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF -C746 divbuf_4/OUT2 divbuf_4/OUT 0.06fF -C747 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF -C748 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF -C749 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C750 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF -C751 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF -C752 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/a0 0.13fF -C753 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF -C754 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF -C755 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF -C756 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF -C757 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF -C758 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF -C759 ro_div_new_0/divider_0/tspc_2/Z1 ro_div_new_0/divider_0/tspc_2/Z4 0.00fF -C760 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF -C761 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF -C762 divbuf_1/OUT5 divbuf_1/OUT 43.38fF -C763 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF -C764 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C765 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF -C766 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF -C767 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF -C768 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF -C769 ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF -C770 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C771 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF -C772 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF -C773 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF -C774 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF -C775 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF -C776 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF -C777 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/divider_0/clk 0.05fF -C778 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF -C779 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF -C780 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF -C781 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF -C782 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF -C783 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF -C784 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/OUT 0.05fF -C785 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF -C786 ro_div_new_0/divider_0/nor_0/Z1 ro_div_new_0/divider_0/and_0/B 0.78fF -C787 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF -C788 divider_0/nor_0/B divider_0/Out 0.22fF +C0 divider_0/nor_1/A divider_0/tspc_0/Q 0.55fF +C1 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF +C2 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF +C3 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C4 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C5 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C6 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF +C7 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C8 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C9 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C10 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C11 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C12 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF +C13 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF +C14 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF +C15 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF +C16 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C17 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z3 0.45fF +C18 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF +C19 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C20 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C21 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF +C22 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C23 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C24 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C25 pll_full_0/ro_complete_0/a0 pll_full_0/divider_0/clk 0.01fF +C26 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C27 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C28 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C29 divbuf_1/OUT2 divbuf_1/OUT 0.06fF +C30 divbuf_1/OUT3 divbuf_1/OUT5 0.01fF +C31 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF +C32 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF +C33 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF +C34 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C35 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C36 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF +C37 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF +C38 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF +C39 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF +C40 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF +C41 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C42 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C43 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C44 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF +C45 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C46 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF +C47 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT2 0.06fF +C48 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT3 0.01fF +C49 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C50 divbuf_6/OUT5 divbuf_6/OUT 43.38fF +C51 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF +C52 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C53 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C54 cp_0/a_1710_0# cp_0/out 0.84fF +C55 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C56 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C57 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C58 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF +C59 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF +C60 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF +C61 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF +C62 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C63 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF +C64 pll_full_0/pd_0/DOWN pll_full_0/cp_0/a_1710_0# 0.04fF +C65 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/R 0.33fF +C66 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C67 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C68 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF +C69 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF +C70 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF +C71 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C72 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C73 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C74 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF +C75 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C76 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C77 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF +C78 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C79 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C80 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF +C81 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF +C82 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C83 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C84 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C85 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C86 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C87 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF +C88 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C89 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF +C90 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C91 divbuf_7/IN divbuf_7/OUT5 0.00fF +C92 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C93 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF +C94 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C95 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C96 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C97 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C98 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C99 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF +C100 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C101 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF +C102 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF +C103 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C104 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C105 divbuf_1/OUT4 divbuf_1/OUT 1.11fF +C106 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z2 0.19fF +C107 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C108 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF +C109 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF +C110 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C111 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C112 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF +C113 divbuf_0/OUT5 divbuf_0/OUT 43.38fF +C114 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT4 1.11fF +C115 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF +C116 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C117 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF +C118 divider_0/prescaler_0/Out divider_0/tspc_0/a_630_n680# 0.01fF +C119 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C120 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF +C121 cp_0/a_1710_0# cp_0/down 0.32fF +C122 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C123 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C124 io_clamp_low[2] io_analog[6] 0.53fF +C125 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C126 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF +C127 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF +C128 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF +C129 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF +C130 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF +C131 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF +C132 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C133 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C134 pll_full_0/pd_0/DIV pll_full_0/divider_0/clk 2.26fF +C135 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C136 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF +C137 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C138 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C139 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C140 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF +C141 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C142 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF +C143 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF +C144 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF +C145 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C146 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C147 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C148 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C149 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C150 divbuf_0/OUT5 divbuf_0/IN 0.00fF +C151 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF +C152 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C153 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF +C154 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF +C155 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C156 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF +C157 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C158 divbuf_7/OUT2 divbuf_7/OUT 0.06fF +C159 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF +C160 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF +C161 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF +C162 pll_full_0/ro_complete_0/a4 pll_full_0/divider_0/clk 0.11fF +C163 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF +C164 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF +C165 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C166 divider_0/nor_0/B divider_0/Out 0.22fF +C167 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C168 cp_0/a_1710_n2840# cp_0/out 0.61fF +C169 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF +C170 divider_0/mc2 divider_0/and_0/out1 0.06fF +C171 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C172 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF +C173 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF +C174 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF +C175 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF +C176 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF +C177 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C178 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C179 pll_full_0/pd_0/DIV pll_full_0/pd_0/R 0.51fF +C180 divbuf_2/OUT3 divbuf_2/OUT 0.26fF +C181 divbuf_5/OUT3 divbuf_5/OUT 0.26fF +C182 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF +C183 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C184 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Qbar1 0.12fF +C185 divider_0/mc2 divider_0/nor_1/A 0.04fF +C186 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C187 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF +C188 divider_0/prescaler_0/Out divider_0/nor_1/A 0.15fF +C189 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF +C190 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF +C191 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C192 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C193 pll_full_0/divbuf_1/OUT5 pll_full_0/pd_0/REF 0.00fF +C194 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C195 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C196 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C197 pll_full_0/pd_0/DIV pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF +C198 pll_full_0/divbuf_1/OUT2 pll_full_0/divbuf_1/OUT3 1.37fF +C199 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF +C200 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF +C201 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF +C202 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF +C203 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C204 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF +C205 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF +C206 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C207 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF +C208 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF +C209 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C210 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C211 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C212 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C213 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C214 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C215 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF +C216 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C217 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF +C218 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF +C219 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF +C220 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF +C221 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C222 cp_0/upbar cp_0/a_1710_n2840# 0.29fF +C223 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C224 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C225 divider_0/mc2 divider_0/nor_1/B 0.06fF +C226 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C227 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF +C228 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C229 divbuf_7/OUT4 divbuf_7/OUT 1.11fF +C230 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF +C231 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF +C232 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C233 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C234 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C235 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C236 divider_0/mc2 divider_0/and_0/A 0.16fF +C237 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF +C238 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF +C239 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF +C240 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C241 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF +C242 divbuf_2/OUT5 divbuf_2/OUT 43.38fF +C243 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C244 divbuf_5/OUT5 divbuf_5/OUT 43.38fF +C245 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF +C246 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF +C247 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF +C248 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF +C249 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C250 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF +C251 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF +C252 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/IN 0.00fF +C253 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF +C254 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF +C255 io_clamp_low[2] io_clamp_high[2] 0.53fF +C256 cp_0/a_10_n50# cp_0/vbias 0.19fF +C257 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C258 io_clamp_high[1] io_analog[5] 0.53fF +C259 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF +C260 divider_0/mc2 divider_0/nor_0/B 0.15fF +C261 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +C262 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF +C263 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C264 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF +C265 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF +C266 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF +C267 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF +C268 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Z3 0.03fF +C269 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF +C270 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C271 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C272 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF +C273 pd_0/DOWN pd_0/R 0.36fF +C274 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C275 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C276 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C277 pll_full_0/pd_0/R pll_full_0/pd_0/REF 0.61fF +C278 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF +C279 divbuf_6/IN divbuf_6/OUT5 0.00fF +C280 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF +C281 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF +C282 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/Out 0.19fF +C283 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C284 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C285 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C286 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C287 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF +C288 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF +C289 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C290 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF +C291 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF +C292 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF +C293 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z2 0.01fF +C294 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/IN 0.13fF +C295 pll_full_0/ro_complete_0/a5 pll_full_0/divider_0/clk 0.15fF +C296 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/clk 0.26fF +C297 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C298 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF +C299 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/UP 0.06fF +C300 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C301 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF +C302 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C303 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF +C304 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF +C305 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/IN 5.26fF +C306 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C307 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF +C308 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF +C309 divider_0/nor_1/A divider_0/tspc_0/Z1 0.03fF +C310 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C311 filter_0/a_4216_n2998# filter_0/v 0.31fF +C312 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/R 0.01fF +C313 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C314 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C315 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/clk 0.45fF +C316 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C317 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C318 divbuf_0/OUT divbuf_0/OUT2 0.06fF +C319 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF +C320 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z2 0.19fF +C321 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF +C322 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF +C323 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/divider_0/clk 1.32fF +C324 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C325 divbuf_1/OUT5 divbuf_1/IN 0.00fF +C326 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C327 io_clamp_low[0] io_analog[4] 0.53fF +C328 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF +C329 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF +C330 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF +C331 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/divider_0/clk 1.27fF +C332 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF +C333 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C334 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C335 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF +C336 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF +C337 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF +C338 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C339 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C340 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C341 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C342 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF +C343 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF +C344 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C345 pll_full_0/filter_0/a_4216_n5230# pll_full_0/divider_0/clk 1.58fF +C346 divbuf_6/OUT2 divbuf_6/OUT 0.06fF +C347 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF +C348 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C349 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/clk 0.45fF +C350 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C351 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C352 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/DOWN 0.07fF +C353 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C354 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF +C355 divbuf_3/OUT3 divbuf_3/OUT 0.26fF +C356 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF +C357 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF +C358 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF +C359 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/A 0.55fF +C360 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C361 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF +C362 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C363 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C364 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C365 divbuf_4/OUT3 divbuf_4/OUT 0.26fF +C366 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF +C367 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF +C368 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF +C369 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF +C370 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF +C371 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C372 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C373 filter_0/a_4216_n5230# filter_0/v 0.19fF +C374 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF +C375 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF +C376 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/z5 0.11fF +C377 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C378 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF +C379 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF +C380 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/clk 0.12fF +C381 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C382 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C383 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/and_pd_0/Out1 0.18fF +C384 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C385 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C386 pd_0/R pd_0/UP 0.45fF +C387 divbuf_0/OUT divbuf_0/OUT3 0.26fF +C388 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C389 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF +C390 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF +C391 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z2 0.14fF +C392 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF +C393 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/Out 0.15fF +C394 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/clk 0.64fF +C395 io_clamp_low[1] io_clamp_high[1] 0.53fF +C396 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C397 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C398 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF +C399 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF +C400 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/nor_1/A 0.03fF +C401 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF +C402 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C403 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/UP 0.33fF +C404 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar 0.21fF +C405 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z3 0.65fF +C406 divider_0/and_0/A divider_0/and_0/B 0.18fF +C407 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF +C408 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C409 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT4 5.16fF +C410 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C411 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF +C412 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C413 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF +C414 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF +C415 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C416 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF +C417 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C418 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT2 0.02fF +C419 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF +C420 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C421 divbuf_6/OUT4 divbuf_6/OUT 1.11fF +C422 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z1 0.01fF +C423 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/clk 0.12fF +C424 divider_0/and_0/OUT divider_0/clk 0.04fF +C425 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C426 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF +C427 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C428 divbuf_3/OUT5 divbuf_3/OUT 43.38fF +C429 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/Z4 0.15fF +C430 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C431 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF +C432 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/clk 0.60fF +C433 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/a_492_n240# 0.01fF +C434 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C435 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C436 divbuf_4/OUT5 divbuf_4/OUT 43.38fF +C437 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF +C438 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF +C439 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_0/D 0.16fF +C440 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.05fF +C441 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF +C442 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C443 divider_0/nor_1/A divider_0/tspc_0/Z4 0.21fF +C444 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF +C445 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF +C446 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C447 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF +C448 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C449 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF +C450 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C451 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C452 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C453 divbuf_0/OUT divbuf_0/OUT4 1.11fF +C454 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C455 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C456 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C457 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF +C458 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF +C459 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C460 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF +C461 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C462 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF +C463 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/clk 0.12fF +C464 cp_0/upbar cp_0/down 0.02fF +C465 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/DOWN 0.12fF +C466 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C467 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C468 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF +C469 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C470 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF +C471 divbuf_1/OUT3 divbuf_1/OUT 0.26fF +C472 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF +C473 divbuf_2/OUT5 divbuf_2/IN 0.00fF +C474 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C475 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C476 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT5 0.01fF +C477 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF +C478 divbuf_5/IN divbuf_5/OUT5 0.00fF +C479 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF +C480 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF +C481 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/divider_0/clk 1.36fF +C482 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C483 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C484 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C485 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF +C486 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/OUT3 0.26fF +C487 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT4 20.26fF +C488 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF +C489 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF +C490 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C491 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF +C492 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C493 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C494 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C495 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C496 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF +C497 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C498 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF +C499 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/divider_0/clk 1.46fF +C500 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C501 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF +C502 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF +C503 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divbuf_0/IN 0.04fF +C504 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/clk 0.05fF +C505 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C506 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/A 0.15fF +C507 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF +C508 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C509 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C510 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C511 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF +C512 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF +C513 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF +C514 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C515 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C516 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C517 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C518 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF +C519 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF +C520 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/clk 0.01fF +C521 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C522 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C523 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C524 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT3 0.26fF +C525 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF +C526 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C527 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF +C528 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF +C529 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/a_630_n680# 0.04fF +C530 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C531 io_clamp_low[0] io_clamp_high[0] 0.53fF +C532 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C533 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C534 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C535 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C536 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF +C537 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF +C538 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF +C539 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF +C540 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF +C541 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF +C542 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C543 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/tspc_r_1/Qbar 0.05fF +C544 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/z5 0.03fF +C545 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF +C546 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C547 pll_full_0/divbuf_0/OUT4 pll_full_0/divbuf_0/OUT5 20.26fF +C548 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF +C549 divbuf_2/OUT2 divbuf_2/OUT 0.06fF +C550 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C551 divbuf_5/OUT2 divbuf_5/OUT 0.06fF +C552 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF +C553 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF +C554 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF +C555 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C556 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C557 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C558 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF +C559 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C560 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF +C561 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF +C562 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF +C563 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF +C564 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.01fF +C565 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.19fF +C566 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/clk 0.14fF +C567 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C568 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C569 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C570 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C571 io_clamp_high[2] io_analog[6] 0.53fF +C572 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF +C573 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C574 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z3 0.38fF +C575 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF +C576 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF +C577 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF +C578 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C579 pll_full_0/divider_0/nor_0/B pll_full_0/divbuf_0/IN 0.29fF +C580 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF +C581 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/clk 0.29fF +C582 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C583 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF +C584 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C585 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF +C586 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF +C587 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C588 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF +C589 pd_0/DIV pd_0/R 0.51fF +C590 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT2 0.42fF +C591 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF +C592 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF +C593 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF +C594 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF +C595 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C596 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF +C597 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C598 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C599 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C600 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C601 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF +C602 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C603 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C604 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C605 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF +C606 pll_full_0/pd_0/UP pll_full_0/pd_0/tspc_r_1/z5 0.03fF +C607 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF +C608 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/divider_0/clk 1.46fF +C609 divbuf_7/OUT3 divbuf_7/OUT 0.26fF +C610 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF +C611 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C612 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF +C613 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C614 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C615 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF +C616 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF +C617 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C618 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF +C619 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C620 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C621 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C622 divbuf_1/OUT2 divbuf_1/a_492_n240# 0.42fF +C623 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z2 0.25fF +C624 divbuf_2/OUT4 divbuf_2/OUT 1.11fF +C625 pll_full_0/divbuf_0/OUT3 pll_full_0/divbuf_0/OUT2 1.37fF +C626 divbuf_5/OUT4 divbuf_5/OUT 1.11fF +C627 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF +C628 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF +C629 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C630 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C631 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF +C632 pd_0/DOWN pd_0/UP 0.46fF +C633 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C634 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF +C635 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C636 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF +C637 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF +C638 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF +C639 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF +C640 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.32fF +C641 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/clk 0.01fF +C642 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C643 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C644 io_clamp_low[1] io_analog[5] 0.53fF +C645 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C646 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF +C647 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF +C648 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/divider_0/clk 1.46fF +C649 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF +C650 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C651 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C652 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/DIV 0.17fF +C653 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF +C654 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C655 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF +C656 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF +C657 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/nor_1/A 0.35fF +C658 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF +C659 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF +C660 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF +C661 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C662 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C663 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C664 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C665 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF +C666 divbuf_1/OUT5 divbuf_1/OUT 43.38fF +C667 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/a_492_n240# 0.01fF +C668 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF +C669 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF +C670 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF +C671 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/Out 0.08fF +C672 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C673 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C674 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT5 43.38fF +C675 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/pd_0/tspc_r_1/Z4 0.14fF +C676 divbuf_3/IN divbuf_3/OUT5 0.00fF +C677 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C678 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF +C679 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C680 divbuf_7/OUT5 divbuf_7/OUT 43.38fF +C681 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C682 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C683 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C684 divider_0/mc2 divider_0/and_0/B 0.20fF +C685 divbuf_4/IN divbuf_4/OUT5 0.00fF +C686 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C687 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.04fF +C688 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C689 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C690 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C691 pll_full_0/pd_0/DOWN pll_full_0/pd_0/REF 1.48fF +C692 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/z5 0.04fF +C693 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF +C694 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/R 0.27fF +C695 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF +C696 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C697 divider_0/prescaler_0/tspc_1/Q divider_0/nor_1/A 0.03fF +C698 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C699 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF +C700 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/clk 0.11fF +C701 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C702 pd_0/R pd_0/REF 0.61fF +C703 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C704 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF +C705 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF +C706 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z1 0.17fF +C707 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF +C708 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C709 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF +C710 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF +C711 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF +C712 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF +C713 pll_full_0/ro_complete_0/a2 pll_full_0/divider_0/clk 0.11fF +C714 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C715 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/tspc_2/D 0.04fF +C716 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF +C717 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C718 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C719 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/a_492_n240# 0.00fF +C720 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF +C721 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/divider_0/clk 1.61fF +C722 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C723 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF +C724 pll_full_0/divbuf_1/OUT5 pll_full_0/divbuf_1/OUT 43.38fF +C725 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_0/Qbar1 0.11fF +C726 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C727 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C728 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF +C729 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF +C730 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/Out 0.12fF +C731 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF +C732 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF +C733 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C734 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C735 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C736 divider_0/nor_1/A divider_0/nor_1/B 1.21fF +C737 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C738 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF +C739 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z3 0.29fF +C740 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C741 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF +C742 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF +C743 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF +C744 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF +C745 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF +C746 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF +C747 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/Out 0.11fF +C748 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/clk 0.11fF +C749 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C750 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C751 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C752 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C753 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C754 divbuf_3/OUT2 divbuf_3/OUT 0.06fF +C755 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF +C756 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF +C757 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z3 0.05fF +C758 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C759 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C760 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C761 divbuf_4/OUT2 divbuf_4/OUT 0.06fF +C762 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF +C763 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/divider_0/clk 1.46fF +C764 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/clk 0.51fF +C765 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C766 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C767 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF +C768 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Q 0.04fF +C769 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Z4 0.20fF +C770 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C771 pll_full_0/divbuf_0/OUT5 pll_full_0/divbuf_0/OUT2 0.02fF +C772 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF +C773 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C774 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C775 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C776 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C777 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C778 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C779 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C780 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF +C781 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF +C782 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF +C783 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF +C784 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C785 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C786 pll_full_0/divider_0/prescaler_0/tspc_0/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF +C787 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/clk 0.11fF +C788 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF C789 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF -C790 divbuf_0/OUT3 divbuf_0/OUT 0.26fF -C791 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z3 0.45fF -C792 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.11fF -C793 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF -C794 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF -C795 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C796 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF -C797 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/UP 0.11fF -C798 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DOWN 0.03fF -C799 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF -C800 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF -C801 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF -C802 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF -C803 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF -C804 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF -C805 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/nor_1/A 0.38fF -C806 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/divider_0/clk 0.05fF -C807 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.44fF -C808 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF -C809 divbuf_0/OUT divbuf_0/OUT2 0.06fF -C810 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF -C811 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF -C812 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF -C813 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z2 0.21fF -C814 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C790 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/R 0.02fF +C791 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C792 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C793 io_clamp_high[0] io_analog[4] 0.53fF +C794 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C795 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C796 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C797 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C798 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C799 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF +C800 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF +C801 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF +C802 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C803 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C804 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C805 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF +C806 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C807 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C808 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF +C809 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF +C810 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF +C811 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_0/Z3 0.05fF +C812 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF +C813 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF +C814 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/clk 0.01fF C815 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF C816 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF -C817 divider_0/nor_1/B divider_0/and_0/A 0.26fF -C818 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF -C819 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C820 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF -C821 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/and_0/OUT 0.14fF -C822 ro_div_new_0/ro_complete_0/a3 ro_div_new_0/divider_0/clk 0.05fF -C823 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF -C824 pll_full_0/ro_complete_0/a3 pll_full_0/divider_0/clk 0.11fF -C825 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF -C826 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF -C827 divbuf_6/OUT3 divbuf_6/OUT 0.26fF -C828 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF -C829 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF -C830 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/DIV 0.19fF -C831 divider_0/mc2 divider_0/and_0/OUT 0.05fF -C832 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.02fF -C833 divider_0/nor_1/A divider_0/and_0/B 0.08fF -C834 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Q 0.05fF -C835 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 ro_div_new_0/divider_0/clk 0.12fF -C836 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF -C837 divbuf_3/OUT4 divbuf_3/OUT 1.11fF -C838 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF -C839 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF -C840 pll_full_0/pd_0/REF pll_full_0/pd_0/tspc_r_1/Z3 0.65fF -C841 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF -C842 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C843 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF -C844 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF -C845 filter_0/a_4216_n5230# filter_0/v 0.19fF -C846 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF -C847 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C848 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/prescaler_0/tspc_2/D 0.04fF -C849 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.22fF -C850 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF -C851 divbuf_4/OUT4 divbuf_4/OUT 1.11fF -C852 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C853 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF -C854 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/Out 0.11fF -C855 pd_0/DOWN pd_0/R 0.36fF -C856 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF -C857 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF -C858 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF -C859 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF -C860 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF -C861 ro_div_new_0/divider_0/tspc_0/Z3 ro_div_new_0/divider_0/tspc_0/Z2 0.16fF -C862 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF -C863 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/divider_0/clk 1.30fF -C864 ro_div_new_0/divider_0/tspc_2/Z3 ro_div_new_0/divider_0/tspc_2/Z4 0.65fF -C865 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF -C866 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF -C867 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF -C868 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF -C869 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF -C870 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF -C871 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/UP 0.03fF -C872 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF -C873 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF -C874 pll_full_0/divbuf_0/a_492_n240# pll_full_0/divbuf_0/OUT5 0.01fF -C875 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF -C876 pll_full_0/pd_0/DIV pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C877 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF -C878 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF -C879 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF -C880 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF -C881 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF -C882 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF -C883 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF -C884 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF -C885 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Q 0.20fF -C886 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_1/A 1.21fF -C887 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF -C888 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF -C889 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/DIV 0.04fF -C890 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF -C891 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF -C892 ro_div_new_0/ro_complete_0/a1 ro_div_new_0/ro_complete_0/cbank_2/v 0.05fF -C893 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF -C894 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF -C895 ro_div_new_0/divider_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/nor_0/B 0.00fF -C896 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/Z4 0.15fF -C897 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.11fF -C898 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/clk 0.11fF -C899 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF -C900 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar 0.03fF -C901 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF -C902 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF -C903 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF -C904 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF -C905 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF -C906 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/and_0/out1 0.06fF -C907 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF -C908 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/Out 0.21fF -C909 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF -C910 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C911 pd_0/R pd_0/tspc_r_1/Z3 0.29fF -C912 pll_full_0/pd_0/REF pll_full_0/divbuf_1/a_492_n240# 0.13fF -C913 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF -C914 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF -C915 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF -C916 io_clamp_low[2] io_analog[6] 0.53fF -C917 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_0/D 0.16fF -C918 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C919 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF -C920 ro_div_new_0/divider_0/prescaler_0/Out ro_div_new_0/divider_0/clk 0.51fF -C921 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z2 0.30fF -C922 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF -C923 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF -C924 divbuf_6/OUT5 divbuf_6/OUT 43.38fF -C925 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF -C926 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF -C927 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF -C928 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.30fF -C929 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF -C930 cp_0/a_1710_0# cp_0/down 0.32fF -C931 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF -C932 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF -C933 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C934 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF -C935 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z1 0.71fF -C936 divider_0/mc2 divider_0/and_0/out1 0.06fF -C937 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF -C938 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/cbank_0/v 1.30fF -C939 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin 0.20fF -C940 cp_0/vbias cp_0/a_10_n50# 0.19fF -C941 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z1 0.03fF -C942 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF -C943 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.01fF -C944 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 ro_div_new_0/divider_0/prescaler_0/Out 0.05fF -C945 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/clk 0.11fF -C946 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF -C947 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C948 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF -C949 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF -C950 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF -C951 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF -C952 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF -C953 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF -C954 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF -C955 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF -C956 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z1 0.03fF -C957 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF -C958 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF -C959 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF -C960 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF -C961 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF -C962 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF -C963 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF -C964 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin ro_div_new_0/ro_complete_0/a5 0.09fF -C965 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF -C966 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF -C967 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C968 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF -C969 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF -C970 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF -C971 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C972 divbuf_1/OUT3 divbuf_1/OUT5 0.01fF -C973 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/nor_0/B 0.47fF -C974 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C975 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF -C976 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF -C977 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.20fF -C978 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/nor_1/A 0.01fF -C979 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF -C980 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF -C981 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.15fF -C982 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF -C983 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF -C984 divbuf_7/IN divbuf_7/OUT5 0.00fF -C985 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.21fF -C986 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF -C987 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF -C988 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF -C989 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 ro_div_new_0/divider_0/prescaler_0/Out 0.28fF -C990 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C991 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF -C992 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF -C993 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF -C994 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF -C995 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/R 0.29fF -C996 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF -C997 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF -C998 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF -C999 ro_div_new_0/ro_complete_0/a2 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF -C1000 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF -C1001 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF -C1002 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF -C1003 ro_div_new_0/divider_0/and_0/OUT ro_div_new_0/divider_0/and_0/B 0.01fF -C1004 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q ro_div_new_0/divider_0/prescaler_0/Out 0.91fF -C1005 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF -C1006 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1007 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1008 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/Out 0.04fF -C1009 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF -C1010 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF -C1011 pd_0/R pd_0/UP 0.45fF -C1012 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_0/switch_0/vin 0.09fF -C1013 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF -C1014 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF -C1015 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF -C1016 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT4 1.11fF -C1017 ro_div_new_0/divider_0/tspc_1/Z3 ro_div_new_0/divider_0/tspc_1/a_630_n680# 0.05fF -C1018 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/nand_0/z1 0.07fF -C1019 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF -C1020 ro_div_new_0/ro_complete_0/a1 ro_div_new_0/divider_0/clk 0.05fF -C1021 ro_div_new_0/divider_0/prescaler_0/Out ro_div_new_0/divider_0/tspc_0/Z4 0.12fF -C1022 pll_full_0/divbuf_1/OUT3 pll_full_0/divbuf_1/OUT4 5.16fF -C1023 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF -C1024 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF -C1025 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF -C1026 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF -C1027 pll_full_0/ro_complete_0/a1 pll_full_0/divider_0/clk 0.11fF -C1028 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF -C1029 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF -C1030 pd_0/UP pd_0/and_pd_0/Out1 0.33fF -C1031 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF -C1032 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF -C1033 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF -C1034 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF -C1035 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1036 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_0/Q 0.01fF -C1037 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/prescaler_0/Out 0.01fF -C1038 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.06fF -C1039 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/clk 0.01fF -C1040 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF -C1041 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF -C1042 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1043 ro_div_new_0/divider_0/mc2 ro_div_new_0/divider_0/nor_0/B 0.15fF -C1044 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin ro_div_new_0/ro_complete_0/cbank_2/v 1.30fF -C1045 divider_0/prescaler_0/Out divider_0/clk 0.51fF -C1046 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF -C1047 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a2 0.09fF -C1048 ro_div_new_0/divider_0/prescaler_0/tspc_2/D ro_div_new_0/divider_0/prescaler_0/nand_1/z1 0.21fF -C1049 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1050 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF -C1051 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF -C1052 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF -C1053 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF -C1054 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF -C1055 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF -C1056 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF -C1057 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF -C1058 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/clk 0.05fF -C1059 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF -C1060 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/tspc_r_0/z5 0.20fF -C1061 ro_div_new_0/divider_0/nor_1/Z1 ro_div_new_0/divider_0/nor_1/B 0.06fF -C1062 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF -C1063 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF -C1064 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF -C1065 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF -C1066 divbuf_1/OUT4 divbuf_1/OUT 1.11fF -C1067 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.03fF -C1068 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_2/Z2 0.20fF -C1069 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF -C1070 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF -C1071 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF -C1072 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF -C1073 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF -C1074 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF -C1075 divbuf_7/OUT2 divbuf_7/OUT 0.06fF -C1076 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF -C1077 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF -C1078 divider_0/mc2 divider_0/nor_0/B 0.15fF -C1079 ro_div_new_0/ro_complete_0/cbank_0/v ro_div_new_0/ro_complete_0/cbank_2/v 0.04fF -C1080 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF -C1081 ro_div_new_0/divider_0/nor_1/A ro_div_new_0/divider_0/tspc_0/Z4 0.21fF -C1082 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF -C1083 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF -C1084 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF -C1085 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF -C1086 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF -C1087 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF -C1088 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF -C1089 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF -C1090 ro_div_new_0/divider_0/tspc_1/Z1 ro_div_new_0/divider_0/tspc_1/Z2 1.07fF -C1091 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/tspc_1/Z3 0.38fF -C1092 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/nor_1/A 0.35fF -C1093 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF -C1094 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF -C1095 ro_div_new_0/divider_0/tspc_2/a_630_n680# ro_div_new_0/divider_0/tspc_2/Z3 0.05fF -C1096 ro_div_new_0/divider_0/nor_0/B ro_div_new_0/divider_0/tspc_2/Z1 0.03fF -C1097 pll_full_0/divbuf_1/a_492_n240# pll_full_0/divbuf_1/OUT5 0.01fF -C1098 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF -C1099 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF -C1100 divbuf_2/OUT3 divbuf_2/OUT 0.26fF -C1101 divbuf_0/IN divbuf_0/OUT5 0.00fF -C1102 divbuf_5/OUT3 divbuf_5/OUT 0.26fF -C1103 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF -C1104 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF -C1105 io_clamp_low[2] io_clamp_high[2] 0.53fF -C1106 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF -C1107 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_0/vin 0.19fF -C1108 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF -C1109 ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/cbank_2/v 0.08fF -C1110 io_clamp_high[1] io_analog[5] 0.53fF -C1111 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# ro_div_new_0/divider_0/prescaler_0/tspc_1/Q 0.38fF -C1112 divbuf_1/a_492_n240# divbuf_1/OUT 0.00fF -C1113 ro_div_new_0/divider_0/and_0/out1 ro_div_new_0/divider_0/and_0/B 0.18fF -C1114 pll_full_0/divbuf_1/OUT4 pll_full_0/divbuf_1/OUT5 20.26fF -C1115 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF -C1116 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF -C1117 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF -C1118 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF -C1119 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF -C1120 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divbuf_0/IN 0.05fF -C1121 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_0/Z4 0.02fF -C1122 divider_0/and_0/OUT divider_0/and_0/B 0.01fF -C1123 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF -C1124 ro_div_new_0/divider_0/tspc_1/Q ro_div_new_0/divider_0/tspc_2/a_630_n680# 0.01fF -C1125 ro_div_new_0/divider_0/tspc_0/a_630_n680# ro_div_new_0/divider_0/tspc_0/Q 0.04fF -C1126 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_div_new_0/divider_0/clk 0.01fF -C1127 ro_div_new_0/divider_0/nor_1/B ro_div_new_0/divider_0/and_0/A 0.26fF -C1128 pll_full_0/divbuf_1/OUT pll_full_0/divbuf_1/a_492_n240# 0.00fF -C1129 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/OUT3 1.37fF -C1130 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF +C817 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C818 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C819 divider_0/nor_1/A divider_0/tspc_1/Z2 0.15fF +C820 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF +C821 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF +C822 pll_full_0/divbuf_0/OUT2 pll_full_0/divbuf_0/a_492_n240# 0.42fF +C823 divbuf_6/OUT3 divbuf_6/OUT 0.26fF +C824 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF +C825 pll_full_0/divider_0/tspc_0/Q pll_full_0/divider_0/nor_1/B 0.22fF +C826 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF +C827 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C828 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/divider_0/prescaler_0/Out 0.28fF +C829 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C830 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C831 pll_full_0/pd_0/DIV pll_full_0/divbuf_0/OUT2 0.06fF +C832 pll_full_0/pd_0/DIV pll_full_0/divider_0/and_0/OUT 0.01fF +C833 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF +C834 divbuf_3/OUT4 divbuf_3/OUT 1.11fF +C835 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/nor_1/A 0.21fF +C836 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C837 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C838 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C839 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF +C840 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/Out 0.91fF +C841 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C842 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C843 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF +C844 divbuf_4/OUT4 divbuf_4/OUT 1.11fF +C845 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C846 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C847 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C848 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF +C849 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF Xpd_0 VDD gnd pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd -Xro_div_new_0/ro_complete_0 ro_div_new_0/ro_complete_0/a0 ro_div_new_0/ro_complete_0/a1 -+ ro_div_new_0/ro_complete_0/a5 ro_div_new_0/ro_complete_0/a4 ro_div_new_0/ro_complete_0/a3 -+ ro_div_new_0/ro_complete_0/a2 ro_complete -Xro_div_new_0/divider_0 gnd vdd ro_div_new_0/divider_0/Out ro_div_new_0/divider_0/clk -+ ro_div_new_0/divider_0/mc2 divider Xcp_0 cp_0/vbias vdd gnd cp_0/out cp_0/down cp_0/upbar cp Xfilter_0 gnd filter_0/v filter Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 @@ -1265,1047 +979,965 @@ + gnd divbuf Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider Xpll_full_0 vdd pll_full -C1131 io_analog[4] vdd 25.05fF -C1132 io_analog[5] vdd 25.05fF -C1133 io_analog[6] vdd 25.05fF -C1134 io_in_3v3[0] vdd 0.61fF -C1135 io_oeb[26] vdd 0.61fF -C1136 io_in[0] vdd 0.61fF -C1137 io_out[26] vdd 0.61fF -C1138 io_out[0] vdd 0.61fF -C1139 io_in[26] vdd 0.61fF -C1140 io_oeb[0] vdd 0.61fF -C1141 io_in_3v3[26] vdd 0.61fF -C1142 io_in_3v3[1] vdd 0.61fF -C1143 io_oeb[25] vdd 0.61fF -C1144 io_in[1] vdd 0.61fF -C1145 io_out[25] vdd 0.61fF -C1146 io_out[1] vdd 0.61fF -C1147 io_in[25] vdd 0.61fF -C1148 io_oeb[1] vdd 0.61fF -C1149 io_in_3v3[25] vdd 0.61fF -C1150 io_in_3v3[2] vdd 0.61fF -C1151 io_oeb[24] vdd 0.61fF -C1152 io_in[2] vdd 0.61fF -C1153 io_out[24] vdd 0.61fF -C1154 io_out[2] vdd 0.61fF -C1155 io_in[24] vdd 0.61fF -C1156 io_oeb[2] vdd 0.61fF -C1157 io_in_3v3[24] vdd 0.61fF -C1158 io_in_3v3[3] vdd 0.61fF -C1159 gpio_noesd[17] vdd 0.61fF -C1160 io_in[3] vdd 0.61fF -C1161 gpio_analog[17] vdd 0.61fF -C1162 io_out[3] vdd 0.61fF -C1163 io_oeb[3] vdd 0.61fF -C1164 io_in_3v3[4] vdd 0.61fF -C1165 io_in[4] vdd 0.61fF -C1166 io_out[4] vdd 0.61fF -C1167 io_oeb[4] vdd 0.61fF -C1168 io_oeb[23] vdd 0.61fF -C1169 io_out[23] vdd 0.61fF -C1170 io_in[23] vdd 0.61fF -C1171 io_in_3v3[23] vdd 0.61fF -C1172 gpio_noesd[16] vdd 0.61fF -C1173 gpio_analog[16] vdd 0.61fF -C1174 io_in_3v3[5] vdd 0.61fF -C1175 io_in[5] vdd 0.61fF -C1176 io_out[5] vdd 0.61fF -C1177 io_oeb[5] vdd 0.61fF -C1178 io_oeb[22] vdd 0.61fF -C1179 io_out[22] vdd 0.61fF -C1180 io_in[22] vdd 0.61fF -C1181 io_in_3v3[22] vdd 0.61fF -C1182 gpio_noesd[15] vdd 0.61fF -C1183 gpio_analog[15] vdd 0.61fF -C1184 io_in_3v3[6] vdd 0.61fF -C1185 io_in[6] vdd 0.61fF -C1186 io_out[6] vdd 0.61fF -C1187 io_oeb[6] vdd 0.61fF -C1188 io_oeb[21] vdd 0.61fF -C1189 io_out[21] vdd 0.61fF -C1190 io_in[21] vdd 0.61fF -C1191 io_in_3v3[21] vdd 0.61fF -C1192 gpio_noesd[14] vdd 0.61fF -C1193 gpio_analog[14] vdd 0.61fF -C1194 vssa1 vdd 26.08fF -C1195 vssd2 vdd 13.04fF -C1196 vssd1 vdd 13.04fF -C1197 vdda2 vdd 13.04fF -C1198 vdda1 vdd 26.08fF -C1199 io_oeb[20] vdd 0.61fF -C1200 io_out[20] vdd 0.61fF -C1201 io_in[20] vdd 0.61fF -C1202 io_in_3v3[20] vdd 0.61fF -C1203 gpio_noesd[13] vdd 0.61fF -C1204 gpio_analog[13] vdd 0.61fF -C1205 gpio_analog[0] vdd 0.61fF -C1206 gpio_noesd[0] vdd 0.61fF -C1207 io_in_3v3[7] vdd 0.61fF -C1208 io_in[7] vdd 0.61fF -C1209 io_out[7] vdd 0.61fF -C1210 io_oeb[7] vdd 0.61fF -C1211 io_oeb[19] vdd 0.61fF -C1212 io_out[19] vdd 0.61fF -C1213 io_in[19] vdd 0.61fF -C1214 io_in_3v3[19] vdd 0.61fF -C1215 gpio_noesd[12] vdd 0.61fF -C1216 gpio_analog[12] vdd 0.61fF -C1217 gpio_analog[1] vdd 0.61fF -C1218 gpio_noesd[1] vdd 0.61fF -C1219 io_in_3v3[8] vdd 0.61fF -C1220 io_in[8] vdd 0.61fF -C1221 io_out[8] vdd 0.61fF -C1222 io_oeb[8] vdd 0.61fF -C1223 io_oeb[18] vdd 0.61fF -C1224 io_out[18] vdd 0.61fF -C1225 io_in[18] vdd 0.61fF -C1226 io_in_3v3[18] vdd 0.61fF -C1227 gpio_noesd[11] vdd 0.61fF -C1228 gpio_analog[11] vdd 0.61fF -C1229 gpio_analog[2] vdd 0.61fF -C1230 gpio_noesd[2] vdd 0.61fF -C1231 io_in_3v3[9] vdd 0.61fF -C1232 io_in[9] vdd 0.61fF -C1233 io_out[9] vdd 0.61fF -C1234 io_oeb[9] vdd 0.61fF -C1235 io_oeb[17] vdd 0.61fF -C1236 io_out[17] vdd 0.61fF -C1237 io_in[17] vdd 0.61fF -C1238 io_in_3v3[17] vdd 0.61fF -C1239 gpio_noesd[10] vdd 0.61fF -C1240 gpio_analog[10] vdd 0.61fF -C1241 gpio_analog[3] vdd 0.61fF -C1242 gpio_noesd[3] vdd 0.61fF -C1243 io_in_3v3[10] vdd 0.61fF -C1244 io_in[10] vdd 0.61fF -C1245 io_out[10] vdd 0.61fF -C1246 io_oeb[10] vdd 0.61fF -C1247 io_oeb[16] vdd 0.61fF -C1248 io_out[16] vdd 0.61fF -C1249 io_in[16] vdd 0.61fF -C1250 io_in_3v3[16] vdd 0.61fF -C1251 gpio_noesd[9] vdd 0.61fF -C1252 gpio_analog[9] vdd 0.61fF -C1253 gpio_analog[4] vdd 0.61fF -C1254 gpio_noesd[4] vdd 0.61fF -C1255 io_in_3v3[11] vdd 0.61fF -C1256 io_in[11] vdd 0.61fF -C1257 io_out[11] vdd 0.61fF -C1258 io_oeb[11] vdd 0.61fF -C1259 io_oeb[15] vdd 0.61fF -C1260 io_out[15] vdd 0.61fF -C1261 io_in[15] vdd 0.61fF -C1262 io_in_3v3[15] vdd 0.61fF -C1263 gpio_noesd[8] vdd 0.61fF -C1264 gpio_analog[8] vdd 0.61fF -C1265 gpio_analog[5] vdd 0.61fF -C1266 gpio_noesd[5] vdd 0.61fF -C1267 io_in_3v3[12] vdd 0.61fF -C1268 io_in[12] vdd 0.61fF -C1269 io_out[12] vdd 0.61fF -C1270 io_oeb[12] vdd 0.61fF -C1271 io_oeb[14] vdd 0.61fF -C1272 io_out[14] vdd 0.61fF -C1273 io_in[14] vdd 0.61fF -C1274 io_in_3v3[14] vdd 0.61fF -C1275 gpio_noesd[7] vdd 0.61fF -C1276 gpio_analog[7] vdd 0.61fF -C1277 vssa2 vdd 13.04fF -C1278 gpio_analog[6] vdd 0.61fF -C1279 gpio_noesd[6] vdd 0.61fF -C1280 io_in_3v3[13] vdd 0.61fF -C1281 io_in[13] vdd 0.61fF -C1282 io_out[13] vdd 0.61fF -C1283 io_oeb[13] vdd 0.61fF -C1284 vccd1 vdd 13.04fF -C1285 vccd2 vdd 13.04fF -C1286 io_analog[0] vdd 6.83fF -C1287 io_analog[10] vdd 6.83fF -C1288 io_analog[1] vdd 6.83fF -C1289 io_analog[2] vdd 6.83fF -C1290 io_analog[3] vdd 6.83fF -C1291 io_clamp_high[0] vdd 3.58fF -C1292 io_clamp_low[0] vdd 3.58fF -C1293 io_clamp_high[1] vdd 3.58fF -C1294 io_clamp_low[1] vdd 3.58fF -C1295 io_clamp_high[2] vdd 3.58fF -C1296 io_clamp_low[2] vdd 3.58fF -C1297 io_analog[7] vdd 6.83fF -C1298 io_analog[8] vdd 6.83fF -C1299 io_analog[9] vdd 6.83fF -C1300 user_irq[2] vdd 0.63fF -C1301 user_irq[1] vdd 0.63fF -C1302 user_irq[0] vdd 0.63fF -C1303 user_clock2 vdd 0.63fF -C1304 la_oenb[127] vdd 0.63fF -C1305 la_data_out[127] vdd 0.63fF -C1306 la_data_in[127] vdd 0.63fF -C1307 la_oenb[126] vdd 0.63fF -C1308 la_data_out[126] vdd 0.63fF -C1309 la_data_in[126] vdd 0.63fF -C1310 la_oenb[125] vdd 0.63fF -C1311 la_data_out[125] vdd 0.63fF -C1312 la_data_in[125] vdd 0.63fF -C1313 la_oenb[124] vdd 0.63fF -C1314 la_data_out[124] vdd 0.63fF -C1315 la_data_in[124] vdd 0.63fF -C1316 la_oenb[123] vdd 0.63fF -C1317 la_data_out[123] vdd 0.63fF -C1318 la_data_in[123] vdd 0.63fF -C1319 la_oenb[122] vdd 0.63fF -C1320 la_data_out[122] vdd 0.63fF -C1321 la_data_in[122] vdd 0.63fF -C1322 la_oenb[121] vdd 0.63fF -C1323 la_data_out[121] vdd 0.63fF -C1324 la_data_in[121] vdd 0.63fF -C1325 la_oenb[120] vdd 0.63fF -C1326 la_data_out[120] vdd 0.63fF -C1327 la_data_in[120] vdd 0.63fF -C1328 la_oenb[119] vdd 0.63fF -C1329 la_data_out[119] vdd 0.63fF -C1330 la_data_in[119] vdd 0.63fF -C1331 la_oenb[118] vdd 0.63fF -C1332 la_data_out[118] vdd 0.63fF -C1333 la_data_in[118] vdd 0.63fF -C1334 la_oenb[117] vdd 0.63fF -C1335 la_data_out[117] vdd 0.63fF -C1336 la_data_in[117] vdd 0.63fF -C1337 la_oenb[116] vdd 0.63fF -C1338 la_data_out[116] vdd 0.63fF -C1339 la_data_in[116] vdd 0.63fF -C1340 la_oenb[115] vdd 0.63fF -C1341 la_data_out[115] vdd 0.63fF -C1342 la_data_in[115] vdd 0.63fF -C1343 la_oenb[114] vdd 0.63fF -C1344 la_data_out[114] vdd 0.63fF -C1345 la_data_in[114] vdd 0.63fF -C1346 la_oenb[113] vdd 0.63fF -C1347 la_data_out[113] vdd 0.63fF -C1348 la_data_in[113] vdd 0.63fF -C1349 la_oenb[112] vdd 0.63fF -C1350 la_data_out[112] vdd 0.63fF -C1351 la_data_in[112] vdd 0.63fF -C1352 la_oenb[111] vdd 0.63fF -C1353 la_data_out[111] vdd 0.63fF -C1354 la_data_in[111] vdd 0.63fF -C1355 la_oenb[110] vdd 0.63fF -C1356 la_data_out[110] vdd 0.63fF -C1357 la_data_in[110] vdd 0.63fF -C1358 la_oenb[109] vdd 0.63fF -C1359 la_data_out[109] vdd 0.63fF -C1360 la_data_in[109] vdd 0.63fF -C1361 la_oenb[108] vdd 0.63fF -C1362 la_data_out[108] vdd 0.63fF -C1363 la_data_in[108] vdd 0.63fF -C1364 la_oenb[107] vdd 0.63fF -C1365 la_data_out[107] vdd 0.63fF -C1366 la_data_in[107] vdd 0.63fF -C1367 la_oenb[106] vdd 0.63fF -C1368 la_data_out[106] vdd 0.63fF -C1369 la_data_in[106] vdd 0.63fF -C1370 la_oenb[105] vdd 0.63fF -C1371 la_data_out[105] vdd 0.63fF -C1372 la_data_in[105] vdd 0.63fF -C1373 la_oenb[104] vdd 0.63fF -C1374 la_data_out[104] vdd 0.63fF -C1375 la_data_in[104] vdd 0.63fF -C1376 la_oenb[103] vdd 0.63fF -C1377 la_data_out[103] vdd 0.63fF -C1378 la_data_in[103] vdd 0.63fF -C1379 la_oenb[102] vdd 0.63fF -C1380 la_data_out[102] vdd 0.63fF -C1381 la_data_in[102] vdd 0.63fF -C1382 la_oenb[101] vdd 0.63fF -C1383 la_data_out[101] vdd 0.63fF -C1384 la_data_in[101] vdd 0.63fF -C1385 la_oenb[100] vdd 0.63fF -C1386 la_data_out[100] vdd 0.63fF -C1387 la_data_in[100] vdd 0.63fF -C1388 la_oenb[99] vdd 0.63fF -C1389 la_data_out[99] vdd 0.63fF -C1390 la_data_in[99] vdd 0.63fF -C1391 la_oenb[98] vdd 0.63fF -C1392 la_data_out[98] vdd 0.63fF -C1393 la_data_in[98] vdd 0.63fF -C1394 la_oenb[97] vdd 0.63fF -C1395 la_data_out[97] vdd 0.63fF -C1396 la_data_in[97] vdd 0.63fF -C1397 la_oenb[96] vdd 0.63fF -C1398 la_data_out[96] vdd 0.63fF -C1399 la_data_in[96] vdd 0.63fF -C1400 la_oenb[95] vdd 0.63fF -C1401 la_data_out[95] vdd 0.63fF -C1402 la_data_in[95] vdd 0.63fF -C1403 la_oenb[94] vdd 0.63fF -C1404 la_data_out[94] vdd 0.63fF -C1405 la_data_in[94] vdd 0.63fF -C1406 la_oenb[93] vdd 0.63fF -C1407 la_data_out[93] vdd 0.63fF -C1408 la_data_in[93] vdd 0.63fF -C1409 la_oenb[92] vdd 0.63fF -C1410 la_data_out[92] vdd 0.63fF -C1411 la_data_in[92] vdd 0.63fF -C1412 la_oenb[91] vdd 0.63fF -C1413 la_data_out[91] vdd 0.63fF -C1414 la_data_in[91] vdd 0.63fF -C1415 la_oenb[90] vdd 0.63fF -C1416 la_data_out[90] vdd 0.63fF -C1417 la_data_in[90] vdd 0.63fF -C1418 la_oenb[89] vdd 0.63fF -C1419 la_data_out[89] vdd 0.63fF -C1420 la_data_in[89] vdd 0.63fF -C1421 la_oenb[88] vdd 0.63fF -C1422 la_data_out[88] vdd 0.63fF -C1423 la_data_in[88] vdd 0.63fF -C1424 la_oenb[87] vdd 0.63fF -C1425 la_data_out[87] vdd 0.63fF -C1426 la_data_in[87] vdd 0.63fF -C1427 la_oenb[86] vdd 0.63fF -C1428 la_data_out[86] vdd 0.63fF -C1429 la_data_in[86] vdd 0.63fF -C1430 la_oenb[85] vdd 0.63fF -C1431 la_data_out[85] vdd 0.63fF -C1432 la_data_in[85] vdd 0.63fF -C1433 la_oenb[84] vdd 0.63fF -C1434 la_data_out[84] vdd 0.63fF -C1435 la_data_in[84] vdd 0.63fF -C1436 la_oenb[83] vdd 0.63fF -C1437 la_data_out[83] vdd 0.63fF -C1438 la_data_in[83] vdd 0.63fF -C1439 la_oenb[82] vdd 0.63fF -C1440 la_data_out[82] vdd 0.63fF -C1441 la_data_in[82] vdd 0.63fF -C1442 la_oenb[81] vdd 0.63fF -C1443 la_data_out[81] vdd 0.63fF -C1444 la_data_in[81] vdd 0.63fF -C1445 la_oenb[80] vdd 0.63fF -C1446 la_data_out[80] vdd 0.63fF -C1447 la_data_in[80] vdd 0.63fF -C1448 la_oenb[79] vdd 0.63fF -C1449 la_data_out[79] vdd 0.63fF -C1450 la_data_in[79] vdd 0.63fF -C1451 la_oenb[78] vdd 0.63fF -C1452 la_data_out[78] vdd 0.63fF -C1453 la_data_in[78] vdd 0.63fF -C1454 la_oenb[77] vdd 0.63fF -C1455 la_data_out[77] vdd 0.63fF -C1456 la_data_in[77] vdd 0.63fF -C1457 la_oenb[76] vdd 0.63fF -C1458 la_data_out[76] vdd 0.63fF -C1459 la_data_in[76] vdd 0.63fF -C1460 la_oenb[75] vdd 0.63fF -C1461 la_data_out[75] vdd 0.63fF -C1462 la_data_in[75] vdd 0.63fF -C1463 la_oenb[74] vdd 0.63fF -C1464 la_data_out[74] vdd 0.63fF -C1465 la_data_in[74] vdd 0.63fF -C1466 la_oenb[73] vdd 0.63fF -C1467 la_data_out[73] vdd 0.63fF -C1468 la_data_in[73] vdd 0.63fF -C1469 la_oenb[72] vdd 0.63fF -C1470 la_data_out[72] vdd 0.63fF -C1471 la_data_in[72] vdd 0.63fF -C1472 la_oenb[71] vdd 0.63fF -C1473 la_data_out[71] vdd 0.63fF -C1474 la_data_in[71] vdd 0.63fF -C1475 la_oenb[70] vdd 0.63fF -C1476 la_data_out[70] vdd 0.63fF -C1477 la_data_in[70] vdd 0.63fF -C1478 la_oenb[69] vdd 0.63fF -C1479 la_data_out[69] vdd 0.63fF -C1480 la_data_in[69] vdd 0.63fF -C1481 la_oenb[68] vdd 0.63fF -C1482 la_data_out[68] vdd 0.63fF -C1483 la_data_in[68] vdd 0.63fF -C1484 la_oenb[67] vdd 0.63fF -C1485 la_data_out[67] vdd 0.63fF -C1486 la_data_in[67] vdd 0.63fF -C1487 la_oenb[66] vdd 0.63fF -C1488 la_data_out[66] vdd 0.63fF -C1489 la_data_in[66] vdd 0.63fF -C1490 la_oenb[65] vdd 0.63fF -C1491 la_data_out[65] vdd 0.63fF -C1492 la_data_in[65] vdd 0.63fF -C1493 la_oenb[64] vdd 0.63fF -C1494 la_data_out[64] vdd 0.63fF -C1495 la_data_in[64] vdd 0.63fF -C1496 la_oenb[63] vdd 0.63fF -C1497 la_data_out[63] vdd 0.63fF -C1498 la_data_in[63] vdd 0.63fF -C1499 la_oenb[62] vdd 0.63fF -C1500 la_data_out[62] vdd 0.63fF -C1501 la_data_in[62] vdd 0.63fF -C1502 la_oenb[61] vdd 0.63fF -C1503 la_data_out[61] vdd 0.63fF -C1504 la_data_in[61] vdd 0.63fF -C1505 la_oenb[60] vdd 0.63fF -C1506 la_data_out[60] vdd 0.63fF -C1507 la_data_in[60] vdd 0.63fF -C1508 la_oenb[59] vdd 0.63fF -C1509 la_data_out[59] vdd 0.63fF -C1510 la_data_in[59] vdd 0.63fF -C1511 la_oenb[58] vdd 0.63fF -C1512 la_data_out[58] vdd 0.63fF -C1513 la_data_in[58] vdd 0.63fF -C1514 la_oenb[57] vdd 0.63fF -C1515 la_data_out[57] vdd 0.63fF -C1516 la_data_in[57] vdd 0.63fF -C1517 la_oenb[56] vdd 0.63fF -C1518 la_data_out[56] vdd 0.63fF -C1519 la_data_in[56] vdd 0.63fF -C1520 la_oenb[55] vdd 0.63fF -C1521 la_data_out[55] vdd 0.63fF -C1522 la_data_in[55] vdd 0.63fF -C1523 la_oenb[54] vdd 0.63fF -C1524 la_data_out[54] vdd 0.63fF -C1525 la_data_in[54] vdd 0.63fF -C1526 la_oenb[53] vdd 0.63fF -C1527 la_data_out[53] vdd 0.63fF -C1528 la_data_in[53] vdd 0.63fF -C1529 la_oenb[52] vdd 0.63fF -C1530 la_data_out[52] vdd 0.63fF -C1531 la_data_in[52] vdd 0.63fF -C1532 la_oenb[51] vdd 0.63fF -C1533 la_data_out[51] vdd 0.63fF -C1534 la_data_in[51] vdd 0.63fF -C1535 la_oenb[50] vdd 0.63fF -C1536 la_data_out[50] vdd 0.63fF -C1537 la_data_in[50] vdd 0.63fF -C1538 la_oenb[49] vdd 0.63fF -C1539 la_data_out[49] vdd 0.63fF -C1540 la_data_in[49] vdd 0.63fF -C1541 la_oenb[48] vdd 0.63fF -C1542 la_data_out[48] vdd 0.63fF -C1543 la_data_in[48] vdd 0.63fF -C1544 la_oenb[47] vdd 0.63fF -C1545 la_data_out[47] vdd 0.63fF -C1546 la_data_in[47] vdd 0.63fF -C1547 la_oenb[46] vdd 0.63fF -C1548 la_data_out[46] vdd 0.63fF -C1549 la_data_in[46] vdd 0.63fF -C1550 la_oenb[45] vdd 0.63fF -C1551 la_data_out[45] vdd 0.63fF -C1552 la_data_in[45] vdd 0.63fF -C1553 la_oenb[44] vdd 0.63fF -C1554 la_data_out[44] vdd 0.63fF -C1555 la_data_in[44] vdd 0.63fF -C1556 la_oenb[43] vdd 0.63fF -C1557 la_data_out[43] vdd 0.63fF -C1558 la_data_in[43] vdd 0.63fF -C1559 la_oenb[42] vdd 0.63fF -C1560 la_data_out[42] vdd 0.63fF -C1561 la_data_in[42] vdd 0.63fF -C1562 la_oenb[41] vdd 0.63fF -C1563 la_data_out[41] vdd 0.63fF -C1564 la_data_in[41] vdd 0.63fF -C1565 la_oenb[40] vdd 0.63fF -C1566 la_data_out[40] vdd 0.63fF -C1567 la_data_in[40] vdd 0.63fF -C1568 la_oenb[39] vdd 0.63fF -C1569 la_data_out[39] vdd 0.63fF -C1570 la_data_in[39] vdd 0.63fF -C1571 la_oenb[38] vdd 0.63fF -C1572 la_data_out[38] vdd 0.63fF -C1573 la_data_in[38] vdd 0.63fF -C1574 la_oenb[37] vdd 0.63fF -C1575 la_data_out[37] vdd 0.63fF -C1576 la_data_in[37] vdd 0.63fF -C1577 la_oenb[36] vdd 0.63fF -C1578 la_data_out[36] vdd 0.63fF -C1579 la_data_in[36] vdd 0.63fF -C1580 la_oenb[35] vdd 0.63fF -C1581 la_data_out[35] vdd 0.63fF -C1582 la_data_in[35] vdd 0.63fF -C1583 la_oenb[34] vdd 0.63fF -C1584 la_data_out[34] vdd 0.63fF -C1585 la_data_in[34] vdd 0.63fF -C1586 la_oenb[33] vdd 0.63fF -C1587 la_data_out[33] vdd 0.63fF -C1588 la_data_in[33] vdd 0.63fF -C1589 la_oenb[32] vdd 0.63fF -C1590 la_data_out[32] vdd 0.63fF -C1591 la_data_in[32] vdd 0.63fF -C1592 la_oenb[31] vdd 0.63fF -C1593 la_data_out[31] vdd 0.63fF -C1594 la_data_in[31] vdd 0.63fF -C1595 la_oenb[30] vdd 0.63fF -C1596 la_data_out[30] vdd 0.63fF -C1597 la_data_in[30] vdd 0.63fF -C1598 la_oenb[29] vdd 0.63fF -C1599 la_data_out[29] vdd 0.63fF -C1600 la_data_in[29] vdd 0.63fF -C1601 la_oenb[28] vdd 0.63fF -C1602 la_data_out[28] vdd 0.63fF -C1603 la_data_in[28] vdd 0.63fF -C1604 la_oenb[27] vdd 0.63fF -C1605 la_data_out[27] vdd 0.63fF -C1606 la_data_in[27] vdd 0.63fF -C1607 la_oenb[26] vdd 0.63fF -C1608 la_data_out[26] vdd 0.63fF -C1609 la_data_in[26] vdd 0.63fF -C1610 la_oenb[25] vdd 0.63fF -C1611 la_data_out[25] vdd 0.63fF -C1612 la_data_in[25] vdd 0.63fF -C1613 la_oenb[24] vdd 0.63fF -C1614 la_data_out[24] vdd 0.63fF -C1615 la_data_in[24] vdd 0.63fF -C1616 la_oenb[23] vdd 0.63fF -C1617 la_data_out[23] vdd 0.63fF -C1618 la_data_in[23] vdd 0.63fF -C1619 la_oenb[22] vdd 0.63fF -C1620 la_data_out[22] vdd 0.63fF -C1621 la_data_in[22] vdd 0.63fF -C1622 la_oenb[21] vdd 0.63fF -C1623 la_data_out[21] vdd 0.63fF -C1624 la_data_in[21] vdd 0.63fF -C1625 la_oenb[20] vdd 0.63fF -C1626 la_data_out[20] vdd 0.63fF -C1627 la_data_in[20] vdd 0.63fF -C1628 la_oenb[19] vdd 0.63fF -C1629 la_data_out[19] vdd 0.63fF -C1630 la_data_in[19] vdd 0.63fF -C1631 la_oenb[18] vdd 0.63fF -C1632 la_data_out[18] vdd 0.63fF -C1633 la_data_in[18] vdd 0.63fF -C1634 la_oenb[17] vdd 0.63fF -C1635 la_data_out[17] vdd 0.63fF -C1636 la_data_in[17] vdd 0.63fF -C1637 la_oenb[16] vdd 0.63fF -C1638 la_data_out[16] vdd 0.63fF -C1639 la_data_in[16] vdd 0.63fF -C1640 la_oenb[15] vdd 0.63fF -C1641 la_data_out[15] vdd 0.63fF -C1642 la_data_in[15] vdd 0.63fF -C1643 la_oenb[14] vdd 0.63fF -C1644 la_data_out[14] vdd 0.63fF -C1645 la_data_in[14] vdd 0.63fF -C1646 la_oenb[13] vdd 0.63fF -C1647 la_data_out[13] vdd 0.63fF -C1648 la_data_in[13] vdd 0.63fF -C1649 la_oenb[12] vdd 0.63fF -C1650 la_data_out[12] vdd 0.63fF -C1651 la_data_in[12] vdd 0.63fF -C1652 la_oenb[11] vdd 0.63fF -C1653 la_data_out[11] vdd 0.63fF -C1654 la_data_in[11] vdd 0.63fF -C1655 la_oenb[10] vdd 0.63fF -C1656 la_data_out[10] vdd 0.63fF -C1657 la_data_in[10] vdd 0.63fF -C1658 la_oenb[9] vdd 0.63fF -C1659 la_data_out[9] vdd 0.63fF -C1660 la_data_in[9] vdd 0.63fF -C1661 la_oenb[8] vdd 0.63fF -C1662 la_data_out[8] vdd 0.63fF -C1663 la_data_in[8] vdd 0.63fF -C1664 la_oenb[7] vdd 0.63fF -C1665 la_data_out[7] vdd 0.63fF -C1666 la_data_in[7] vdd 0.63fF -C1667 la_oenb[6] vdd 0.63fF -C1668 la_data_out[6] vdd 0.63fF -C1669 la_data_in[6] vdd 0.63fF -C1670 la_oenb[5] vdd 0.63fF -C1671 la_data_out[5] vdd 0.63fF -C1672 la_data_in[5] vdd 0.63fF -C1673 la_oenb[4] vdd 0.63fF -C1674 la_data_out[4] vdd 0.63fF -C1675 la_data_in[4] vdd 0.63fF -C1676 la_oenb[3] vdd 0.63fF -C1677 la_data_out[3] vdd 0.63fF -C1678 la_data_in[3] vdd 0.63fF -C1679 la_oenb[2] vdd 0.63fF -C1680 la_data_out[2] vdd 0.63fF -C1681 la_data_in[2] vdd 0.63fF -C1682 la_oenb[1] vdd 0.63fF -C1683 la_data_out[1] vdd 0.63fF -C1684 la_data_in[1] vdd 0.63fF -C1685 la_oenb[0] vdd 0.63fF -C1686 la_data_out[0] vdd 0.63fF -C1687 la_data_in[0] vdd 0.63fF -C1688 wbs_dat_o[31] vdd 0.63fF -C1689 wbs_dat_i[31] vdd 0.63fF -C1690 wbs_adr_i[31] vdd 0.63fF -C1691 wbs_dat_o[30] vdd 0.63fF -C1692 wbs_dat_i[30] vdd 0.63fF -C1693 wbs_adr_i[30] vdd 0.63fF -C1694 wbs_dat_o[29] vdd 0.63fF -C1695 wbs_dat_i[29] vdd 0.63fF -C1696 wbs_adr_i[29] vdd 0.63fF -C1697 wbs_dat_o[28] vdd 0.63fF -C1698 wbs_dat_i[28] vdd 0.63fF -C1699 wbs_adr_i[28] vdd 0.63fF -C1700 wbs_dat_o[27] vdd 0.63fF -C1701 wbs_dat_i[27] vdd 0.63fF -C1702 wbs_adr_i[27] vdd 0.63fF -C1703 wbs_dat_o[26] vdd 0.63fF -C1704 wbs_dat_i[26] vdd 0.63fF -C1705 wbs_adr_i[26] vdd 0.63fF -C1706 wbs_dat_o[25] vdd 0.63fF -C1707 wbs_dat_i[25] vdd 0.63fF -C1708 wbs_adr_i[25] vdd 0.63fF -C1709 wbs_dat_o[24] vdd 0.63fF -C1710 wbs_dat_i[24] vdd 0.63fF -C1711 wbs_adr_i[24] vdd 0.63fF -C1712 wbs_dat_o[23] vdd 0.63fF -C1713 wbs_dat_i[23] vdd 0.63fF -C1714 wbs_adr_i[23] vdd 0.63fF -C1715 wbs_dat_o[22] vdd 0.63fF -C1716 wbs_dat_i[22] vdd 0.63fF -C1717 wbs_adr_i[22] vdd 0.63fF -C1718 wbs_dat_o[21] vdd 0.63fF -C1719 wbs_dat_i[21] vdd 0.63fF -C1720 wbs_adr_i[21] vdd 0.63fF -C1721 wbs_dat_o[20] vdd 0.63fF -C1722 wbs_dat_i[20] vdd 0.63fF -C1723 wbs_adr_i[20] vdd 0.63fF -C1724 wbs_dat_o[19] vdd 0.63fF -C1725 wbs_dat_i[19] vdd 0.63fF -C1726 wbs_adr_i[19] vdd 0.63fF -C1727 wbs_dat_o[18] vdd 0.63fF -C1728 wbs_dat_i[18] vdd 0.63fF -C1729 wbs_adr_i[18] vdd 0.63fF -C1730 wbs_dat_o[17] vdd 0.63fF -C1731 wbs_dat_i[17] vdd 0.63fF -C1732 wbs_adr_i[17] vdd 0.63fF -C1733 wbs_dat_o[16] vdd 0.63fF -C1734 wbs_dat_i[16] vdd 0.63fF -C1735 wbs_adr_i[16] vdd 0.63fF -C1736 wbs_dat_o[15] vdd 0.63fF -C1737 wbs_dat_i[15] vdd 0.63fF -C1738 wbs_adr_i[15] vdd 0.63fF -C1739 wbs_dat_o[14] vdd 0.63fF -C1740 wbs_dat_i[14] vdd 0.63fF -C1741 wbs_adr_i[14] vdd 0.63fF -C1742 wbs_dat_o[13] vdd 0.63fF -C1743 wbs_dat_i[13] vdd 0.63fF -C1744 wbs_adr_i[13] vdd 0.63fF -C1745 wbs_dat_o[12] vdd 0.63fF -C1746 wbs_dat_i[12] vdd 0.63fF -C1747 wbs_adr_i[12] vdd 0.63fF -C1748 wbs_dat_o[11] vdd 0.63fF -C1749 wbs_dat_i[11] vdd 0.63fF -C1750 wbs_adr_i[11] vdd 0.63fF -C1751 wbs_dat_o[10] vdd 0.63fF -C1752 wbs_dat_i[10] vdd 0.63fF -C1753 wbs_adr_i[10] vdd 0.63fF -C1754 wbs_dat_o[9] vdd 0.63fF -C1755 wbs_dat_i[9] vdd 0.63fF -C1756 wbs_adr_i[9] vdd 0.63fF -C1757 wbs_dat_o[8] vdd 0.63fF -C1758 wbs_dat_i[8] vdd 0.63fF -C1759 wbs_adr_i[8] vdd 0.63fF -C1760 wbs_dat_o[7] vdd 0.63fF -C1761 wbs_dat_i[7] vdd 0.63fF -C1762 wbs_adr_i[7] vdd 0.63fF -C1763 wbs_dat_o[6] vdd 0.63fF -C1764 wbs_dat_i[6] vdd 0.63fF -C1765 wbs_adr_i[6] vdd 0.63fF -C1766 wbs_dat_o[5] vdd 0.63fF -C1767 wbs_dat_i[5] vdd 0.63fF -C1768 wbs_adr_i[5] vdd 0.63fF -C1769 wbs_dat_o[4] vdd 0.63fF -C1770 wbs_dat_i[4] vdd 0.63fF -C1771 wbs_adr_i[4] vdd 0.63fF -C1772 wbs_sel_i[3] vdd 0.63fF -C1773 wbs_dat_o[3] vdd 0.63fF -C1774 wbs_dat_i[3] vdd 0.63fF -C1775 wbs_adr_i[3] vdd 0.63fF -C1776 wbs_sel_i[2] vdd 0.63fF -C1777 wbs_dat_o[2] vdd 0.63fF -C1778 wbs_dat_i[2] vdd 0.63fF -C1779 wbs_adr_i[2] vdd 0.63fF -C1780 wbs_sel_i[1] vdd 0.63fF -C1781 wbs_dat_o[1] vdd 0.63fF -C1782 wbs_dat_i[1] vdd 0.63fF -C1783 wbs_adr_i[1] vdd 0.63fF -C1784 wbs_sel_i[0] vdd 0.63fF -C1785 wbs_dat_o[0] vdd 0.63fF -C1786 wbs_dat_i[0] vdd 0.63fF -C1787 wbs_adr_i[0] vdd 0.63fF -C1788 wbs_we_i vdd 0.63fF -C1789 wbs_stb_i vdd 0.63fF -C1790 wbs_cyc_i vdd 0.63fF -C1791 wbs_ack_o vdd 0.63fF -C1792 wb_rst_i vdd 0.63fF -C1793 wb_clk_i vdd 0.63fF -C1794 pll_full_0/divider_0/and_0/Z1 vdd 0.65fF -C1795 pll_full_0/divider_0/and_0/B vdd 2.45fF -C1796 pll_full_0/divider_0/and_0/A vdd 2.35fF -C1797 pll_full_0/divider_0/and_0/out1 vdd 2.99fF -C1798 pll_full_0/divider_0/tspc_2/Z4 vdd 0.86fF -C1799 pll_full_0/divbuf_0/IN vdd 9.95fF -C1800 pll_full_0/divider_0/tspc_2/Z3 vdd 2.26fF -C1801 pll_full_0/divider_0/tspc_2/Z2 vdd 1.46fF -C1802 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF -C1803 pll_full_0/divider_0/nor_0/B vdd 6.48fF -C1804 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C1805 pll_full_0/divider_0/tspc_1/Z4 vdd 0.86fF -C1806 pll_full_0/divider_0/tspc_1/Q vdd 3.12fF -C1807 pll_full_0/divider_0/tspc_1/Z3 vdd 2.26fF -C1808 pll_full_0/divider_0/tspc_1/Z2 vdd 1.46fF -C1809 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF -C1810 pll_full_0/divider_0/nor_1/B vdd 7.12fF -C1811 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C1812 pll_full_0/divider_0/tspc_0/Z4 vdd 0.86fF -C1813 pll_full_0/divider_0/tspc_0/Q vdd 3.14fF -C1814 pll_full_0/divider_0/tspc_0/Z3 vdd 2.26fF -C1815 pll_full_0/divider_0/tspc_0/Z2 vdd 1.46fF -C1816 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF -C1817 pll_full_0/divider_0/nor_1/A vdd 7.08fF -C1818 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C1819 pll_full_0/divider_0/clk vdd 31.85fF -C1820 pll_full_0/divider_0/prescaler_0/Out vdd 4.59fF -C1821 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C1822 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C1823 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C1824 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C1825 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C1826 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C1827 pll_full_0/divider_0/and_0/OUT vdd 5.67fF -C1828 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C1829 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C1830 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C1831 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C1832 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C1833 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C1834 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C1835 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C1836 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C1837 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C1838 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C1839 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C1840 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C1841 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C1842 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.19fF -C1843 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C1844 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.47fF **FLOATING -C1845 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C1846 pll_full_0/divider_0/nor_1/Z1 vdd 1.34fF -C1847 pll_full_0/divider_0/nor_0/Z1 vdd 1.34fF -C1848 pll_full_0/divbuf_1/OUT vdd 363.82fF -C1849 pll_full_0/divbuf_1/OUT5 vdd 350.37fF -C1850 pll_full_0/divbuf_1/OUT4 vdd 133.72fF -C1851 pll_full_0/divbuf_1/OUT3 vdd 34.03fF -C1852 pll_full_0/divbuf_1/OUT2 vdd 8.71fF -C1853 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C1854 pll_full_0/divbuf_0/OUT5 vdd 350.37fF -C1855 pll_full_0/divbuf_0/OUT4 vdd 133.72fF -C1856 pll_full_0/divbuf_0/OUT3 vdd 34.03fF -C1857 pll_full_0/divbuf_0/OUT2 vdd 8.71fF -C1858 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C1859 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF -C1860 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C1861 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C1862 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C1863 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C1864 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C1865 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C1866 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C1867 pll_full_0/ro_complete_0/a0 vdd 7.88fF -C1868 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C1869 pll_full_0/ro_complete_0/a1 vdd 5.39fF -C1870 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C1871 pll_full_0/ro_complete_0/a3 vdd 6.85fF -C1872 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C1873 pll_full_0/ro_complete_0/a2 vdd 5.48fF -C1874 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C1875 pll_full_0/ro_complete_0/a4 vdd 5.36fF -C1876 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C1877 pll_full_0/ro_complete_0/a5 vdd 5.19fF -C1878 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF -C1879 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C1880 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C1881 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C1882 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C1883 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C1884 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C1885 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C1886 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING -C1887 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING -C1888 pll_full_0/cp_0/down vdd 1.54fF -C1889 pll_full_0/cp_0/upbar vdd 1.79fF -C1890 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C1891 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C1892 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING -C1893 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING -C1894 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING -C1895 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING -C1896 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF -C1897 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF -C1898 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF -C1899 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF -C1900 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF -C1901 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF -C1902 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF -C1903 pll_full_0/pd_0/UP vdd 6.61fF -C1904 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C1905 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF -C1906 pll_full_0/pd_0/REF vdd 6.44fF -C1907 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF -C1908 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF -C1909 pll_full_0/pd_0/R vdd 3.05fF -C1910 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF -C1911 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF -C1912 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF -C1913 pll_full_0/pd_0/DOWN vdd 7.24fF -C1914 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C1915 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF -C1916 pll_full_0/pd_0/DIV vdd 371.87fF -C1917 divider_0/and_0/Z1 vdd 0.74fF -C1918 divider_0/and_0/B vdd 2.25fF -C1919 divider_0/and_0/A vdd 2.19fF -C1920 divider_0/and_0/out1 vdd 2.93fF -C1921 divider_0/tspc_2/Z4 vdd 0.86fF -C1922 divider_0/Out vdd 1.60fF -C1923 divider_0/tspc_2/Z3 vdd 2.26fF -C1924 divider_0/tspc_2/Z2 vdd 1.46fF -C1925 divider_0/tspc_2/Z1 vdd 0.99fF -C1926 divider_0/nor_0/B vdd 6.33fF -C1927 divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C1928 divider_0/tspc_1/Z4 vdd 0.86fF -C1929 divider_0/tspc_1/Q vdd 3.12fF -C1930 divider_0/tspc_1/Z3 vdd 2.26fF -C1931 divider_0/tspc_1/Z2 vdd 1.46fF -C1932 divider_0/tspc_1/Z1 vdd 0.99fF -C1933 divider_0/nor_1/B vdd 7.05fF -C1934 divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C1935 divider_0/tspc_0/Z4 vdd 0.86fF -C1936 divider_0/tspc_0/Q vdd 3.14fF -C1937 divider_0/tspc_0/Z3 vdd 2.26fF -C1938 divider_0/tspc_0/Z2 vdd 1.46fF -C1939 divider_0/tspc_0/Z1 vdd 0.99fF -C1940 divider_0/nor_1/A vdd 7.04fF -C1941 divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C1942 divider_0/clk vdd 5.63fF -C1943 divider_0/prescaler_0/Out vdd 4.59fF -C1944 divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C1945 divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C1946 divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C1947 divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C1948 divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C1949 divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C1950 divider_0/and_0/OUT vdd 5.62fF -C1951 divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C1952 divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C1953 divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C1954 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C1955 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C1956 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C1957 divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C1958 divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C1959 divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C1960 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C1961 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C1962 divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C1963 divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C1964 divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C1965 divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF -C1966 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C1967 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING -C1968 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C1969 divider_0/nor_1/Z1 vdd 1.34fF -C1970 divider_0/nor_0/Z1 vdd 1.34fF -C1971 divider_0/mc2 vdd 5.29fF -C1972 divbuf_7/OUT vdd 363.82fF -C1973 divbuf_7/OUT5 vdd 350.37fF -C1974 divbuf_7/OUT4 vdd 133.72fF -C1975 divbuf_7/OUT3 vdd 34.03fF -C1976 divbuf_7/OUT2 vdd 8.71fF -C1977 divbuf_7/IN vdd 0.89fF -C1978 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING -C1979 divbuf_6/OUT vdd 363.82fF -C1980 divbuf_6/OUT5 vdd 350.37fF -C1981 divbuf_6/OUT4 vdd 133.72fF -C1982 divbuf_6/OUT3 vdd 34.03fF -C1983 divbuf_6/OUT2 vdd 8.71fF -C1984 divbuf_6/IN vdd 0.89fF -C1985 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING -C1986 divbuf_5/OUT vdd 363.82fF -C1987 divbuf_5/OUT5 vdd 350.37fF -C1988 divbuf_5/OUT4 vdd 133.72fF -C1989 divbuf_5/OUT3 vdd 34.03fF -C1990 divbuf_5/OUT2 vdd 8.71fF -C1991 divbuf_5/IN vdd 0.89fF -C1992 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING -C1993 divbuf_4/OUT vdd 363.82fF -C1994 divbuf_4/OUT5 vdd 350.37fF -C1995 divbuf_4/OUT4 vdd 133.72fF -C1996 divbuf_4/OUT3 vdd 34.03fF -C1997 divbuf_4/OUT2 vdd 8.71fF -C1998 divbuf_4/IN vdd 0.89fF -C1999 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING -C2000 divbuf_3/OUT vdd 363.82fF -C2001 divbuf_3/OUT5 vdd 350.37fF -C2002 divbuf_3/OUT4 vdd 133.72fF -C2003 divbuf_3/OUT3 vdd 34.03fF -C2004 divbuf_3/OUT2 vdd 8.71fF -C2005 divbuf_3/IN vdd 0.89fF -C2006 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING -C2007 divbuf_2/OUT vdd 363.82fF -C2008 divbuf_2/OUT5 vdd 350.37fF -C2009 divbuf_2/OUT4 vdd 133.72fF -C2010 divbuf_2/OUT3 vdd 34.03fF -C2011 divbuf_2/OUT2 vdd 8.71fF -C2012 divbuf_2/IN vdd 0.89fF -C2013 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING -C2014 divbuf_1/OUT vdd 363.82fF -C2015 divbuf_1/OUT5 vdd 350.37fF -C2016 divbuf_1/OUT4 vdd 133.72fF -C2017 divbuf_1/OUT3 vdd 34.03fF -C2018 divbuf_1/OUT2 vdd 8.71fF -C2019 divbuf_1/IN vdd 0.89fF -C2020 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING -C2021 divbuf_0/OUT vdd 363.82fF -C2022 divbuf_0/OUT5 vdd 350.37fF -C2023 divbuf_0/OUT4 vdd 133.72fF -C2024 divbuf_0/OUT3 vdd 34.03fF -C2025 divbuf_0/OUT2 vdd 8.71fF -C2026 divbuf_0/IN vdd 0.89fF -C2027 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING -C2028 ro_complete_0/cbank_2/v vdd 17.84fF -C2029 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C2030 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C2031 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C2032 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C2033 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C2034 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C2035 ro_complete_0/cbank_1/v vdd 16.34fF -C2036 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C2037 ro_complete_0/a0 vdd 7.88fF -C2038 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C2039 ro_complete_0/a1 vdd 5.39fF -C2040 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C2041 ro_complete_0/a3 vdd 6.85fF -C2042 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C2043 ro_complete_0/a2 vdd 5.48fF -C2044 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C2045 ro_complete_0/a4 vdd 5.36fF -C2046 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C2047 ro_complete_0/a5 vdd 5.19fF -C2048 ro_complete_0/cbank_0/v vdd 14.98fF -C2049 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C2050 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C2051 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C2052 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C2053 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C2054 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C2055 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C2056 filter_0/v vdd 85.69fF -C2057 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING -C2058 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING -C2059 cp_0/down vdd 1.54fF -C2060 cp_0/vbias vdd 2.41fF -C2061 cp_0/out vdd 5.26fF -C2062 cp_0/upbar vdd 1.50fF -C2063 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING -C2064 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING -C2065 cp_0/a_7110_0# vdd 0.17fF **FLOATING -C2066 cp_0/a_6370_0# vdd 0.40fF **FLOATING -C2067 cp_0/a_3060_0# vdd 1.65fF **FLOATING -C2068 cp_0/a_1710_0# vdd 5.76fF **FLOATING -C2069 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING -C2070 cp_0/a_10_n50# vdd 2.96fF **FLOATING -C2071 ro_div_new_0/divider_0/and_0/Z1 vdd 0.74fF -C2072 ro_div_new_0/divider_0/and_0/B vdd 2.25fF -C2073 ro_div_new_0/divider_0/and_0/A vdd 2.19fF -C2074 ro_div_new_0/divider_0/and_0/out1 vdd 2.93fF -C2075 ro_div_new_0/divider_0/tspc_2/Z4 vdd 0.86fF -C2076 ro_div_new_0/divider_0/Out vdd 1.60fF -C2077 ro_div_new_0/divider_0/tspc_2/Z3 vdd 2.26fF -C2078 ro_div_new_0/divider_0/tspc_2/Z2 vdd 1.46fF -C2079 ro_div_new_0/divider_0/tspc_2/Z1 vdd 0.99fF -C2080 ro_div_new_0/divider_0/nor_0/B vdd 6.33fF -C2081 ro_div_new_0/divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING -C2082 ro_div_new_0/divider_0/tspc_1/Z4 vdd 0.86fF -C2083 ro_div_new_0/divider_0/tspc_1/Q vdd 3.12fF -C2084 ro_div_new_0/divider_0/tspc_1/Z3 vdd 2.26fF -C2085 ro_div_new_0/divider_0/tspc_1/Z2 vdd 1.46fF -C2086 ro_div_new_0/divider_0/tspc_1/Z1 vdd 0.99fF -C2087 ro_div_new_0/divider_0/nor_1/B vdd 7.05fF -C2088 ro_div_new_0/divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING -C2089 ro_div_new_0/divider_0/tspc_0/Z4 vdd 0.86fF -C2090 ro_div_new_0/divider_0/tspc_0/Q vdd 3.14fF -C2091 ro_div_new_0/divider_0/tspc_0/Z3 vdd 2.26fF -C2092 ro_div_new_0/divider_0/tspc_0/Z2 vdd 1.46fF -C2093 ro_div_new_0/divider_0/tspc_0/Z1 vdd 0.99fF -C2094 ro_div_new_0/divider_0/nor_1/A vdd 7.04fF -C2095 ro_div_new_0/divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING -C2096 ro_div_new_0/divider_0/clk vdd 23.62fF -C2097 ro_div_new_0/divider_0/prescaler_0/Out vdd 4.59fF -C2098 ro_div_new_0/divider_0/prescaler_0/nand_1/z1 vdd 0.36fF -C2099 ro_div_new_0/divider_0/prescaler_0/tspc_2/D vdd 2.64fF -C2100 ro_div_new_0/divider_0/prescaler_0/tspc_0/Q vdd 3.64fF -C2101 ro_div_new_0/divider_0/prescaler_0/tspc_1/Q vdd 3.61fF -C2102 ro_div_new_0/divider_0/prescaler_0/nand_0/z1 vdd 0.36fF -C2103 ro_div_new_0/divider_0/prescaler_0/tspc_0/D vdd 3.12fF -C2104 ro_div_new_0/divider_0/and_0/OUT vdd 5.62fF -C2105 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF -C2106 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF -C2107 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF -C2108 ro_div_new_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF -C2109 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING -C2110 ro_div_new_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING -C2111 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF -C2112 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF -C2113 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF -C2114 ro_div_new_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF -C2115 ro_div_new_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING -C2116 ro_div_new_0/divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING -C2117 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF -C2118 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF -C2119 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF -C2120 ro_div_new_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF -C2121 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING -C2122 ro_div_new_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING -C2123 ro_div_new_0/divider_0/nor_1/Z1 vdd 1.34fF -C2124 ro_div_new_0/divider_0/nor_0/Z1 vdd 1.34fF -C2125 ro_div_new_0/divider_0/mc2 vdd 5.29fF -C2126 ro_div_new_0/ro_complete_0/cbank_2/v vdd 17.84fF -C2127 ro_div_new_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF -C2128 ro_div_new_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF -C2129 ro_div_new_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF -C2130 ro_div_new_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF -C2131 ro_div_new_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF -C2132 ro_div_new_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF -C2133 ro_div_new_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF -C2134 ro_div_new_0/ro_complete_0/a0 vdd 7.88fF -C2135 ro_div_new_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF -C2136 ro_div_new_0/ro_complete_0/a1 vdd 5.39fF -C2137 ro_div_new_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF -C2138 ro_div_new_0/ro_complete_0/a3 vdd 6.85fF -C2139 ro_div_new_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF -C2140 ro_div_new_0/ro_complete_0/a2 vdd 5.48fF -C2141 ro_div_new_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF -C2142 ro_div_new_0/ro_complete_0/a4 vdd 5.36fF -C2143 ro_div_new_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF -C2144 ro_div_new_0/ro_complete_0/a5 vdd 5.19fF -C2145 ro_div_new_0/ro_complete_0/cbank_0/v vdd 14.98fF -C2146 ro_div_new_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF -C2147 ro_div_new_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF -C2148 ro_div_new_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF -C2149 ro_div_new_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF -C2150 ro_div_new_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF -C2151 ro_div_new_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF -C2152 ro_div_new_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF -C2153 pd_0/and_pd_0/Z1 vdd 0.39fF -C2154 pd_0/and_pd_0/Out1 vdd 2.22fF -C2155 pd_0/tspc_r_1/z5 vdd 1.10fF -C2156 pd_0/tspc_r_1/Z4 vdd 1.07fF -C2157 pd_0/tspc_r_1/Qbar vdd 0.88fF -C2158 pd_0/tspc_r_1/Z2 vdd 1.22fF -C2159 pd_0/tspc_r_1/Z1 vdd 0.67fF -C2160 pd_0/UP vdd 2.21fF -C2161 pd_0/tspc_r_1/Qbar1 vdd 1.34fF -C2162 pd_0/tspc_r_1/Z3 vdd 2.12fF -C2163 pd_0/REF vdd 1.80fF -C2164 pd_0/tspc_r_0/z5 vdd 1.10fF -C2165 pd_0/tspc_r_0/Z4 vdd 1.07fF -C2166 pd_0/R vdd 3.05fF -C2167 pd_0/tspc_r_0/Qbar vdd 0.79fF -C2168 pd_0/tspc_r_0/Z2 vdd 1.22fF -C2169 pd_0/tspc_r_0/Z1 vdd 0.67fF -C2170 pd_0/DOWN vdd 3.08fF -C2171 pd_0/tspc_r_0/Qbar1 vdd 1.34fF -C2172 pd_0/tspc_r_0/Z3 vdd 2.12fF -C2173 pd_0/DIV vdd 1.82fF +C850 io_analog[4] vdd 43.96fF +C851 io_analog[5] vdd 44.13fF +C852 io_analog[6] vdd 43.46fF +C853 io_in_3v3[0] vdd 0.61fF +C854 io_oeb[26] vdd 0.61fF +C855 io_in[0] vdd 0.61fF +C856 io_out[26] vdd 0.61fF +C857 io_out[0] vdd 0.61fF +C858 io_in[26] vdd 0.61fF +C859 io_oeb[0] vdd 0.61fF +C860 io_in_3v3[26] vdd 0.61fF +C861 io_in_3v3[1] vdd 0.61fF +C862 io_oeb[25] vdd 0.61fF +C863 io_in[1] vdd 0.61fF +C864 io_out[25] vdd 0.61fF +C865 io_out[1] vdd 0.61fF +C866 io_in[25] vdd 0.61fF +C867 io_oeb[1] vdd 0.61fF +C868 io_in_3v3[25] vdd 0.61fF +C869 io_in_3v3[2] vdd 0.61fF +C870 io_oeb[24] vdd 0.61fF +C871 io_in[2] vdd 0.61fF +C872 io_out[24] vdd 0.61fF +C873 io_out[2] vdd 0.61fF +C874 io_in[24] vdd 0.61fF +C875 io_oeb[2] vdd 0.61fF +C876 io_in_3v3[24] vdd 0.61fF +C877 io_in_3v3[3] vdd 0.61fF +C878 gpio_noesd[17] vdd 0.61fF +C879 io_in[3] vdd 0.61fF +C880 gpio_analog[17] vdd 0.61fF +C881 io_out[3] vdd 0.61fF +C882 io_oeb[3] vdd 0.61fF +C883 io_in_3v3[4] vdd 0.61fF +C884 io_in[4] vdd 0.61fF +C885 io_out[4] vdd 0.61fF +C886 io_oeb[4] vdd 0.61fF +C887 io_oeb[23] vdd 0.61fF +C888 io_out[23] vdd 0.61fF +C889 io_in[23] vdd 0.61fF +C890 io_in_3v3[23] vdd 0.61fF +C891 gpio_noesd[16] vdd 0.61fF +C892 gpio_analog[16] vdd 0.61fF +C893 io_in_3v3[5] vdd 0.61fF +C894 io_in[5] vdd 0.61fF +C895 io_out[5] vdd 0.61fF +C896 io_oeb[5] vdd 0.61fF +C897 io_oeb[22] vdd 0.61fF +C898 io_out[22] vdd 0.61fF +C899 io_in[22] vdd 0.61fF +C900 io_in_3v3[22] vdd 0.61fF +C901 gpio_noesd[15] vdd 0.61fF +C902 gpio_analog[15] vdd 0.61fF +C903 io_in_3v3[6] vdd 0.61fF +C904 io_in[6] vdd 0.61fF +C905 io_out[6] vdd 0.61fF +C906 io_oeb[6] vdd 0.61fF +C907 io_oeb[21] vdd 0.61fF +C908 io_out[21] vdd 0.61fF +C909 io_in[21] vdd 0.61fF +C910 io_in_3v3[21] vdd 0.61fF +C911 gpio_noesd[14] vdd 0.61fF +C912 gpio_analog[14] vdd 0.61fF +C913 vssa1 vdd 38.21fF +C914 vssd2 vdd 13.04fF +C915 vssd1 vdd 13.04fF +C916 vdda2 vdd 13.04fF +C917 vdda1 vdd 26.08fF +C918 io_oeb[20] vdd 0.61fF +C919 io_out[20] vdd 0.61fF +C920 io_in[20] vdd 0.61fF +C921 io_in_3v3[20] vdd 0.61fF +C922 gpio_noesd[13] vdd 0.61fF +C923 gpio_analog[13] vdd 0.61fF +C924 gpio_analog[0] vdd 0.61fF +C925 gpio_noesd[0] vdd 0.61fF +C926 io_in_3v3[7] vdd 0.61fF +C927 io_in[7] vdd 0.61fF +C928 io_out[7] vdd 0.61fF +C929 io_oeb[7] vdd 0.61fF +C930 io_oeb[19] vdd 0.61fF +C931 io_out[19] vdd 0.61fF +C932 io_in[19] vdd 0.61fF +C933 io_in_3v3[19] vdd 0.61fF +C934 gpio_noesd[12] vdd 0.61fF +C935 gpio_analog[12] vdd 0.61fF +C936 gpio_analog[1] vdd 0.61fF +C937 gpio_noesd[1] vdd 0.61fF +C938 io_in_3v3[8] vdd 0.61fF +C939 io_in[8] vdd 0.61fF +C940 io_out[8] vdd 0.61fF +C941 io_oeb[8] vdd 0.61fF +C942 io_oeb[18] vdd 0.61fF +C943 io_out[18] vdd 0.61fF +C944 io_in[18] vdd 0.61fF +C945 io_in_3v3[18] vdd 0.61fF +C946 gpio_noesd[11] vdd 0.61fF +C947 gpio_analog[11] vdd 0.61fF +C948 gpio_analog[2] vdd 0.61fF +C949 gpio_noesd[2] vdd 0.61fF +C950 io_in_3v3[9] vdd 0.61fF +C951 io_in[9] vdd 0.61fF +C952 io_out[9] vdd 0.61fF +C953 io_oeb[9] vdd 0.61fF +C954 io_oeb[17] vdd 0.61fF +C955 io_out[17] vdd 0.61fF +C956 io_in[17] vdd 0.61fF +C957 io_in_3v3[17] vdd 0.61fF +C958 gpio_noesd[10] vdd 0.61fF +C959 gpio_analog[10] vdd 0.61fF +C960 gpio_analog[3] vdd 0.61fF +C961 gpio_noesd[3] vdd 0.61fF +C962 io_in_3v3[10] vdd 0.61fF +C963 io_in[10] vdd 0.61fF +C964 io_out[10] vdd 0.61fF +C965 io_oeb[10] vdd 0.61fF +C966 io_oeb[16] vdd 0.61fF +C967 io_out[16] vdd 0.61fF +C968 io_in[16] vdd 0.61fF +C969 io_in_3v3[16] vdd 0.61fF +C970 gpio_noesd[9] vdd 0.61fF +C971 gpio_analog[9] vdd 0.61fF +C972 gpio_analog[4] vdd 0.61fF +C973 gpio_noesd[4] vdd 0.61fF +C974 io_in_3v3[11] vdd 0.61fF +C975 io_in[11] vdd 0.61fF +C976 io_out[11] vdd 0.61fF +C977 io_oeb[11] vdd 0.61fF +C978 io_oeb[15] vdd 0.61fF +C979 io_out[15] vdd 0.61fF +C980 io_in[15] vdd 0.61fF +C981 io_in_3v3[15] vdd 0.61fF +C982 gpio_noesd[8] vdd 0.61fF +C983 gpio_analog[8] vdd 0.61fF +C984 gpio_analog[5] vdd 0.61fF +C985 gpio_noesd[5] vdd 0.61fF +C986 io_in_3v3[12] vdd 0.61fF +C987 io_in[12] vdd 0.61fF +C988 io_out[12] vdd 0.61fF +C989 io_oeb[12] vdd 0.61fF +C990 io_oeb[14] vdd 0.61fF +C991 io_out[14] vdd 0.61fF +C992 io_in[14] vdd 0.61fF +C993 io_in_3v3[14] vdd 0.61fF +C994 gpio_noesd[7] vdd 0.61fF +C995 gpio_analog[7] vdd 0.61fF +C996 vssa2 vdd 13.04fF +C997 gpio_analog[6] vdd 0.61fF +C998 gpio_noesd[6] vdd 0.61fF +C999 io_in_3v3[13] vdd 0.61fF +C1000 io_in[13] vdd 0.61fF +C1001 io_out[13] vdd 0.61fF +C1002 io_oeb[13] vdd 0.61fF +C1003 vccd1 vdd 13.04fF +C1004 vccd2 vdd 13.04fF +C1005 io_analog[0] vdd 6.83fF +C1006 io_analog[10] vdd 6.83fF +C1007 io_analog[1] vdd 13.17fF +C1008 io_analog[2] vdd 12.57fF +C1009 io_analog[3] vdd 12.83fF +C1010 io_clamp_high[0] vdd 3.58fF +C1011 io_clamp_low[0] vdd 3.58fF +C1012 io_clamp_high[1] vdd 3.58fF +C1013 io_clamp_low[1] vdd 3.58fF +C1014 io_clamp_high[2] vdd 3.58fF +C1015 io_clamp_low[2] vdd 3.58fF +C1016 io_analog[7] vdd 12.74fF +C1017 io_analog[8] vdd 13.08fF +C1018 io_analog[9] vdd 13.08fF +C1019 user_irq[2] vdd 0.63fF +C1020 user_irq[1] vdd 0.63fF +C1021 user_irq[0] vdd 0.63fF +C1022 user_clock2 vdd 0.63fF +C1023 la_oenb[127] vdd 0.63fF +C1024 la_data_out[127] vdd 0.63fF +C1025 la_data_in[127] vdd 0.63fF +C1026 la_oenb[126] vdd 0.63fF +C1027 la_data_out[126] vdd 0.63fF +C1028 la_data_in[126] vdd 0.63fF +C1029 la_oenb[125] vdd 0.63fF +C1030 la_data_out[125] vdd 0.63fF +C1031 la_data_in[125] vdd 0.63fF +C1032 la_oenb[124] vdd 0.63fF +C1033 la_data_out[124] vdd 0.63fF +C1034 la_data_in[124] vdd 0.63fF +C1035 la_oenb[123] vdd 0.63fF +C1036 la_data_out[123] vdd 0.63fF +C1037 la_data_in[123] vdd 0.63fF +C1038 la_oenb[122] vdd 0.63fF +C1039 la_data_out[122] vdd 0.63fF +C1040 la_data_in[122] vdd 0.63fF +C1041 la_oenb[121] vdd 0.63fF +C1042 la_data_out[121] vdd 0.63fF +C1043 la_data_in[121] vdd 0.63fF +C1044 la_oenb[120] vdd 0.63fF +C1045 la_data_out[120] vdd 0.63fF +C1046 la_data_in[120] vdd 0.63fF +C1047 la_oenb[119] vdd 0.63fF +C1048 la_data_out[119] vdd 0.63fF +C1049 la_data_in[119] vdd 0.63fF +C1050 la_oenb[118] vdd 0.63fF +C1051 la_data_out[118] vdd 0.63fF +C1052 la_data_in[118] vdd 0.63fF +C1053 la_oenb[117] vdd 0.63fF +C1054 la_data_out[117] vdd 0.63fF +C1055 la_data_in[117] vdd 0.63fF +C1056 la_oenb[116] vdd 0.63fF +C1057 la_data_out[116] vdd 0.63fF +C1058 la_data_in[116] vdd 0.63fF +C1059 la_oenb[115] vdd 0.63fF +C1060 la_data_out[115] vdd 0.63fF +C1061 la_data_in[115] vdd 0.63fF +C1062 la_oenb[114] vdd 0.63fF +C1063 la_data_out[114] vdd 0.63fF +C1064 la_data_in[114] vdd 0.63fF +C1065 la_oenb[113] vdd 0.63fF +C1066 la_data_out[113] vdd 0.63fF +C1067 la_data_in[113] vdd 0.63fF +C1068 la_oenb[112] vdd 0.63fF +C1069 la_data_out[112] vdd 0.63fF +C1070 la_data_in[112] vdd 0.63fF +C1071 la_oenb[111] vdd 0.63fF +C1072 la_data_out[111] vdd 0.63fF +C1073 la_data_in[111] vdd 0.63fF +C1074 la_oenb[110] vdd 0.63fF +C1075 la_data_out[110] vdd 0.63fF +C1076 la_data_in[110] vdd 0.63fF +C1077 la_oenb[109] vdd 0.63fF +C1078 la_data_out[109] vdd 0.63fF +C1079 la_data_in[109] vdd 0.63fF +C1080 la_oenb[108] vdd 0.63fF +C1081 la_data_out[108] vdd 0.63fF +C1082 la_data_in[108] vdd 0.63fF +C1083 la_oenb[107] vdd 0.63fF +C1084 la_data_out[107] vdd 0.63fF +C1085 la_data_in[107] vdd 0.63fF +C1086 la_oenb[106] vdd 0.63fF +C1087 la_data_out[106] vdd 0.63fF +C1088 la_data_in[106] vdd 0.63fF +C1089 la_oenb[105] vdd 0.63fF +C1090 la_data_out[105] vdd 0.63fF +C1091 la_data_in[105] vdd 0.63fF +C1092 la_oenb[104] vdd 0.63fF +C1093 la_data_out[104] vdd 0.63fF +C1094 la_data_in[104] vdd 0.63fF +C1095 la_oenb[103] vdd 0.63fF +C1096 la_data_out[103] vdd 0.63fF +C1097 la_data_in[103] vdd 0.63fF +C1098 la_oenb[102] vdd 0.63fF +C1099 la_data_out[102] vdd 0.63fF +C1100 la_data_in[102] vdd 0.63fF +C1101 la_oenb[101] vdd 0.63fF +C1102 la_data_out[101] vdd 0.63fF +C1103 la_data_in[101] vdd 0.63fF +C1104 la_oenb[100] vdd 0.63fF +C1105 la_data_out[100] vdd 0.63fF +C1106 la_data_in[100] vdd 0.63fF +C1107 la_oenb[99] vdd 0.63fF +C1108 la_data_out[99] vdd 0.63fF +C1109 la_data_in[99] vdd 0.63fF +C1110 la_oenb[98] vdd 0.63fF +C1111 la_data_out[98] vdd 0.63fF +C1112 la_data_in[98] vdd 0.63fF +C1113 la_oenb[97] vdd 0.63fF +C1114 la_data_out[97] vdd 0.63fF +C1115 la_data_in[97] vdd 0.63fF +C1116 la_oenb[96] vdd 0.63fF +C1117 la_data_out[96] vdd 0.63fF +C1118 la_data_in[96] vdd 0.63fF +C1119 la_oenb[95] vdd 0.63fF +C1120 la_data_out[95] vdd 0.63fF +C1121 la_data_in[95] vdd 0.63fF +C1122 la_oenb[94] vdd 0.63fF +C1123 la_data_out[94] vdd 0.63fF +C1124 la_data_in[94] vdd 0.63fF +C1125 la_oenb[93] vdd 0.63fF +C1126 la_data_out[93] vdd 0.63fF +C1127 la_data_in[93] vdd 0.63fF +C1128 la_oenb[92] vdd 0.63fF +C1129 la_data_out[92] vdd 0.63fF +C1130 la_data_in[92] vdd 0.63fF +C1131 la_oenb[91] vdd 0.63fF +C1132 la_data_out[91] vdd 0.63fF +C1133 la_data_in[91] vdd 0.63fF +C1134 la_oenb[90] vdd 0.63fF +C1135 la_data_out[90] vdd 0.63fF +C1136 la_data_in[90] vdd 0.63fF +C1137 la_oenb[89] vdd 0.63fF +C1138 la_data_out[89] vdd 0.63fF +C1139 la_data_in[89] vdd 0.63fF +C1140 la_oenb[88] vdd 0.63fF +C1141 la_data_out[88] vdd 0.63fF +C1142 la_data_in[88] vdd 0.63fF +C1143 la_oenb[87] vdd 0.63fF +C1144 la_data_out[87] vdd 0.63fF +C1145 la_data_in[87] vdd 0.63fF +C1146 la_oenb[86] vdd 0.63fF +C1147 la_data_out[86] vdd 0.63fF +C1148 la_data_in[86] vdd 0.63fF +C1149 la_oenb[85] vdd 0.63fF +C1150 la_data_out[85] vdd 0.63fF +C1151 la_data_in[85] vdd 0.63fF +C1152 la_oenb[84] vdd 0.63fF +C1153 la_data_out[84] vdd 0.63fF +C1154 la_data_in[84] vdd 0.63fF +C1155 la_oenb[83] vdd 0.63fF +C1156 la_data_out[83] vdd 0.63fF +C1157 la_data_in[83] vdd 0.63fF +C1158 la_oenb[82] vdd 0.63fF +C1159 la_data_out[82] vdd 0.63fF +C1160 la_data_in[82] vdd 0.63fF +C1161 la_oenb[81] vdd 0.63fF +C1162 la_data_out[81] vdd 0.63fF +C1163 la_data_in[81] vdd 0.63fF +C1164 la_oenb[80] vdd 0.63fF +C1165 la_data_out[80] vdd 0.63fF +C1166 la_data_in[80] vdd 0.63fF +C1167 la_oenb[79] vdd 0.63fF +C1168 la_data_out[79] vdd 0.63fF +C1169 la_data_in[79] vdd 0.63fF +C1170 la_oenb[78] vdd 0.63fF +C1171 la_data_out[78] vdd 0.63fF +C1172 la_data_in[78] vdd 0.63fF +C1173 la_oenb[77] vdd 0.63fF +C1174 la_data_out[77] vdd 0.63fF +C1175 la_data_in[77] vdd 0.63fF +C1176 la_oenb[76] vdd 0.63fF +C1177 la_data_out[76] vdd 0.63fF +C1178 la_data_in[76] vdd 0.63fF +C1179 la_oenb[75] vdd 0.63fF +C1180 la_data_out[75] vdd 0.63fF +C1181 la_data_in[75] vdd 0.63fF +C1182 la_oenb[74] vdd 0.63fF +C1183 la_data_out[74] vdd 0.63fF +C1184 la_data_in[74] vdd 0.63fF +C1185 la_oenb[73] vdd 0.63fF +C1186 la_data_out[73] vdd 0.63fF +C1187 la_data_in[73] vdd 0.63fF +C1188 la_oenb[72] vdd 0.63fF +C1189 la_data_out[72] vdd 0.63fF +C1190 la_data_in[72] vdd 0.63fF +C1191 la_oenb[71] vdd 0.63fF +C1192 la_data_out[71] vdd 0.63fF +C1193 la_data_in[71] vdd 0.63fF +C1194 la_oenb[70] vdd 0.63fF +C1195 la_data_out[70] vdd 0.63fF +C1196 la_data_in[70] vdd 0.63fF +C1197 la_oenb[69] vdd 0.63fF +C1198 la_data_out[69] vdd 0.63fF +C1199 la_data_in[69] vdd 0.63fF +C1200 la_oenb[68] vdd 0.63fF +C1201 la_data_out[68] vdd 0.63fF +C1202 la_data_in[68] vdd 0.63fF +C1203 la_oenb[67] vdd 0.63fF +C1204 la_data_out[67] vdd 0.63fF +C1205 la_data_in[67] vdd 0.63fF +C1206 la_oenb[66] vdd 0.63fF +C1207 la_data_out[66] vdd 0.63fF +C1208 la_data_in[66] vdd 0.63fF +C1209 la_oenb[65] vdd 0.63fF +C1210 la_data_out[65] vdd 0.63fF +C1211 la_data_in[65] vdd 0.63fF +C1212 la_oenb[64] vdd 0.63fF +C1213 la_data_out[64] vdd 0.63fF +C1214 la_data_in[64] vdd 0.63fF +C1215 la_oenb[63] vdd 0.63fF +C1216 la_data_out[63] vdd 0.63fF +C1217 la_data_in[63] vdd 0.63fF +C1218 la_oenb[62] vdd 0.63fF +C1219 la_data_out[62] vdd 0.63fF +C1220 la_data_in[62] vdd 0.63fF +C1221 la_oenb[61] vdd 0.63fF +C1222 la_data_out[61] vdd 0.63fF +C1223 la_data_in[61] vdd 0.63fF +C1224 la_oenb[60] vdd 0.63fF +C1225 la_data_out[60] vdd 0.63fF +C1226 la_data_in[60] vdd 0.63fF +C1227 la_oenb[59] vdd 0.63fF +C1228 la_data_out[59] vdd 0.63fF +C1229 la_data_in[59] vdd 0.63fF +C1230 la_oenb[58] vdd 0.63fF +C1231 la_data_out[58] vdd 0.63fF +C1232 la_data_in[58] vdd 0.63fF +C1233 la_oenb[57] vdd 0.63fF +C1234 la_data_out[57] vdd 0.63fF +C1235 la_data_in[57] vdd 0.63fF +C1236 la_oenb[56] vdd 0.63fF +C1237 la_data_out[56] vdd 0.63fF +C1238 la_data_in[56] vdd 0.63fF +C1239 la_oenb[55] vdd 0.63fF +C1240 la_data_out[55] vdd 0.63fF +C1241 la_data_in[55] vdd 0.63fF +C1242 la_oenb[54] vdd 0.63fF +C1243 la_data_out[54] vdd 0.63fF +C1244 la_data_in[54] vdd 0.63fF +C1245 la_oenb[53] vdd 0.63fF +C1246 la_data_out[53] vdd 0.63fF +C1247 la_data_in[53] vdd 0.63fF +C1248 la_oenb[52] vdd 0.63fF +C1249 la_data_out[52] vdd 0.63fF +C1250 la_data_in[52] vdd 0.63fF +C1251 la_oenb[51] vdd 0.63fF +C1252 la_data_out[51] vdd 0.63fF +C1253 la_data_in[51] vdd 0.63fF +C1254 la_oenb[50] vdd 0.63fF +C1255 la_data_out[50] vdd 0.63fF +C1256 la_data_in[50] vdd 0.63fF +C1257 la_oenb[49] vdd 0.63fF +C1258 la_data_out[49] vdd 0.63fF +C1259 la_data_in[49] vdd 0.63fF +C1260 la_oenb[48] vdd 0.63fF +C1261 la_data_out[48] vdd 0.63fF +C1262 la_data_in[48] vdd 0.63fF +C1263 la_oenb[47] vdd 0.63fF +C1264 la_data_out[47] vdd 0.63fF +C1265 la_data_in[47] vdd 0.63fF +C1266 la_oenb[46] vdd 0.63fF +C1267 la_data_out[46] vdd 0.63fF +C1268 la_data_in[46] vdd 0.63fF +C1269 la_oenb[45] vdd 0.63fF +C1270 la_data_out[45] vdd 0.63fF +C1271 la_data_in[45] vdd 0.63fF +C1272 la_oenb[44] vdd 0.63fF +C1273 la_data_out[44] vdd 0.63fF +C1274 la_data_in[44] vdd 0.63fF +C1275 la_oenb[43] vdd 0.63fF +C1276 la_data_out[43] vdd 0.63fF +C1277 la_data_in[43] vdd 0.63fF +C1278 la_oenb[42] vdd 0.63fF +C1279 la_data_out[42] vdd 0.63fF +C1280 la_data_in[42] vdd 0.63fF +C1281 la_oenb[41] vdd 0.63fF +C1282 la_data_out[41] vdd 0.63fF +C1283 la_data_in[41] vdd 0.63fF +C1284 la_oenb[40] vdd 0.63fF +C1285 la_data_out[40] vdd 0.63fF +C1286 la_data_in[40] vdd 0.63fF +C1287 la_oenb[39] vdd 0.63fF +C1288 la_data_out[39] vdd 0.63fF +C1289 la_data_in[39] vdd 0.63fF +C1290 la_oenb[38] vdd 0.63fF +C1291 la_data_out[38] vdd 0.63fF +C1292 la_data_in[38] vdd 0.63fF +C1293 la_oenb[37] vdd 0.63fF +C1294 la_data_out[37] vdd 0.63fF +C1295 la_data_in[37] vdd 0.63fF +C1296 la_oenb[36] vdd 0.63fF +C1297 la_data_out[36] vdd 0.63fF +C1298 la_data_in[36] vdd 0.63fF +C1299 la_oenb[35] vdd 0.63fF +C1300 la_data_out[35] vdd 0.63fF +C1301 la_data_in[35] vdd 0.63fF +C1302 la_oenb[34] vdd 0.63fF +C1303 la_data_out[34] vdd 0.63fF +C1304 la_data_in[34] vdd 0.63fF +C1305 la_oenb[33] vdd 0.63fF +C1306 la_data_out[33] vdd 0.63fF +C1307 la_data_in[33] vdd 0.63fF +C1308 la_oenb[32] vdd 0.63fF +C1309 la_data_out[32] vdd 0.63fF +C1310 la_data_in[32] vdd 0.63fF +C1311 la_oenb[31] vdd 0.63fF +C1312 la_data_out[31] vdd 0.63fF +C1313 la_data_in[31] vdd 0.63fF +C1314 la_oenb[30] vdd 0.63fF +C1315 la_data_out[30] vdd 0.63fF +C1316 la_data_in[30] vdd 0.63fF +C1317 la_oenb[29] vdd 0.63fF +C1318 la_data_out[29] vdd 0.63fF +C1319 la_data_in[29] vdd 0.63fF +C1320 la_oenb[28] vdd 0.63fF +C1321 la_data_out[28] vdd 0.63fF +C1322 la_data_in[28] vdd 0.63fF +C1323 la_oenb[27] vdd 0.63fF +C1324 la_data_out[27] vdd 0.63fF +C1325 la_data_in[27] vdd 0.63fF +C1326 la_oenb[26] vdd 0.63fF +C1327 la_data_out[26] vdd 0.63fF +C1328 la_data_in[26] vdd 0.63fF +C1329 la_oenb[25] vdd 0.63fF +C1330 la_data_out[25] vdd 0.63fF +C1331 la_data_in[25] vdd 0.63fF +C1332 la_oenb[24] vdd 0.63fF +C1333 la_data_out[24] vdd 0.63fF +C1334 la_data_in[24] vdd 0.63fF +C1335 la_oenb[23] vdd 0.63fF +C1336 la_data_out[23] vdd 0.63fF +C1337 la_data_in[23] vdd 0.63fF +C1338 la_oenb[22] vdd 0.63fF +C1339 la_data_out[22] vdd 0.63fF +C1340 la_data_in[22] vdd 0.63fF +C1341 la_oenb[21] vdd 0.63fF +C1342 la_data_out[21] vdd 0.63fF +C1343 la_data_in[21] vdd 0.63fF +C1344 la_oenb[20] vdd 0.63fF +C1345 la_data_out[20] vdd 0.63fF +C1346 la_data_in[20] vdd 0.63fF +C1347 la_oenb[19] vdd 0.63fF +C1348 la_data_out[19] vdd 0.63fF +C1349 la_data_in[19] vdd 0.63fF +C1350 la_oenb[18] vdd 0.63fF +C1351 la_data_out[18] vdd 0.63fF +C1352 la_data_in[18] vdd 0.63fF +C1353 la_oenb[17] vdd 0.63fF +C1354 la_data_out[17] vdd 0.63fF +C1355 la_data_in[17] vdd 0.63fF +C1356 la_oenb[16] vdd 0.63fF +C1357 la_data_out[16] vdd 0.63fF +C1358 la_data_in[16] vdd 0.63fF +C1359 la_oenb[15] vdd 0.63fF +C1360 la_data_out[15] vdd 0.63fF +C1361 la_data_in[15] vdd 0.63fF +C1362 la_oenb[14] vdd 0.63fF +C1363 la_data_out[14] vdd 0.63fF +C1364 la_data_in[14] vdd 0.63fF +C1365 la_oenb[13] vdd 0.63fF +C1366 la_data_out[13] vdd 0.63fF +C1367 la_data_in[13] vdd 0.63fF +C1368 la_oenb[12] vdd 0.63fF +C1369 la_data_out[12] vdd 0.63fF +C1370 la_data_in[12] vdd 0.63fF +C1371 la_oenb[11] vdd 0.63fF +C1372 la_data_out[11] vdd 0.63fF +C1373 la_data_in[11] vdd 0.63fF +C1374 la_oenb[10] vdd 0.63fF +C1375 la_data_out[10] vdd 0.63fF +C1376 la_data_in[10] vdd 0.63fF +C1377 la_oenb[9] vdd 0.63fF +C1378 la_data_out[9] vdd 0.63fF +C1379 la_data_in[9] vdd 0.63fF +C1380 la_oenb[8] vdd 0.63fF +C1381 la_data_out[8] vdd 0.63fF +C1382 la_data_in[8] vdd 0.63fF +C1383 la_oenb[7] vdd 0.63fF +C1384 la_data_out[7] vdd 0.63fF +C1385 la_data_in[7] vdd 0.63fF +C1386 la_oenb[6] vdd 0.63fF +C1387 la_data_out[6] vdd 0.63fF +C1388 la_data_in[6] vdd 0.63fF +C1389 la_oenb[5] vdd 0.63fF +C1390 la_data_out[5] vdd 0.63fF +C1391 la_data_in[5] vdd 0.63fF +C1392 la_oenb[4] vdd 0.63fF +C1393 la_data_out[4] vdd 0.63fF +C1394 la_data_in[4] vdd 0.63fF +C1395 la_oenb[3] vdd 0.63fF +C1396 la_data_out[3] vdd 0.63fF +C1397 la_data_in[3] vdd 0.63fF +C1398 la_oenb[2] vdd 0.63fF +C1399 la_data_out[2] vdd 0.63fF +C1400 la_data_in[2] vdd 0.63fF +C1401 la_oenb[1] vdd 0.63fF +C1402 la_data_out[1] vdd 0.63fF +C1403 la_data_in[1] vdd 0.63fF +C1404 la_oenb[0] vdd 0.63fF +C1405 la_data_out[0] vdd 0.63fF +C1406 la_data_in[0] vdd 0.63fF +C1407 wbs_dat_o[31] vdd 0.63fF +C1408 wbs_dat_i[31] vdd 0.63fF +C1409 wbs_adr_i[31] vdd 0.63fF +C1410 wbs_dat_o[30] vdd 0.63fF +C1411 wbs_dat_i[30] vdd 0.63fF +C1412 wbs_adr_i[30] vdd 0.63fF +C1413 wbs_dat_o[29] vdd 0.63fF +C1414 wbs_dat_i[29] vdd 0.63fF +C1415 wbs_adr_i[29] vdd 0.63fF +C1416 wbs_dat_o[28] vdd 0.63fF +C1417 wbs_dat_i[28] vdd 0.63fF +C1418 wbs_adr_i[28] vdd 0.63fF +C1419 wbs_dat_o[27] vdd 0.63fF +C1420 wbs_dat_i[27] vdd 0.63fF +C1421 wbs_adr_i[27] vdd 0.63fF +C1422 wbs_dat_o[26] vdd 0.63fF +C1423 wbs_dat_i[26] vdd 0.63fF +C1424 wbs_adr_i[26] vdd 0.63fF +C1425 wbs_dat_o[25] vdd 0.63fF +C1426 wbs_dat_i[25] vdd 0.63fF +C1427 wbs_adr_i[25] vdd 0.63fF +C1428 wbs_dat_o[24] vdd 0.63fF +C1429 wbs_dat_i[24] vdd 0.63fF +C1430 wbs_adr_i[24] vdd 0.63fF +C1431 wbs_dat_o[23] vdd 0.63fF +C1432 wbs_dat_i[23] vdd 0.63fF +C1433 wbs_adr_i[23] vdd 0.63fF +C1434 wbs_dat_o[22] vdd 0.63fF +C1435 wbs_dat_i[22] vdd 0.63fF +C1436 wbs_adr_i[22] vdd 0.63fF +C1437 wbs_dat_o[21] vdd 0.63fF +C1438 wbs_dat_i[21] vdd 0.63fF +C1439 wbs_adr_i[21] vdd 0.63fF +C1440 wbs_dat_o[20] vdd 0.63fF +C1441 wbs_dat_i[20] vdd 0.63fF +C1442 wbs_adr_i[20] vdd 0.63fF +C1443 wbs_dat_o[19] vdd 0.63fF +C1444 wbs_dat_i[19] vdd 0.63fF +C1445 wbs_adr_i[19] vdd 0.63fF +C1446 wbs_dat_o[18] vdd 0.63fF +C1447 wbs_dat_i[18] vdd 0.63fF +C1448 wbs_adr_i[18] vdd 0.63fF +C1449 wbs_dat_o[17] vdd 0.63fF +C1450 wbs_dat_i[17] vdd 0.63fF +C1451 wbs_adr_i[17] vdd 0.63fF +C1452 wbs_dat_o[16] vdd 0.63fF +C1453 wbs_dat_i[16] vdd 0.63fF +C1454 wbs_adr_i[16] vdd 0.63fF +C1455 wbs_dat_o[15] vdd 0.63fF +C1456 wbs_dat_i[15] vdd 0.63fF +C1457 wbs_adr_i[15] vdd 0.63fF +C1458 wbs_dat_o[14] vdd 0.63fF +C1459 wbs_dat_i[14] vdd 0.63fF +C1460 wbs_adr_i[14] vdd 0.63fF +C1461 wbs_dat_o[13] vdd 0.63fF +C1462 wbs_dat_i[13] vdd 0.63fF +C1463 wbs_adr_i[13] vdd 0.63fF +C1464 wbs_dat_o[12] vdd 0.63fF +C1465 wbs_dat_i[12] vdd 0.63fF +C1466 wbs_adr_i[12] vdd 0.63fF +C1467 wbs_dat_o[11] vdd 0.63fF +C1468 wbs_dat_i[11] vdd 0.63fF +C1469 wbs_adr_i[11] vdd 0.63fF +C1470 wbs_dat_o[10] vdd 0.63fF +C1471 wbs_dat_i[10] vdd 0.63fF +C1472 wbs_adr_i[10] vdd 0.63fF +C1473 wbs_dat_o[9] vdd 0.63fF +C1474 wbs_dat_i[9] vdd 0.63fF +C1475 wbs_adr_i[9] vdd 0.63fF +C1476 wbs_dat_o[8] vdd 0.63fF +C1477 wbs_dat_i[8] vdd 0.63fF +C1478 wbs_adr_i[8] vdd 0.63fF +C1479 wbs_dat_o[7] vdd 0.63fF +C1480 wbs_dat_i[7] vdd 0.63fF +C1481 wbs_adr_i[7] vdd 0.63fF +C1482 wbs_dat_o[6] vdd 0.63fF +C1483 wbs_dat_i[6] vdd 0.63fF +C1484 wbs_adr_i[6] vdd 0.63fF +C1485 wbs_dat_o[5] vdd 0.63fF +C1486 wbs_dat_i[5] vdd 0.63fF +C1487 wbs_adr_i[5] vdd 0.63fF +C1488 wbs_dat_o[4] vdd 0.63fF +C1489 wbs_dat_i[4] vdd 0.63fF +C1490 wbs_adr_i[4] vdd 0.63fF +C1491 wbs_sel_i[3] vdd 0.63fF +C1492 wbs_dat_o[3] vdd 0.63fF +C1493 wbs_dat_i[3] vdd 0.63fF +C1494 wbs_adr_i[3] vdd 0.63fF +C1495 wbs_sel_i[2] vdd 0.63fF +C1496 wbs_dat_o[2] vdd 0.63fF +C1497 wbs_dat_i[2] vdd 0.63fF +C1498 wbs_adr_i[2] vdd 0.63fF +C1499 wbs_sel_i[1] vdd 0.63fF +C1500 wbs_dat_o[1] vdd 0.63fF +C1501 wbs_dat_i[1] vdd 0.63fF +C1502 wbs_adr_i[1] vdd 0.63fF +C1503 wbs_sel_i[0] vdd 0.63fF +C1504 wbs_dat_o[0] vdd 0.63fF +C1505 wbs_dat_i[0] vdd 0.63fF +C1506 wbs_adr_i[0] vdd 0.63fF +C1507 wbs_we_i vdd 0.63fF +C1508 wbs_stb_i vdd 0.63fF +C1509 wbs_cyc_i vdd 0.63fF +C1510 wbs_ack_o vdd 0.63fF +C1511 wb_rst_i vdd 0.63fF +C1512 wb_clk_i vdd 0.63fF +C1513 pll_full_0/divider_0/and_0/Z1 vdd 0.65fF +C1514 pll_full_0/divider_0/and_0/B vdd 2.45fF +C1515 pll_full_0/divider_0/and_0/A vdd 2.35fF +C1516 pll_full_0/divider_0/and_0/out1 vdd 2.99fF +C1517 pll_full_0/divider_0/tspc_2/Z4 vdd 0.86fF +C1518 pll_full_0/divbuf_0/IN vdd 9.95fF +C1519 pll_full_0/divider_0/tspc_2/Z3 vdd 2.26fF +C1520 pll_full_0/divider_0/tspc_2/Z2 vdd 1.46fF +C1521 pll_full_0/divider_0/tspc_2/Z1 vdd 0.99fF +C1522 pll_full_0/divider_0/nor_0/B vdd 6.48fF +C1523 pll_full_0/divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING +C1524 pll_full_0/divider_0/tspc_1/Z4 vdd 0.86fF +C1525 pll_full_0/divider_0/tspc_1/Q vdd 3.12fF +C1526 pll_full_0/divider_0/tspc_1/Z3 vdd 2.26fF +C1527 pll_full_0/divider_0/tspc_1/Z2 vdd 1.46fF +C1528 pll_full_0/divider_0/tspc_1/Z1 vdd 0.99fF +C1529 pll_full_0/divider_0/nor_1/B vdd 7.12fF +C1530 pll_full_0/divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING +C1531 pll_full_0/divider_0/tspc_0/Z4 vdd 0.86fF +C1532 pll_full_0/divider_0/tspc_0/Q vdd 3.14fF +C1533 pll_full_0/divider_0/tspc_0/Z3 vdd 2.26fF +C1534 pll_full_0/divider_0/tspc_0/Z2 vdd 1.46fF +C1535 pll_full_0/divider_0/tspc_0/Z1 vdd 0.99fF +C1536 pll_full_0/divider_0/nor_1/A vdd 7.08fF +C1537 pll_full_0/divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING +C1538 pll_full_0/divider_0/clk vdd 31.85fF +C1539 pll_full_0/divider_0/prescaler_0/Out vdd 4.59fF +C1540 pll_full_0/divider_0/prescaler_0/nand_1/z1 vdd 0.36fF +C1541 pll_full_0/divider_0/prescaler_0/tspc_2/D vdd 2.64fF +C1542 pll_full_0/divider_0/prescaler_0/tspc_0/Q vdd 3.64fF +C1543 pll_full_0/divider_0/prescaler_0/tspc_1/Q vdd 3.61fF +C1544 pll_full_0/divider_0/prescaler_0/nand_0/z1 vdd 0.36fF +C1545 pll_full_0/divider_0/prescaler_0/tspc_0/D vdd 3.12fF +C1546 pll_full_0/divider_0/and_0/OUT vdd 5.67fF +C1547 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF +C1548 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF +C1549 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF +C1550 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C1551 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING +C1552 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING +C1553 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF +C1554 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF +C1555 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF +C1556 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C1557 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING +C1558 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING +C1559 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF +C1560 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF +C1561 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vdd 1.19fF +C1562 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C1563 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.47fF **FLOATING +C1564 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING +C1565 pll_full_0/divider_0/nor_1/Z1 vdd 1.34fF +C1566 pll_full_0/divider_0/nor_0/Z1 vdd 1.34fF +C1567 pll_full_0/divbuf_1/OUT vdd 363.82fF +C1568 pll_full_0/divbuf_1/OUT5 vdd 350.37fF +C1569 pll_full_0/divbuf_1/OUT4 vdd 133.72fF +C1570 pll_full_0/divbuf_1/OUT3 vdd 34.03fF +C1571 pll_full_0/divbuf_1/OUT2 vdd 8.71fF +C1572 pll_full_0/divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C1573 pll_full_0/divbuf_0/OUT5 vdd 350.37fF +C1574 pll_full_0/divbuf_0/OUT4 vdd 133.72fF +C1575 pll_full_0/divbuf_0/OUT3 vdd 34.03fF +C1576 pll_full_0/divbuf_0/OUT2 vdd 8.71fF +C1577 pll_full_0/divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C1578 pll_full_0/ro_complete_0/cbank_2/v vdd 17.88fF +C1579 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C1580 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C1581 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C1582 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C1583 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C1584 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C1585 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C1586 pll_full_0/ro_complete_0/a0 vdd 7.88fF +C1587 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C1588 pll_full_0/ro_complete_0/a1 vdd 5.39fF +C1589 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C1590 pll_full_0/ro_complete_0/a3 vdd 6.85fF +C1591 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C1592 pll_full_0/ro_complete_0/a2 vdd 5.48fF +C1593 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C1594 pll_full_0/ro_complete_0/a4 vdd 5.36fF +C1595 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C1596 pll_full_0/ro_complete_0/a5 vdd 5.19fF +C1597 pll_full_0/ro_complete_0/cbank_0/v vdd 15.02fF +C1598 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C1599 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C1600 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C1601 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C1602 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C1603 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C1604 pll_full_0/ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C1605 pll_full_0/filter_0/a_4216_n5230# vdd 419.25fF **FLOATING +C1606 pll_full_0/filter_0/a_4216_n2998# vdd 1.39fF **FLOATING +C1607 pll_full_0/cp_0/down vdd 1.54fF +C1608 pll_full_0/cp_0/upbar vdd 1.79fF +C1609 pll_full_0/cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C1610 pll_full_0/cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C1611 pll_full_0/cp_0/a_7110_0# vdd 0.17fF **FLOATING +C1612 pll_full_0/cp_0/a_6370_0# vdd 0.40fF **FLOATING +C1613 pll_full_0/cp_0/a_3060_0# vdd 2.49fF **FLOATING +C1614 pll_full_0/cp_0/a_1710_0# vdd 7.47fF **FLOATING +C1615 pll_full_0/pd_0/and_pd_0/Z1 vdd 0.39fF +C1616 pll_full_0/pd_0/and_pd_0/Out1 vdd 2.22fF +C1617 pll_full_0/pd_0/tspc_r_1/z5 vdd 1.10fF +C1618 pll_full_0/pd_0/tspc_r_1/Z4 vdd 1.07fF +C1619 pll_full_0/pd_0/tspc_r_1/Qbar vdd 0.88fF +C1620 pll_full_0/pd_0/tspc_r_1/Z2 vdd 1.22fF +C1621 pll_full_0/pd_0/tspc_r_1/Z1 vdd 0.67fF +C1622 pll_full_0/pd_0/UP vdd 6.61fF +C1623 pll_full_0/pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C1624 pll_full_0/pd_0/tspc_r_1/Z3 vdd 2.12fF +C1625 pll_full_0/pd_0/REF vdd 6.44fF +C1626 pll_full_0/pd_0/tspc_r_0/z5 vdd 1.10fF +C1627 pll_full_0/pd_0/tspc_r_0/Z4 vdd 1.07fF +C1628 pll_full_0/pd_0/R vdd 3.05fF +C1629 pll_full_0/pd_0/tspc_r_0/Qbar vdd 0.79fF +C1630 pll_full_0/pd_0/tspc_r_0/Z2 vdd 1.22fF +C1631 pll_full_0/pd_0/tspc_r_0/Z1 vdd 0.67fF +C1632 pll_full_0/pd_0/DOWN vdd 7.24fF +C1633 pll_full_0/pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C1634 pll_full_0/pd_0/tspc_r_0/Z3 vdd 2.12fF +C1635 pll_full_0/pd_0/DIV vdd 371.87fF +C1636 divider_0/and_0/Z1 vdd 0.74fF +C1637 divider_0/and_0/B vdd 2.25fF +C1638 divider_0/and_0/A vdd 2.19fF +C1639 divider_0/and_0/out1 vdd 2.93fF +C1640 divider_0/tspc_2/Z4 vdd 0.86fF +C1641 divider_0/Out vdd 1.60fF +C1642 divider_0/tspc_2/Z3 vdd 2.26fF +C1643 divider_0/tspc_2/Z2 vdd 1.46fF +C1644 divider_0/tspc_2/Z1 vdd 0.99fF +C1645 divider_0/nor_0/B vdd 6.33fF +C1646 divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING +C1647 divider_0/tspc_1/Z4 vdd 0.86fF +C1648 divider_0/tspc_1/Q vdd 3.12fF +C1649 divider_0/tspc_1/Z3 vdd 2.26fF +C1650 divider_0/tspc_1/Z2 vdd 1.46fF +C1651 divider_0/tspc_1/Z1 vdd 0.99fF +C1652 divider_0/nor_1/B vdd 7.05fF +C1653 divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING +C1654 divider_0/tspc_0/Z4 vdd 0.86fF +C1655 divider_0/tspc_0/Q vdd 3.14fF +C1656 divider_0/tspc_0/Z3 vdd 2.26fF +C1657 divider_0/tspc_0/Z2 vdd 1.46fF +C1658 divider_0/tspc_0/Z1 vdd 0.99fF +C1659 divider_0/nor_1/A vdd 7.04fF +C1660 divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING +C1661 divider_0/clk vdd 5.63fF +C1662 divider_0/prescaler_0/Out vdd 4.59fF +C1663 divider_0/prescaler_0/nand_1/z1 vdd 0.36fF +C1664 divider_0/prescaler_0/tspc_2/D vdd 2.64fF +C1665 divider_0/prescaler_0/tspc_0/Q vdd 3.64fF +C1666 divider_0/prescaler_0/tspc_1/Q vdd 3.61fF +C1667 divider_0/prescaler_0/nand_0/z1 vdd 0.36fF +C1668 divider_0/prescaler_0/tspc_0/D vdd 3.12fF +C1669 divider_0/and_0/OUT vdd 5.62fF +C1670 divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF +C1671 divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF +C1672 divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF +C1673 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF +C1674 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING +C1675 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING +C1676 divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF +C1677 divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF +C1678 divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF +C1679 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF +C1680 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING +C1681 divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING +C1682 divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF +C1683 divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF +C1684 divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF +C1685 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF +C1686 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING +C1687 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING +C1688 divider_0/nor_1/Z1 vdd 1.34fF +C1689 divider_0/nor_0/Z1 vdd 1.34fF +C1690 divider_0/mc2 vdd 5.29fF +C1691 divbuf_7/OUT vdd 363.82fF +C1692 divbuf_7/OUT5 vdd 350.37fF +C1693 divbuf_7/OUT4 vdd 133.72fF +C1694 divbuf_7/OUT3 vdd 34.03fF +C1695 divbuf_7/OUT2 vdd 8.71fF +C1696 divbuf_7/IN vdd 0.89fF +C1697 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING +C1698 divbuf_6/OUT vdd 363.82fF +C1699 divbuf_6/OUT5 vdd 350.37fF +C1700 divbuf_6/OUT4 vdd 133.72fF +C1701 divbuf_6/OUT3 vdd 34.03fF +C1702 divbuf_6/OUT2 vdd 8.71fF +C1703 divbuf_6/IN vdd 0.89fF +C1704 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING +C1705 divbuf_5/OUT vdd 363.82fF +C1706 divbuf_5/OUT5 vdd 350.37fF +C1707 divbuf_5/OUT4 vdd 133.72fF +C1708 divbuf_5/OUT3 vdd 34.03fF +C1709 divbuf_5/OUT2 vdd 8.71fF +C1710 divbuf_5/IN vdd 0.89fF +C1711 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING +C1712 divbuf_4/OUT vdd 363.82fF +C1713 divbuf_4/OUT5 vdd 350.37fF +C1714 divbuf_4/OUT4 vdd 133.72fF +C1715 divbuf_4/OUT3 vdd 34.03fF +C1716 divbuf_4/OUT2 vdd 8.71fF +C1717 divbuf_4/IN vdd 0.89fF +C1718 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING +C1719 divbuf_3/OUT vdd 363.82fF +C1720 divbuf_3/OUT5 vdd 350.37fF +C1721 divbuf_3/OUT4 vdd 133.72fF +C1722 divbuf_3/OUT3 vdd 34.03fF +C1723 divbuf_3/OUT2 vdd 8.71fF +C1724 divbuf_3/IN vdd 0.89fF +C1725 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING +C1726 divbuf_2/OUT vdd 363.82fF +C1727 divbuf_2/OUT5 vdd 350.37fF +C1728 divbuf_2/OUT4 vdd 133.72fF +C1729 divbuf_2/OUT3 vdd 34.03fF +C1730 divbuf_2/OUT2 vdd 8.71fF +C1731 divbuf_2/IN vdd 0.89fF +C1732 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING +C1733 divbuf_1/OUT vdd 363.82fF +C1734 divbuf_1/OUT5 vdd 350.37fF +C1735 divbuf_1/OUT4 vdd 133.72fF +C1736 divbuf_1/OUT3 vdd 34.03fF +C1737 divbuf_1/OUT2 vdd 8.71fF +C1738 divbuf_1/IN vdd 0.89fF +C1739 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING +C1740 divbuf_0/OUT vdd 363.82fF +C1741 divbuf_0/OUT5 vdd 350.37fF +C1742 divbuf_0/OUT4 vdd 133.72fF +C1743 divbuf_0/OUT3 vdd 34.03fF +C1744 divbuf_0/OUT2 vdd 8.71fF +C1745 divbuf_0/IN vdd 0.89fF +C1746 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING +C1747 ro_complete_0/cbank_2/v vdd 17.84fF +C1748 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF +C1749 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF +C1750 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF +C1751 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF +C1752 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF +C1753 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF +C1754 ro_complete_0/cbank_1/v vdd 16.34fF +C1755 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF +C1756 ro_complete_0/a0 vdd 7.88fF +C1757 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF +C1758 ro_complete_0/a1 vdd 5.39fF +C1759 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF +C1760 ro_complete_0/a3 vdd 6.85fF +C1761 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF +C1762 ro_complete_0/a2 vdd 5.48fF +C1763 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF +C1764 ro_complete_0/a4 vdd 5.36fF +C1765 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF +C1766 ro_complete_0/a5 vdd 5.19fF +C1767 ro_complete_0/cbank_0/v vdd 14.98fF +C1768 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF +C1769 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF +C1770 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF +C1771 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF +C1772 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF +C1773 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF +C1774 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF +C1775 filter_0/v vdd 85.69fF +C1776 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING +C1777 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING +C1778 cp_0/down vdd 1.54fF +C1779 cp_0/vbias vdd 2.41fF +C1780 cp_0/out vdd 5.26fF +C1781 cp_0/upbar vdd 1.50fF +C1782 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING +C1783 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING +C1784 cp_0/a_7110_0# vdd 0.17fF **FLOATING +C1785 cp_0/a_6370_0# vdd 0.40fF **FLOATING +C1786 cp_0/a_3060_0# vdd 1.65fF **FLOATING +C1787 cp_0/a_1710_0# vdd 5.76fF **FLOATING +C1788 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING +C1789 cp_0/a_10_n50# vdd 2.96fF **FLOATING +C1790 pd_0/and_pd_0/Z1 vdd 0.39fF +C1791 pd_0/and_pd_0/Out1 vdd 2.22fF +C1792 pd_0/tspc_r_1/z5 vdd 1.10fF +C1793 pd_0/tspc_r_1/Z4 vdd 1.07fF +C1794 pd_0/tspc_r_1/Qbar vdd 0.88fF +C1795 pd_0/tspc_r_1/Z2 vdd 1.22fF +C1796 pd_0/tspc_r_1/Z1 vdd 0.67fF +C1797 pd_0/UP vdd 2.21fF +C1798 pd_0/tspc_r_1/Qbar1 vdd 1.34fF +C1799 pd_0/tspc_r_1/Z3 vdd 2.12fF +C1800 pd_0/REF vdd 1.80fF +C1801 pd_0/tspc_r_0/z5 vdd 1.10fF +C1802 pd_0/tspc_r_0/Z4 vdd 1.07fF +C1803 pd_0/R vdd 3.05fF +C1804 pd_0/tspc_r_0/Qbar vdd 0.79fF +C1805 pd_0/tspc_r_0/Z2 vdd 1.22fF +C1806 pd_0/tspc_r_0/Z1 vdd 0.67fF +C1807 pd_0/DOWN vdd 3.08fF +C1808 pd_0/tspc_r_0/Qbar1 vdd 1.34fF +C1809 pd_0/tspc_r_0/Z3 vdd 2.12fF +C1810 pd_0/DIV vdd 1.82fF .ends