user_proj_example is not need
diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds index c32854a..4a91f90 100644 --- a/gds/user_proj_example.gds +++ b/gds/user_proj_example.gds Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds index c56bb0a..efa5e00 100644 --- a/gds/user_project_wrapper.gds +++ b/gds/user_project_wrapper.gds Binary files differ
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag index eac5648..391002f 100644 --- a/mag/user_proj_example.mag +++ b/mag/user_proj_example.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1645740598 +timestamp 1647172517 << viali >> rect 2697 117249 2731 117283 rect 4261 117249 4295 117283
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag index bfb3dbe..e87c4e6 100644 --- a/mag/user_project_wrapper.mag +++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1645741047 +timestamp 1647172836 << metal1 >> rect 218974 700952 218980 701004 rect 219032 700992 219038 701004
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag index 0c216b7..38253d7 100644 --- a/maglef/user_proj_example.mag +++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1645740619 +timestamp 1647172531 << obsli1 >> rect 1104 2159 178848 117521 << obsm1 >> @@ -2489,7 +2489,7 @@ string LEFclass BLOCK string LEFview TRUE string GDS_END 8544028 -string GDS_FILE /home/marwan/mpw-5c/caravel_example/openlane/user_proj_example/runs/user_proj_example/results/finishing/user_proj_example.magic.gds +string GDS_FILE /home/jasteve4/Documents/ActuatorController/openlane/user_proj_example/runs/user_proj_example/results/finishing/user_proj_example.magic.gds string GDS_START 308790 << end >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag index e89b608..96e30db 100644 --- a/maglef/user_project_wrapper.mag +++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1645741056 +timestamp 1647172842 << obsli1 >> rect 236104 340159 413848 455521 << obsm1 >> @@ -3872,7 +3872,7 @@ string LEFclass BLOCK string LEFview TRUE string GDS_END 10274330 -string GDS_FILE /home/marwan/mpw-5c/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.magic.gds +string GDS_FILE /home/jasteve4/Documents/ActuatorController/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.magic.gds string GDS_START 8544082 << end >>
diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_proj_example/final_summary_report.csv index 6c0a9d4..7cb30b1 100644 --- a/signoff/user_proj_example/final_summary_report.csv +++ b/signoff/user_proj_example/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/marwan/mpw-5c/caravel_example/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,0h10m35s0ms,0h6m34s0ms,2151.851851851852,0.54,1075.925925925926,0.92,2449.42,581,0,0,0,0,0,0,0,11,0,0,-1,110221,8454,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,66866361.0,0.0,5.41,5.45,4.59,2.32,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4 +0,/home/jasteve4/Documents/ActuatorController/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,0h7m45s0ms,0h5m8s0ms,2151.851851851852,0.54,1075.925925925926,0.92,2451.93,581,0,0,0,0,0,0,0,11,0,0,-1,110221,8454,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,66866361.0,0.0,5.41,5.45,4.59,2.32,-1,342,1149,29,836,0,0,0,380,37,0,14,31,46,17,15,129,174,67,13,424,7276,0,7700,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.05,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index cb685ab..be9d9cc 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/marwan/mpw-5c/caravel_example/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h6m50s0ms,0h3m18s0ms,-2.0,-1,-1,-1,482.53,1,0,0,0,0,0,0,0,0,0,-1,-1,1384170,1949,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,1.92,6.58,0.48,0.29,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/home/jasteve4/Documents/ActuatorController/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h4m52s0ms,0h2m40s0ms,-2.0,-1,-1,-1,481.46,1,0,0,0,0,0,0,0,0,0,-1,-1,1384170,1949,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,1.92,6.58,0.48,0.29,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v deleted file mode 100644 index 26081e9..0000000 --- a/verilog/rtl/user_proj_example.v +++ /dev/null
@@ -1,165 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -/* - *------------------------------------------------------------- - * - * user_proj_example - * - * This is an example of a (trivially simple) user project, - * showing how the user project can connect to the logic - * analyzer, the wishbone bus, and the I/O pads. - * - * This project generates an integer count, which is output - * on the user area GPIO pads (digital output only). The - * wishbone connection allows the project to be controlled - * (start and stop) from the management SoC program. - * - * See the testbenches in directory "mprj_counter" for the - * example programs that drive this user project. The three - * testbenches are "io_ports", "la_test1", and "la_test2". - * - *------------------------------------------------------------- - */ - -module user_proj_example #( - parameter BITS = 32 -)( -`ifdef USE_POWER_PINS - inout vccd1, // User area 1 1.8V supply - inout vssd1, // User area 1 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // IRQ - output [2:0] irq -); - wire clk; - wire rst; - - wire [`MPRJ_IO_PADS-1:0] io_in; - wire [`MPRJ_IO_PADS-1:0] io_out; - wire [`MPRJ_IO_PADS-1:0] io_oeb; - - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; - - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; - - // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & {4{wbs_we_i}}; - assign wbs_dat_o = rdata; - assign wdata = wbs_dat_i; - - // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; - - // IRQ - assign irq = 3'b000; // Unused - - // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) - ); - -endmodule - -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end - -endmodule -`default_nettype wire