commit 20e7cc3433ec6ad1f90e4e2ce317f7b0c639039f
author jasteve4 <jasteve4@ncsu.edu> Sun Mar 13 09:22:37 2022 -0400
committer jasteve4 <jasteve4@ncsu.edu> Sun Mar 13 09:22:37 2022 -0400
tree 718af78bf89b945296deaffe26a06344dd391b7f
parent 61b9523f9942fe3a3472f03dfde8c8de85094f8a

adding test files

verilog/dv/braille_driver_test0/braille_driver_test0_tb.v

diff --git a/verilog/dv/braille_driver_test0/braille_driver_test0_tb.v b/verilog/dv/braille_driver_test0/braille_driver_test0_tb.v
index 09af9f6..0c1c552 100644
--- a/verilog/dv/braille_driver_test0/braille_driver_test0_tb.v
+++ b/verilog/dv/braille_driver_test0/braille_driver_test0_tb.v
@@ -107,7 +107,7 @@
   	endtask
 
 	initial begin
-		$dumpfile("araille_driver_test0.vcd");
+		$dumpfile("baraille_driver_test0.vcd");
 		$dumpvars(0, braille_driver_test0_tb);
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench