add self check in testbench for actuator state
diff --git a/Makefile b/Makefile index eab7c0f..ad0a063 100644 --- a/Makefile +++ b/Makefile
@@ -88,6 +88,18 @@ -e MCW_ROOT=$(MCW_ROOT) \ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \ sh -c $(verify_command) +docker_run_verify-sdf=\ + docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ + -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ + -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ + -e CARAVEL_ROOT=${CARAVEL_ROOT} \ + -e TOOLS=/opt/riscv32i \ + -e DESIGNS=$(TARGET_PATH) \ + -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ + -e GCC_PREFIX=riscv32-unknown-elf \ + -e MCW_ROOT=$(MCW_ROOT) \ + -u $$(id -u $$USER):$$(id -g $$USER) efabless/caravel_openlane:2021.11.23_01.42.34 \ + sh -c $(verify_command) .PHONY: harden harden: $(blocks) @@ -105,7 +117,7 @@ $(dv-targets-gl-sdf): SIM=GL_SDF $(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) - $(docker_run_verify) + $(docker_run_verify-sdk) clean-targets=$(blocks:%=clean-%) .PHONY: $(clean-targets)
diff --git a/openlane/spi_mod/config.tcl b/openlane/spi_mod/config.tcl index 63461de..cd2c048 100755 --- a/openlane/spi_mod/config.tcl +++ b/openlane/spi_mod/config.tcl
@@ -28,7 +28,7 @@ set ::env(CLOCK_PORT) "clock" set ::env(CLOCK_NET) "clock" -set ::env(CLOCK_PERIOD) "20" +set ::env(CLOCK_PERIOD) "12.5" set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 900 900"
diff --git a/openlane/system_controler/config.tcl b/openlane/system_controler/config.tcl index fc36bfe..1f90d0d 100755 --- a/openlane/system_controler/config.tcl +++ b/openlane/system_controler/config.tcl
@@ -28,7 +28,7 @@ set ::env(CLOCK_PORT) "clock" set ::env(CLOCK_NET) "clock" -set ::env(CLOCK_PERIOD) "20" +set ::env(CLOCK_PERIOD) "12.5" set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 900 900"
diff --git a/verilog/dv/braille_driver_test0/Makefile b/verilog/dv/actuator_driver_test0/Makefile similarity index 100% rename from verilog/dv/braille_driver_test0/Makefile rename to verilog/dv/actuator_driver_test0/Makefile
diff --git a/verilog/dv/braille_driver_test0/braille_driver_test0.c b/verilog/dv/actuator_driver_test0/actuator_driver_test0.c similarity index 100% rename from verilog/dv/braille_driver_test0/braille_driver_test0.c rename to verilog/dv/actuator_driver_test0/actuator_driver_test0.c
diff --git a/verilog/dv/braille_driver_test0/braille_driver_test0_tb.v b/verilog/dv/actuator_driver_test0/actuator_driver_test0_tb.v similarity index 85% rename from verilog/dv/braille_driver_test0/braille_driver_test0_tb.v rename to verilog/dv/actuator_driver_test0/actuator_driver_test0_tb.v index c915065..18456bd 100644 --- a/verilog/dv/braille_driver_test0/braille_driver_test0_tb.v +++ b/verilog/dv/actuator_driver_test0/actuator_driver_test0_tb.v
@@ -44,6 +44,8 @@ wire [1:0] h_COLS; wire [9:0] h_dots; wire [9:0] dots; + reg [9:0] b_set_state; + wire trigger_out_n; assign mprj_io[37] = enable_n; assign mprj_io[36] = trigger_in_n; @@ -53,6 +55,7 @@ assign mprj_io[32] = ss_n; assign mprj_io[31] = sclk; + assign trigger_out_n = mprj_io[16]; assign mprj_io[7] = 1'b0; assign uart_tx = mprj_io[6]; assign mprj_io[5] = 1'b0; @@ -78,9 +81,9 @@ task init_signals; begin tb_to_core = 1'b0; - enable_n = 0; - trigger_in_n = 0; - latch_data_n = 0; + enable_n = 1; + trigger_in_n = 1; + latch_data_n = 1; mosi = 0; ss_n = 1; wait_n_clks(50); @@ -352,12 +355,50 @@ end endtask + task check_b_state; + input [9:0] b_state; + reg [9:0] local_dots; + reg [9:0] local_h_dots; + begin + local_dots = dots; + local_h_dots = h_dots; + if({b_state[9],b_state[7],b_state[8],b_state[3],b_state[7:5],b_state[2:0]} === dots) + begin + $display("b_state dot test: PASSED"); + $display("b_state:\t%b",b_state); + $display("trans :\t%b",{b_state[9],b_state[7],b_state[8],b_state[3],b_state[7:5],b_state[2:0]}); + $display("dots :\t%b",dots); + end + else + begin + $display("b_state set faild"); + $display("b_state:\t%b",b_state); + $display("trans :\t%b",{b_state[9],b_state[7],b_state[8],b_state[3],b_state[7:5],b_state[2:0]}); + $display("dots :\t%b",dots); + end + if({b_state[9],b_state[7],b_state[8],b_state[3],b_state[7:5],b_state[2:0]} === h_dots) + begin + $display("b_state dot test: PASSED"); + $display("b_state:\t%b",b_state); + $display("trans :\t%b",{b_state[9],b_state[7],b_state[8],b_state[3],b_state[7:5],b_state[2:0]}); + $display("dots :\t%b",h_dots); + end + else + begin + $display("b_state set faild"); + $display("b_state:\t%b",b_state); + $display("trans :\t%b",{b_state[9],b_state[7],b_state[8],b_state[3],b_state[7:5],b_state[2:0]}); + $display("dots :\t%b",h_dots); + end + end + endtask + task write_b_state; input [9:0] b_state; begin wait_n_clks(20); write_data(8'h00,{6'b0,b_state}); - wait_n_clks(20); + wait_n_clks(100); end endtask @@ -385,6 +426,33 @@ end endtask + task advance_b_state_and_check; + input [9:0] b_state; + input past_state_bit; + input inv_bit; + integer j; + reg [31:0] pass; + begin + write_b_state(b_state); + @(posedge clock); + latch_data_n = 1'b1; + trigger_in_n = 1'b1; + wait_n_clks(20); + spi_shift({2'b0,past_state_bit,inv_bit,4'h8,24'b0},pass); + wait_n_clks(100); + latch_data_n = 0; + wait_n_clks(20); + latch_data_n = 1; + wait_n_clks(20); + trigger_in_n = 1'b0; + wait_n_clks(20); + trigger_in_n = 1'b1; + @(negedge trigger_out_n); + check_b_state(b_state); + wait_n_clks(20); + end + endtask + initial begin init_signals(); @@ -394,8 +462,7 @@ wait_n_clks(50); ccr_set(); check_ccr_set(); - write_b_state(10'b11_1111_1111); - set_trigger_mode_no_wait(1'b0,1'b0); + advance_b_state_and_check(10'b11_1111_1111,1'b0,1'b0); tb_to_core = 1'b1; wait(core_to_tb === 1'b0); tb_to_core = 1'b0;
diff --git a/verilog/dv/la_config_test/la_config_test_tb.v b/verilog/dv/la_config_test/la_config_test_tb.v index d6fa0d5..5dbbbb0 100644 --- a/verilog/dv/la_config_test/la_config_test_tb.v +++ b/verilog/dv/la_config_test/la_config_test_tb.v
@@ -87,12 +87,12 @@ initial begin tb_to_core = 1'b0; - enable_n = 0; - trigger_in_n = 0; - latch_data_n = 0; - sclk = 0; + enable_n = 1; + trigger_in_n = 1; + latch_data_n = 1; mosi = 0; - ss_n = 0; + ss_n = 1; + wait_n_clks(50); wait(core_to_tb === 1'b1); $display("LA Test 1 started"); tb_to_core = 1'b1;
diff --git a/verilog/dv/memory_test/memory_test_tb.v b/verilog/dv/memory_test/memory_test_tb.v index 9f5a64c..aae91ac 100644 --- a/verilog/dv/memory_test/memory_test_tb.v +++ b/verilog/dv/memory_test/memory_test_tb.v
@@ -74,9 +74,9 @@ task init_signals; begin tb_to_core = 1'b0; - enable_n = 0; - trigger_in_n = 0; - latch_data_n = 0; + enable_n = 1; + trigger_in_n = 1; + latch_data_n = 1; mosi = 0; ss_n = 1; wait_n_clks(50);
diff --git a/verilog/dv/spi_transfer_test/spi_transfer_test_tb.v b/verilog/dv/spi_transfer_test/spi_transfer_test_tb.v index 74730e9..7129da3 100644 --- a/verilog/dv/spi_transfer_test/spi_transfer_test_tb.v +++ b/verilog/dv/spi_transfer_test/spi_transfer_test_tb.v
@@ -59,8 +59,9 @@ assign core_to_tb = mprj_io[0]; + //always #12.5 clock <= (clock === 1'b0); always #12.5 clock <= (clock === 1'b0); - always #56.5 spi_clock <= ~spi_clock; + always #100 spi_clock <= ~spi_clock; assign sclk = ~ss_n & spi_clock; @@ -74,9 +75,9 @@ task init_signals; begin tb_to_core = 1'b0; - enable_n = 0; - trigger_in_n = 0; - latch_data_n = 0; + enable_n = 1; + trigger_in_n = 1; + latch_data_n = 1; mosi = 0; ss_n = 1; wait_n_clks(50);
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project index 284a97c..f75e8f3 100644 --- a/verilog/includes/includes.gl+sdf.caravel_user_project +++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -1,3 +1,3 @@ // Caravel user project includes $USER_PROJECT_VERILOG/gl/user_project_wrapper.v -$USER_PROJECT_VERILOG/gl/user_proj_example.v +$USER_PROJECT_VERILOG/gl/braille_driver_controller.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index f5047d5..9c7efb3 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,3 +1,11 @@ # Caravel user project includes -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v --v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v +-v $(USER_PROJECT_VERILOG)/gl/braille_driver_controller.v +#-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v +#-v $(USER_PROJECT_VERILOG)/rtl/braille_driver_controller.v +#-v $(USER_PROJECT_VERILOG)/rtl/cells_controller.v +#-v $(USER_PROJECT_VERILOG)/rtl/memory_controller.v +#-v $(USER_PROJECT_VERILOG)/gl/spi_mod.v +#-v $(USER_PROJECT_VERILOG)/rtl/sync_reg.v +#-v $(USER_PROJECT_VERILOG)/gl/system_controller.v +#-v $(USER_PROJECT_VERILOG)/rtl/top.v
diff --git a/verilog/rtl/braille_driver_controller.v b/verilog/rtl/braille_driver_controller.v index de4a7cf..0352ea3 100644 --- a/verilog/rtl/braille_driver_controller.v +++ b/verilog/rtl/braille_driver_controller.v
@@ -158,29 +158,29 @@ }; assign user_data_oeb = { - 1'b1, // 37 enable_n : input - 1'b1, // 36 trigger_in_n : input - 1'b1, // 35 latch_data_n : input - 1'b0, // 34 miso : output - 1'b1, // 33 mosi : input - 1'b1, // 32 ss_n : input - 1'b1, // 31 sclk : input - 1'b0, // 30 hbrige_0 : output - 1'b0, // 29 hbrige_0 : output - 1'b0, // 28 hbrige_0 : output - 1'b0, // 27 hbrige_0 : output - 1'b0, // 26 hbrige_0 : output - 1'b0, // 25 hbrige_0 : output - 1'b0, // 24 hbrige_0 : output - 1'b0, // 23 hbrige_0 : output - 1'b0, // 22 hbrige_0 : output - 1'b0, // 21 hbrige_0 : output - 1'b0, // 20 hbrige_0 : output - 1'b0, // 19 hbrige_0 : output - 1'b0, // 18 hbrige_0 : output - 1'b0, // 17 hbrige_0 : output - 1'b0, // 16 hbrige_0 : output - 1'b0, // 15 triger_out_n : output + 1'b1, // 37 enable_n : input + 1'b1, // 36 trigger_in_n : input + 1'b1, // 35 latch_data_n : input + 1'b0, // 34 miso : output + 1'b1, // 33 mosi : input + 1'b1, // 32 ss_n : input + 1'b1, // 31 sclk : input + 1'b0, // 30 hbrige_0 : output + 1'b0, // 29 hbrige_0 : output + 1'b0, // 28 hbrige_0 : output + 1'b0, // 27 hbrige_0 : output + 1'b0, // 26 hbrige_0 : output + 1'b0, // 25 hbrige_0 : output + 1'b0, // 24 hbrige_0 : output + 1'b0, // 23 hbrige_0 : output + 1'b0, // 22 hbrige_0 : output + 1'b0, // 21 hbrige_0 : output + 1'b0, // 20 hbrige_0 : output + 1'b0, // 19 hbrige_0 : output + 1'b0, // 18 hbrige_0 : output + 1'b0, // 17 hbrige_0 : output + 1'b0, // 16 triger_out_n : output + 1'b1, // 15 n/a : input ~rows_enable[4], // 14 user_control_enable_6 ~rows_enable[3], // 13 user_control_enable_5 ~rows_enable[2], // 12 user_control_enable_4 @@ -206,6 +206,10 @@ assign sclk = io_in_reg[31]; top user_design ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .clock (clk ), .enable_n (enable_n ), .rows (rows ),
diff --git a/verilog/rtl/cells_controller.v b/verilog/rtl/cells_controller.v index 7138e0b..f1c57ef 100644 --- a/verilog/rtl/cells_controller.v +++ b/verilog/rtl/cells_controller.v
@@ -1,5 +1,9 @@ module cells_controller ( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif input wire clock, input wire [15:0] cells_state, input wire system_enable_n,
diff --git a/verilog/rtl/memory_controller.v b/verilog/rtl/memory_controller.v index 05a4415..66cf639 100644 --- a/verilog/rtl/memory_controller.v +++ b/verilog/rtl/memory_controller.v
@@ -1,5 +1,9 @@ module memory_controller ( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif input wire clock, //input wire reset_sn, input wire memory_enable_n,
diff --git a/verilog/rtl/spi_mod.v b/verilog/rtl/spi_mod.v index 2d6b161..78cd3a4 100644 --- a/verilog/rtl/spi_mod.v +++ b/verilog/rtl/spi_mod.v
@@ -1,5 +1,9 @@ module spi_mod ( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif input wire clock, input wire enable_sn, input wire sclk,
diff --git a/verilog/rtl/sync_reg.v b/verilog/rtl/sync_reg.v index 2bd91ba..061c4ed 100644 --- a/verilog/rtl/sync_reg.v +++ b/verilog/rtl/sync_reg.v
@@ -1,4 +1,8 @@ module sync_n( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif input wire signal_n, output wire signal_sn, input wire clock
diff --git a/verilog/rtl/system_controller.v b/verilog/rtl/system_controller.v index 17aa61e..cdec421 100644 --- a/verilog/rtl/system_controller.v +++ b/verilog/rtl/system_controller.v
@@ -1,8 +1,9 @@ - - - module system_controller ( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif input wire clock, input wire enable_sn, input wire update_done,
diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v index 14b71ef..500edfe 100644 --- a/verilog/rtl/top.v +++ b/verilog/rtl/top.v
@@ -1,4 +1,8 @@ module top ( +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif input wire clock, input wire enable_n, output wire [4:0] rows, @@ -42,12 +46,20 @@ sync_n trigger_sync ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .signal_n (trigger_in_n ), .signal_sn (trigger_in_sn ), .clock (clock ) ); sync_n latch_sync ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .signal_n (latch_data_n ), .signal_sn (latch_data_sn ), .clock (clock ) @@ -55,6 +67,10 @@ sync_n enable_sync ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .signal_n (enable_n ), .signal_sn (enable_sn ), .clock (clock ) @@ -62,6 +78,10 @@ spi_mod spi_core ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .clock (clock ), .enable_sn (enable_sn ), .sclk (sclk ), @@ -78,6 +98,10 @@ system_controller system_core ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .clock (clock ), .enable_sn (enable_sn ), .update_done (update_done ), @@ -102,6 +126,10 @@ memory_controller mem_core ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .clock (clock ), .memory_enable_n (memory_enable_n ), .memory_write_n (memory_write_n ), @@ -120,6 +148,10 @@ cells_controller cell_core ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ), // User area 1 1.8V supply + .vssd1 (vssd1 ), // User area 1 digital ground +`endif .clock (clock ), .cells_state (cell_state ), .system_enable_n (system_enable_n ),