commit	14cdd4a8efa574d4ae2206efd099dd07d0b7eacd	[log] [tgz]
author	jasteve4 <jasteve4@ncsu.edu>	Wed Mar 16 15:42:48 2022 -0400
committer	jasteve4 <jasteve4@ncsu.edu>	Wed Mar 16 15:42:48 2022 -0400
tree	ac00927d1896673a76a64214d5a99a6c8861c425
parent	d7fa0a65f1ac567faab2566424d5207861d3e871 [diff]

add self check in testbench for actuator state

Makefile[diff]
openlane/spi_mod/config.tcl[diff]
openlane/system_controler/config.tcl[diff]
verilog/dv/actuator_driver_test0/Makefile[Renamed from verilog/dv/braille_driver_test0/Makefile - diff]
verilog/dv/actuator_driver_test0/actuator_driver_test0.c[Renamed from verilog/dv/braille_driver_test0/braille_driver_test0.c - diff]
verilog/dv/actuator_driver_test0/actuator_driver_test0_tb.v[Renamed from verilog/dv/braille_driver_test0/braille_driver_test0_tb.v - diff]
verilog/dv/la_config_test/la_config_test_tb.v[diff]
verilog/dv/memory_test/memory_test_tb.v[diff]
verilog/dv/spi_transfer_test/spi_transfer_test_tb.v[diff]
verilog/includes/includes.gl+sdf.caravel_user_project[diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/rtl/braille_driver_controller.v[diff]
verilog/rtl/cells_controller.v[diff]
verilog/rtl/memory_controller.v[diff]
verilog/rtl/spi_mod.v[diff]
verilog/rtl/sync_reg.v[diff]
verilog/rtl/system_controller.v[diff]
verilog/rtl/top.v[diff]

18 files changed

tree: ac00927d1896673a76a64214d5a99a6c8861c425

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.