re-harden with all timing files
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index a4bbed9..b20246e 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/wrapped_rgb_mixer.lef b/lef/wrapped_rgb_mixer.lef
index 52edc58..f5701c4 100644
--- a/lef/wrapped_rgb_mixer.lef
+++ b/lef/wrapped_rgb_mixer.lef
@@ -6,13 +6,13 @@
   CLASS BLOCK ;
   FOREIGN wrapped_rgb_mixer ;
   ORIGIN 0.000 0.000 ;
-  SIZE 150.000 BY 210.000 ;
+  SIZE 180.000 BY 210.000 ;
   PIN active
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 166.340 4.000 167.540 ;
+        RECT 0.000 179.940 4.000 181.140 ;
     END
   END active
   PIN io_in[0]
@@ -20,7 +20,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 54.690 0.000 55.250 4.000 ;
+        RECT 57.910 0.000 58.470 4.000 ;
     END
   END io_in[0]
   PIN io_in[10]
@@ -28,7 +28,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 70.790 206.000 71.350 210.000 ;
+        RECT 93.330 206.000 93.890 210.000 ;
     END
   END io_in[10]
   PIN io_in[11]
@@ -36,7 +36,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 179.940 4.000 181.140 ;
+        RECT 0.000 193.540 4.000 194.740 ;
     END
   END io_in[11]
   PIN io_in[12]
@@ -44,7 +44,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 179.940 150.000 181.140 ;
+        RECT 176.000 179.940 180.000 181.140 ;
     END
   END io_in[12]
   PIN io_in[13]
@@ -52,7 +52,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 83.670 0.000 84.230 4.000 ;
+        RECT 90.110 0.000 90.670 4.000 ;
     END
   END io_in[13]
   PIN io_in[14]
@@ -60,7 +60,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 38.590 206.000 39.150 210.000 ;
+        RECT 57.910 206.000 58.470 210.000 ;
     END
   END io_in[14]
   PIN io_in[15]
@@ -68,7 +68,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 186.740 150.000 187.940 ;
+        RECT 176.000 186.740 180.000 187.940 ;
     END
   END io_in[15]
   PIN io_in[16]
@@ -76,7 +76,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 43.940 150.000 45.140 ;
+        RECT 176.000 30.340 180.000 31.540 ;
     END
   END io_in[16]
   PIN io_in[17]
@@ -84,7 +84,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 6.390 206.000 6.950 210.000 ;
+        RECT 25.710 206.000 26.270 210.000 ;
     END
   END io_in[17]
   PIN io_in[18]
@@ -92,15 +92,15 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 12.830 206.000 13.390 210.000 ;
+        RECT 32.150 206.000 32.710 210.000 ;
     END
   END io_in[18]
   PIN io_in[19]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 146.000 3.140 150.000 4.340 ;
+      LAYER met2 ;
+        RECT 167.390 0.000 167.950 4.000 ;
     END
   END io_in[19]
   PIN io_in[1]
@@ -108,7 +108,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 57.540 4.000 58.740 ;
+        RECT 0.000 60.940 4.000 62.140 ;
     END
   END io_in[1]
   PIN io_in[20]
@@ -116,7 +116,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 101.740 4.000 102.940 ;
+        RECT 0.000 111.940 4.000 113.140 ;
     END
   END io_in[20]
   PIN io_in[21]
@@ -124,7 +124,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 67.740 4.000 68.940 ;
+        RECT 0.000 74.540 4.000 75.740 ;
     END
   END io_in[21]
   PIN io_in[22]
@@ -132,7 +132,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 88.140 150.000 89.340 ;
+        RECT 176.000 77.940 180.000 79.140 ;
     END
   END io_in[22]
   PIN io_in[23]
@@ -140,15 +140,15 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 3.170 206.000 3.730 210.000 ;
+        RECT 22.490 206.000 23.050 210.000 ;
     END
   END io_in[23]
   PIN io_in[24]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 0.000 203.740 4.000 204.940 ;
+      LAYER met2 ;
+        RECT 9.610 206.000 10.170 210.000 ;
     END
   END io_in[24]
   PIN io_in[25]
@@ -156,7 +156,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 135.190 0.000 135.750 4.000 ;
+        RECT 144.850 0.000 145.410 4.000 ;
     END
   END io_in[25]
   PIN io_in[26]
@@ -164,7 +164,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 131.970 0.000 132.530 4.000 ;
+        RECT 141.630 0.000 142.190 4.000 ;
     END
   END io_in[26]
   PIN io_in[27]
@@ -172,7 +172,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 67.740 150.000 68.940 ;
+        RECT 176.000 57.540 180.000 58.740 ;
     END
   END io_in[27]
   PIN io_in[28]
@@ -180,7 +180,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 119.090 0.000 119.650 4.000 ;
+        RECT 128.750 0.000 129.310 4.000 ;
     END
   END io_in[28]
   PIN io_in[29]
@@ -188,7 +188,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 148.070 206.000 148.630 210.000 ;
+        RECT 177.050 206.000 177.610 210.000 ;
     END
   END io_in[29]
   PIN io_in[2]
@@ -196,7 +196,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 57.910 0.000 58.470 4.000 ;
+        RECT 64.350 0.000 64.910 4.000 ;
     END
   END io_in[2]
   PIN io_in[30]
@@ -204,7 +204,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 101.740 150.000 102.940 ;
+        RECT 176.000 91.540 180.000 92.740 ;
     END
   END io_in[30]
   PIN io_in[31]
@@ -212,7 +212,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 159.540 4.000 160.740 ;
+        RECT 0.000 173.140 4.000 174.340 ;
     END
   END io_in[31]
   PIN io_in[32]
@@ -220,7 +220,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 109.430 0.000 109.990 4.000 ;
+        RECT 119.090 0.000 119.650 4.000 ;
     END
   END io_in[32]
   PIN io_in[33]
@@ -228,7 +228,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 91.540 4.000 92.740 ;
+        RECT 0.000 101.740 4.000 102.940 ;
     END
   END io_in[33]
   PIN io_in[34]
@@ -236,7 +236,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 106.210 206.000 106.770 210.000 ;
+        RECT 131.970 206.000 132.530 210.000 ;
     END
   END io_in[34]
   PIN io_in[35]
@@ -244,7 +244,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 125.530 206.000 126.090 210.000 ;
+        RECT 154.510 206.000 155.070 210.000 ;
     END
   END io_in[35]
   PIN io_in[36]
@@ -252,7 +252,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 142.540 150.000 143.740 ;
+        RECT 176.000 135.740 180.000 136.940 ;
     END
   END io_in[36]
   PIN io_in[37]
@@ -260,7 +260,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 128.750 206.000 129.310 210.000 ;
+        RECT 157.730 206.000 158.290 210.000 ;
     END
   END io_in[37]
   PIN io_in[3]
@@ -268,7 +268,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 74.010 206.000 74.570 210.000 ;
+        RECT 96.550 206.000 97.110 210.000 ;
     END
   END io_in[3]
   PIN io_in[4]
@@ -276,7 +276,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 139.140 150.000 140.340 ;
+        RECT 176.000 132.340 180.000 133.540 ;
     END
   END io_in[4]
   PIN io_in[5]
@@ -284,7 +284,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 200.340 150.000 201.540 ;
+        RECT 176.000 200.340 180.000 201.540 ;
     END
   END io_in[5]
   PIN io_in[6]
@@ -292,7 +292,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 108.540 4.000 109.740 ;
+        RECT 0.000 118.740 4.000 119.940 ;
     END
   END io_in[6]
   PIN io_in[7]
@@ -300,7 +300,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 74.540 4.000 75.740 ;
+        RECT 0.000 81.340 4.000 82.540 ;
     END
   END io_in[7]
   PIN io_in[8]
@@ -308,7 +308,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 149.340 150.000 150.540 ;
+        RECT 176.000 145.940 180.000 147.140 ;
     END
   END io_in[8]
   PIN io_in[9]
@@ -316,7 +316,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT -0.050 206.000 0.510 210.000 ;
+        RECT 16.050 206.000 16.610 210.000 ;
     END
   END io_in[9]
   PIN io_oeb[0]
@@ -324,7 +324,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 93.330 0.000 93.890 4.000 ;
+        RECT 102.990 0.000 103.550 4.000 ;
     END
   END io_oeb[0]
   PIN io_oeb[10]
@@ -332,7 +332,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 60.940 4.000 62.140 ;
+        RECT 0.000 67.740 4.000 68.940 ;
     END
   END io_oeb[10]
   PIN io_oeb[11]
@@ -340,7 +340,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 132.340 150.000 133.540 ;
+        RECT 176.000 125.540 180.000 126.740 ;
     END
   END io_oeb[11]
   PIN io_oeb[12]
@@ -348,7 +348,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 81.340 150.000 82.540 ;
+        RECT 176.000 71.140 180.000 72.340 ;
     END
   END io_oeb[12]
   PIN io_oeb[13]
@@ -356,7 +356,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 77.940 150.000 79.140 ;
+        RECT 176.000 67.740 180.000 68.940 ;
     END
   END io_oeb[13]
   PIN io_oeb[14]
@@ -372,7 +372,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 19.270 206.000 19.830 210.000 ;
+        RECT 38.590 206.000 39.150 210.000 ;
     END
   END io_oeb[15]
   PIN io_oeb[16]
@@ -380,7 +380,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 37.140 150.000 38.340 ;
+        RECT 176.000 23.540 180.000 24.740 ;
     END
   END io_oeb[16]
   PIN io_oeb[17]
@@ -388,7 +388,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 48.250 0.000 48.810 4.000 ;
+        RECT 51.470 0.000 52.030 4.000 ;
     END
   END io_oeb[17]
   PIN io_oeb[18]
@@ -396,7 +396,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 99.770 206.000 100.330 210.000 ;
+        RECT 125.530 206.000 126.090 210.000 ;
     END
   END io_oeb[18]
   PIN io_oeb[19]
@@ -404,7 +404,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 22.490 206.000 23.050 210.000 ;
+        RECT 41.810 206.000 42.370 210.000 ;
     END
   END io_oeb[19]
   PIN io_oeb[1]
@@ -412,7 +412,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 141.630 0.000 142.190 4.000 ;
+        RECT 151.290 0.000 151.850 4.000 ;
     END
   END io_oeb[1]
   PIN io_oeb[20]
@@ -420,7 +420,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 108.540 150.000 109.740 ;
+        RECT 176.000 98.340 180.000 99.540 ;
     END
   END io_oeb[20]
   PIN io_oeb[21]
@@ -428,7 +428,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 186.740 4.000 187.940 ;
+        RECT 0.000 203.740 4.000 204.940 ;
     END
   END io_oeb[21]
   PIN io_oeb[22]
@@ -444,7 +444,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 61.130 206.000 61.690 210.000 ;
+        RECT 80.450 206.000 81.010 210.000 ;
     END
   END io_oeb[23]
   PIN io_oeb[24]
@@ -452,7 +452,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 64.350 206.000 64.910 210.000 ;
+        RECT 86.890 206.000 87.450 210.000 ;
     END
   END io_oeb[24]
   PIN io_oeb[25]
@@ -460,7 +460,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 20.140 150.000 21.340 ;
+        RECT 176.000 3.140 180.000 4.340 ;
     END
   END io_oeb[25]
   PIN io_oeb[26]
@@ -468,7 +468,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 169.740 150.000 170.940 ;
+        RECT 176.000 166.340 180.000 167.540 ;
     END
   END io_oeb[26]
   PIN io_oeb[27]
@@ -476,15 +476,15 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 77.230 206.000 77.790 210.000 ;
+        RECT 99.770 206.000 100.330 210.000 ;
     END
   END io_oeb[27]
   PIN io_oeb[28]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 146.000 -0.260 150.000 0.940 ;
+      LAYER met2 ;
+        RECT 164.170 0.000 164.730 4.000 ;
     END
   END io_oeb[28]
   PIN io_oeb[29]
@@ -492,7 +492,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 145.940 150.000 147.140 ;
+        RECT 176.000 139.140 180.000 140.340 ;
     END
   END io_oeb[29]
   PIN io_oeb[2]
@@ -500,7 +500,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 119.090 206.000 119.650 210.000 ;
+        RECT 144.850 206.000 145.410 210.000 ;
     END
   END io_oeb[2]
   PIN io_oeb[30]
@@ -508,7 +508,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 190.140 4.000 191.340 ;
+        RECT 0.000 207.140 4.000 208.340 ;
     END
   END io_oeb[30]
   PIN io_oeb[31]
@@ -516,7 +516,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 148.070 0.000 148.630 4.000 ;
+        RECT 160.950 0.000 161.510 4.000 ;
     END
   END io_oeb[31]
   PIN io_oeb[32]
@@ -524,7 +524,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 88.140 4.000 89.340 ;
+        RECT 0.000 94.940 4.000 96.140 ;
     END
   END io_oeb[32]
   PIN io_oeb[33]
@@ -532,7 +532,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 23.540 150.000 24.740 ;
+        RECT 176.000 9.940 180.000 11.140 ;
     END
   END io_oeb[33]
   PIN io_oeb[34]
@@ -540,7 +540,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 9.610 206.000 10.170 210.000 ;
+        RECT 28.930 206.000 29.490 210.000 ;
     END
   END io_oeb[34]
   PIN io_oeb[35]
@@ -548,7 +548,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 77.940 4.000 79.140 ;
+        RECT 0.000 84.740 4.000 85.940 ;
     END
   END io_oeb[35]
   PIN io_oeb[36]
@@ -556,7 +556,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 40.540 4.000 41.740 ;
+        RECT 0.000 43.940 4.000 45.140 ;
     END
   END io_oeb[36]
   PIN io_oeb[37]
@@ -564,7 +564,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 64.340 4.000 65.540 ;
+        RECT 0.000 71.140 4.000 72.340 ;
     END
   END io_oeb[37]
   PIN io_oeb[3]
@@ -572,7 +572,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 90.110 0.000 90.670 4.000 ;
+        RECT 99.770 0.000 100.330 4.000 ;
     END
   END io_oeb[3]
   PIN io_oeb[4]
@@ -580,7 +580,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 30.340 150.000 31.540 ;
+        RECT 176.000 16.740 180.000 17.940 ;
     END
   END io_oeb[4]
   PIN io_oeb[5]
@@ -588,7 +588,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 115.340 4.000 116.540 ;
+        RECT 0.000 125.540 4.000 126.740 ;
     END
   END io_oeb[5]
   PIN io_oeb[6]
@@ -596,7 +596,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 94.940 150.000 96.140 ;
+        RECT 176.000 84.740 180.000 85.940 ;
     END
   END io_oeb[6]
   PIN io_oeb[7]
@@ -604,7 +604,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 16.050 206.000 16.610 210.000 ;
+        RECT 35.370 206.000 35.930 210.000 ;
     END
   END io_oeb[7]
   PIN io_oeb[8]
@@ -620,7 +620,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 38.590 0.000 39.150 4.000 ;
+        RECT 41.810 0.000 42.370 4.000 ;
     END
   END io_oeb[9]
   PIN io_out[0]
@@ -628,7 +628,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 196.940 150.000 198.140 ;
+        RECT 176.000 196.940 180.000 198.140 ;
     END
   END io_out[0]
   PIN io_out[10]
@@ -636,7 +636,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 128.940 150.000 130.140 ;
+        RECT 176.000 122.140 180.000 123.340 ;
     END
   END io_out[10]
   PIN io_out[11]
@@ -660,7 +660,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 144.850 0.000 145.410 4.000 ;
+        RECT 154.510 0.000 155.070 4.000 ;
     END
   END io_out[13]
   PIN io_out[14]
@@ -668,7 +668,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 173.140 150.000 174.340 ;
+        RECT 176.000 169.740 180.000 170.940 ;
     END
   END io_out[14]
   PIN io_out[15]
@@ -676,7 +676,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 149.340 4.000 150.540 ;
+        RECT 0.000 159.540 4.000 160.740 ;
     END
   END io_out[15]
   PIN io_out[16]
@@ -684,7 +684,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 125.540 150.000 126.740 ;
+        RECT 176.000 118.740 180.000 119.940 ;
     END
   END io_out[16]
   PIN io_out[17]
@@ -692,7 +692,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 135.190 206.000 135.750 210.000 ;
+        RECT 164.170 206.000 164.730 210.000 ;
     END
   END io_out[17]
   PIN io_out[18]
@@ -700,7 +700,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 16.740 150.000 17.940 ;
+        RECT 176.000 -0.260 180.000 0.940 ;
     END
   END io_out[18]
   PIN io_out[19]
@@ -708,7 +708,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 84.740 4.000 85.940 ;
+        RECT 0.000 91.540 4.000 92.740 ;
     END
   END io_out[19]
   PIN io_out[1]
@@ -716,7 +716,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 90.110 206.000 90.670 210.000 ;
+        RECT 112.650 206.000 113.210 210.000 ;
     END
   END io_out[1]
   PIN io_out[20]
@@ -724,7 +724,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 115.870 206.000 116.430 210.000 ;
+        RECT 141.630 206.000 142.190 210.000 ;
     END
   END io_out[20]
   PIN io_out[21]
@@ -732,7 +732,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 145.940 4.000 147.140 ;
+        RECT 0.000 156.140 4.000 157.340 ;
     END
   END io_out[21]
   PIN io_out[22]
@@ -740,7 +740,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 112.650 0.000 113.210 4.000 ;
+        RECT 122.310 0.000 122.870 4.000 ;
     END
   END io_out[22]
   PIN io_out[23]
@@ -748,7 +748,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 111.940 150.000 113.140 ;
+        RECT 176.000 101.740 180.000 102.940 ;
     END
   END io_out[23]
   PIN io_out[24]
@@ -756,7 +756,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 96.550 0.000 97.110 4.000 ;
+        RECT 106.210 0.000 106.770 4.000 ;
     END
   END io_out[24]
   PIN io_out[25]
@@ -764,7 +764,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 102.990 206.000 103.550 210.000 ;
+        RECT 128.750 206.000 129.310 210.000 ;
     END
   END io_out[25]
   PIN io_out[26]
@@ -780,7 +780,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 109.430 206.000 109.990 210.000 ;
+        RECT 135.190 206.000 135.750 210.000 ;
     END
   END io_out[27]
   PIN io_out[28]
@@ -788,7 +788,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 61.130 0.000 61.690 4.000 ;
+        RECT 67.570 0.000 68.130 4.000 ;
     END
   END io_out[28]
   PIN io_out[29]
@@ -796,7 +796,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 33.740 150.000 34.940 ;
+        RECT 176.000 20.140 180.000 21.340 ;
     END
   END io_out[29]
   PIN io_out[2]
@@ -820,7 +820,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 50.740 4.000 51.940 ;
+        RECT 0.000 54.140 4.000 55.340 ;
     END
   END io_out[31]
   PIN io_out[32]
@@ -828,7 +828,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 169.740 4.000 170.940 ;
+        RECT 0.000 183.340 4.000 184.540 ;
     END
   END io_out[32]
   PIN io_out[33]
@@ -836,7 +836,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 54.140 150.000 55.340 ;
+        RECT 176.000 43.940 180.000 45.140 ;
     END
   END io_out[33]
   PIN io_out[34]
@@ -844,7 +844,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 176.540 150.000 177.740 ;
+        RECT 176.000 173.140 180.000 174.340 ;
     END
   END io_out[34]
   PIN io_out[35]
@@ -852,7 +852,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 166.340 150.000 167.540 ;
+        RECT 176.000 162.940 180.000 164.140 ;
     END
   END io_out[35]
   PIN io_out[36]
@@ -860,7 +860,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 25.710 206.000 26.270 210.000 ;
+        RECT 45.030 206.000 45.590 210.000 ;
     END
   END io_out[36]
   PIN io_out[37]
@@ -868,7 +868,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 190.140 150.000 191.340 ;
+        RECT 176.000 190.140 180.000 191.340 ;
     END
   END io_out[37]
   PIN io_out[3]
@@ -876,7 +876,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 156.140 4.000 157.340 ;
+        RECT 0.000 169.740 4.000 170.940 ;
     END
   END io_out[3]
   PIN io_out[4]
@@ -884,7 +884,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 135.740 150.000 136.940 ;
+        RECT 176.000 128.940 180.000 130.140 ;
     END
   END io_out[4]
   PIN io_out[5]
@@ -892,7 +892,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 54.690 206.000 55.250 210.000 ;
+        RECT 74.010 206.000 74.570 210.000 ;
     END
   END io_out[5]
   PIN io_out[6]
@@ -900,7 +900,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 141.630 206.000 142.190 210.000 ;
+        RECT 170.610 206.000 171.170 210.000 ;
     END
   END io_out[6]
   PIN io_out[7]
@@ -908,7 +908,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 71.140 4.000 72.340 ;
+        RECT 0.000 77.940 4.000 79.140 ;
     END
   END io_out[7]
   PIN io_out[8]
@@ -916,7 +916,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 67.570 0.000 68.130 4.000 ;
+        RECT 74.010 0.000 74.570 4.000 ;
     END
   END io_out[8]
   PIN io_out[9]
@@ -924,7 +924,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 54.140 4.000 55.340 ;
+        RECT 0.000 57.540 4.000 58.740 ;
     END
   END io_out[9]
   PIN la1_data_in[0]
@@ -932,7 +932,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 57.540 150.000 58.740 ;
+        RECT 176.000 47.340 180.000 48.540 ;
     END
   END la1_data_in[0]
   PIN la1_data_in[10]
@@ -940,7 +940,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 77.230 0.000 77.790 4.000 ;
+        RECT 83.670 0.000 84.230 4.000 ;
     END
   END la1_data_in[10]
   PIN la1_data_in[11]
@@ -948,7 +948,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 50.740 150.000 51.940 ;
+        RECT 176.000 37.140 180.000 38.340 ;
     END
   END la1_data_in[11]
   PIN la1_data_in[12]
@@ -956,7 +956,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 135.740 4.000 136.940 ;
+        RECT 0.000 145.940 4.000 147.140 ;
     END
   END la1_data_in[12]
   PIN la1_data_in[13]
@@ -964,7 +964,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 122.310 0.000 122.870 4.000 ;
+        RECT 131.970 0.000 132.530 4.000 ;
     END
   END la1_data_in[13]
   PIN la1_data_in[14]
@@ -972,7 +972,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 47.340 4.000 48.540 ;
+        RECT 0.000 50.740 4.000 51.940 ;
     END
   END la1_data_in[14]
   PIN la1_data_in[15]
@@ -980,7 +980,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 28.930 206.000 29.490 210.000 ;
+        RECT 48.250 206.000 48.810 210.000 ;
     END
   END la1_data_in[15]
   PIN la1_data_in[16]
@@ -988,7 +988,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 83.670 206.000 84.230 210.000 ;
+        RECT 106.210 206.000 106.770 210.000 ;
     END
   END la1_data_in[16]
   PIN la1_data_in[17]
@@ -996,15 +996,15 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 57.910 206.000 58.470 210.000 ;
+        RECT 77.230 206.000 77.790 210.000 ;
     END
   END la1_data_in[17]
   PIN la1_data_in[18]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 146.000 6.540 150.000 7.740 ;
+      LAYER met2 ;
+        RECT 170.610 0.000 171.170 4.000 ;
     END
   END la1_data_in[18]
   PIN la1_data_in[19]
@@ -1012,7 +1012,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 35.370 206.000 35.930 210.000 ;
+        RECT 54.690 206.000 55.250 210.000 ;
     END
   END la1_data_in[19]
   PIN la1_data_in[1]
@@ -1020,7 +1020,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 70.790 0.000 71.350 4.000 ;
+        RECT 77.230 0.000 77.790 4.000 ;
     END
   END la1_data_in[1]
   PIN la1_data_in[20]
@@ -1028,7 +1028,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 132.340 4.000 133.540 ;
+        RECT 0.000 142.540 4.000 143.740 ;
     END
   END la1_data_in[20]
   PIN la1_data_in[21]
@@ -1036,7 +1036,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 144.850 206.000 145.410 210.000 ;
+        RECT 173.830 206.000 174.390 210.000 ;
     END
   END la1_data_in[21]
   PIN la1_data_in[22]
@@ -1044,7 +1044,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 60.940 150.000 62.140 ;
+        RECT 176.000 50.740 180.000 51.940 ;
     END
   END la1_data_in[22]
   PIN la1_data_in[23]
@@ -1060,7 +1060,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 51.470 0.000 52.030 4.000 ;
+        RECT 54.690 0.000 55.250 4.000 ;
     END
   END la1_data_in[24]
   PIN la1_data_in[25]
@@ -1068,7 +1068,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 139.140 4.000 140.340 ;
+        RECT 0.000 149.340 4.000 150.540 ;
     END
   END la1_data_in[25]
   PIN la1_data_in[26]
@@ -1076,7 +1076,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 40.540 150.000 41.740 ;
+        RECT 176.000 26.940 180.000 28.140 ;
     END
   END la1_data_in[26]
   PIN la1_data_in[27]
@@ -1084,7 +1084,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 102.990 0.000 103.550 4.000 ;
+        RECT 112.650 0.000 113.210 4.000 ;
     END
   END la1_data_in[27]
   PIN la1_data_in[28]
@@ -1092,7 +1092,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 118.740 4.000 119.940 ;
+        RECT 0.000 128.940 4.000 130.140 ;
     END
   END la1_data_in[28]
   PIN la1_data_in[29]
@@ -1100,7 +1100,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 183.340 4.000 184.540 ;
+        RECT 0.000 196.940 4.000 198.140 ;
     END
   END la1_data_in[29]
   PIN la1_data_in[2]
@@ -1108,7 +1108,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 41.810 0.000 42.370 4.000 ;
+        RECT 45.030 0.000 45.590 4.000 ;
     END
   END la1_data_in[2]
   PIN la1_data_in[30]
@@ -1124,7 +1124,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 138.410 0.000 138.970 4.000 ;
+        RECT 148.070 0.000 148.630 4.000 ;
     END
   END la1_data_in[31]
   PIN la1_data_in[3]
@@ -1132,7 +1132,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 111.940 4.000 113.140 ;
+        RECT 0.000 122.140 4.000 123.340 ;
     END
   END la1_data_in[3]
   PIN la1_data_in[4]
@@ -1140,7 +1140,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 122.310 206.000 122.870 210.000 ;
+        RECT 151.290 206.000 151.850 210.000 ;
     END
   END la1_data_in[4]
   PIN la1_data_in[5]
@@ -1148,7 +1148,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 118.740 150.000 119.940 ;
+        RECT 176.000 111.940 180.000 113.140 ;
     END
   END la1_data_in[5]
   PIN la1_data_in[6]
@@ -1156,7 +1156,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 41.810 206.000 42.370 210.000 ;
+        RECT 61.130 206.000 61.690 210.000 ;
     END
   END la1_data_in[6]
   PIN la1_data_in[7]
@@ -1164,7 +1164,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 81.340 4.000 82.540 ;
+        RECT 0.000 88.140 4.000 89.340 ;
     END
   END la1_data_in[7]
   PIN la1_data_in[8]
@@ -1172,7 +1172,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 45.030 206.000 45.590 210.000 ;
+        RECT 64.350 206.000 64.910 210.000 ;
     END
   END la1_data_in[8]
   PIN la1_data_in[9]
@@ -1180,7 +1180,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 125.540 4.000 126.740 ;
+        RECT 0.000 135.740 4.000 136.940 ;
     END
   END la1_data_in[9]
   PIN la1_data_out[0]
@@ -1188,7 +1188,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 28.930 0.000 29.490 4.000 ;
+        RECT 32.150 0.000 32.710 4.000 ;
     END
   END la1_data_out[0]
   PIN la1_data_out[10]
@@ -1196,7 +1196,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 71.140 150.000 72.340 ;
+        RECT 176.000 60.940 180.000 62.140 ;
     END
   END la1_data_out[10]
   PIN la1_data_out[11]
@@ -1204,7 +1204,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 80.450 0.000 81.010 4.000 ;
+        RECT 86.890 0.000 87.450 4.000 ;
     END
   END la1_data_out[11]
   PIN la1_data_out[12]
@@ -1212,15 +1212,15 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 193.540 150.000 194.740 ;
+        RECT 176.000 193.540 180.000 194.740 ;
     END
   END la1_data_out[12]
   PIN la1_data_out[13]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 0.000 196.940 4.000 198.140 ;
+      LAYER met2 ;
+        RECT 3.170 206.000 3.730 210.000 ;
     END
   END la1_data_out[13]
   PIN la1_data_out[14]
@@ -1228,7 +1228,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 67.570 206.000 68.130 210.000 ;
+        RECT 90.110 206.000 90.670 210.000 ;
     END
   END la1_data_out[14]
   PIN la1_data_out[15]
@@ -1244,7 +1244,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 91.540 150.000 92.740 ;
+        RECT 176.000 81.340 180.000 82.540 ;
     END
   END la1_data_out[16]
   PIN la1_data_out[17]
@@ -1252,15 +1252,15 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 159.540 150.000 160.740 ;
+        RECT 176.000 156.140 180.000 157.340 ;
     END
   END la1_data_out[17]
   PIN la1_data_out[18]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 0.000 200.340 4.000 201.540 ;
+      LAYER met2 ;
+        RECT 6.390 206.000 6.950 210.000 ;
     END
   END la1_data_out[18]
   PIN la1_data_out[19]
@@ -1268,7 +1268,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 122.140 150.000 123.340 ;
+        RECT 176.000 115.340 180.000 116.540 ;
     END
   END la1_data_out[19]
   PIN la1_data_out[1]
@@ -1276,7 +1276,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 162.940 4.000 164.140 ;
+        RECT 0.000 176.540 4.000 177.740 ;
     END
   END la1_data_out[1]
   PIN la1_data_out[20]
@@ -1284,7 +1284,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 37.140 4.000 38.340 ;
+        RECT 0.000 40.540 4.000 41.740 ;
     END
   END la1_data_out[20]
   PIN la1_data_out[21]
@@ -1292,7 +1292,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 183.340 150.000 184.540 ;
+        RECT 176.000 183.340 180.000 184.540 ;
     END
   END la1_data_out[21]
   PIN la1_data_out[22]
@@ -1300,7 +1300,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 80.450 206.000 81.010 210.000 ;
+        RECT 102.990 206.000 103.550 210.000 ;
     END
   END la1_data_out[22]
   PIN la1_data_out[23]
@@ -1308,7 +1308,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 45.030 0.000 45.590 4.000 ;
+        RECT 48.250 0.000 48.810 4.000 ;
     END
   END la1_data_out[23]
   PIN la1_data_out[24]
@@ -1316,7 +1316,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 98.340 150.000 99.540 ;
+        RECT 176.000 88.140 180.000 89.340 ;
     END
   END la1_data_out[24]
   PIN la1_data_out[25]
@@ -1332,7 +1332,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 47.340 150.000 48.540 ;
+        RECT 176.000 33.740 180.000 34.940 ;
     END
   END la1_data_out[26]
   PIN la1_data_out[27]
@@ -1340,15 +1340,15 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 173.140 4.000 174.340 ;
+        RECT 0.000 186.740 4.000 187.940 ;
     END
   END la1_data_out[27]
   PIN la1_data_out[28]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 146.000 9.940 150.000 11.140 ;
+      LAYER met2 ;
+        RECT 173.830 0.000 174.390 4.000 ;
     END
   END la1_data_out[28]
   PIN la1_data_out[29]
@@ -1364,7 +1364,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 74.010 0.000 74.570 4.000 ;
+        RECT 80.450 0.000 81.010 4.000 ;
     END
   END la1_data_out[2]
   PIN la1_data_out[30]
@@ -1372,7 +1372,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 74.540 150.000 75.740 ;
+        RECT 176.000 64.340 180.000 65.540 ;
     END
   END la1_data_out[30]
   PIN la1_data_out[31]
@@ -1380,7 +1380,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 203.740 150.000 204.940 ;
+        RECT 176.000 203.740 180.000 204.940 ;
     END
   END la1_data_out[31]
   PIN la1_data_out[3]
@@ -1388,15 +1388,15 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 33.740 4.000 34.940 ;
+        RECT 0.000 37.140 4.000 38.340 ;
     END
   END la1_data_out[3]
   PIN la1_data_out[4]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 146.000 13.340 150.000 14.540 ;
+      LAYER met2 ;
+        RECT 177.050 0.000 177.610 4.000 ;
     END
   END la1_data_out[4]
   PIN la1_data_out[5]
@@ -1412,7 +1412,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 105.140 150.000 106.340 ;
+        RECT 176.000 94.940 180.000 96.140 ;
     END
   END la1_data_out[6]
   PIN la1_data_out[7]
@@ -1428,7 +1428,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 162.940 150.000 164.140 ;
+        RECT 176.000 159.540 180.000 160.740 ;
     END
   END la1_data_out[8]
   PIN la1_data_out[9]
@@ -1436,7 +1436,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 138.410 206.000 138.970 210.000 ;
+        RECT 167.390 206.000 167.950 210.000 ;
     END
   END la1_data_out[9]
   PIN la1_oenb[0]
@@ -1444,7 +1444,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 26.940 150.000 28.140 ;
+        RECT 176.000 13.340 180.000 14.540 ;
     END
   END la1_oenb[0]
   PIN la1_oenb[10]
@@ -1452,7 +1452,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 131.970 206.000 132.530 210.000 ;
+        RECT 160.950 206.000 161.510 210.000 ;
     END
   END la1_oenb[10]
   PIN la1_oenb[11]
@@ -1460,7 +1460,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 98.340 4.000 99.540 ;
+        RECT 0.000 108.540 4.000 109.740 ;
     END
   END la1_oenb[11]
   PIN la1_oenb[12]
@@ -1468,7 +1468,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 105.140 4.000 106.340 ;
+        RECT 0.000 115.340 4.000 116.540 ;
     END
   END la1_oenb[12]
   PIN la1_oenb[13]
@@ -1476,7 +1476,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 106.210 0.000 106.770 4.000 ;
+        RECT 115.870 0.000 116.430 4.000 ;
     END
   END la1_oenb[13]
   PIN la1_oenb[14]
@@ -1492,7 +1492,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 128.750 0.000 129.310 4.000 ;
+        RECT 138.410 0.000 138.970 4.000 ;
     END
   END la1_oenb[15]
   PIN la1_oenb[16]
@@ -1500,15 +1500,15 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 128.940 4.000 130.140 ;
+        RECT 0.000 139.140 4.000 140.340 ;
     END
   END la1_oenb[16]
   PIN la1_oenb[17]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 0.000 193.540 4.000 194.740 ;
+      LAYER met2 ;
+        RECT -0.050 206.000 0.510 210.000 ;
     END
   END la1_oenb[17]
   PIN la1_oenb[18]
@@ -1516,7 +1516,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 51.470 206.000 52.030 210.000 ;
+        RECT 70.790 206.000 71.350 210.000 ;
     END
   END la1_oenb[18]
   PIN la1_oenb[19]
@@ -1524,7 +1524,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 94.940 4.000 96.140 ;
+        RECT 0.000 105.140 4.000 106.340 ;
     END
   END la1_oenb[19]
   PIN la1_oenb[1]
@@ -1532,7 +1532,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 32.150 0.000 32.710 4.000 ;
+        RECT 35.370 0.000 35.930 4.000 ;
     END
   END la1_oenb[1]
   PIN la1_oenb[20]
@@ -1548,7 +1548,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 86.890 206.000 87.450 210.000 ;
+        RECT 109.430 206.000 109.990 210.000 ;
     END
   END la1_oenb[21]
   PIN la1_oenb[22]
@@ -1556,7 +1556,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 48.250 206.000 48.810 210.000 ;
+        RECT 67.570 206.000 68.130 210.000 ;
     END
   END la1_oenb[22]
   PIN la1_oenb[23]
@@ -1564,7 +1564,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 86.890 0.000 87.450 4.000 ;
+        RECT 96.550 0.000 97.110 4.000 ;
     END
   END la1_oenb[23]
   PIN la1_oenb[24]
@@ -1572,7 +1572,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 112.650 206.000 113.210 210.000 ;
+        RECT 138.410 206.000 138.970 210.000 ;
     END
   END la1_oenb[24]
   PIN la1_oenb[25]
@@ -1580,7 +1580,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 64.340 150.000 65.540 ;
+        RECT 176.000 54.140 180.000 55.340 ;
     END
   END la1_oenb[25]
   PIN la1_oenb[26]
@@ -1588,7 +1588,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 142.540 4.000 143.740 ;
+        RECT 0.000 152.740 4.000 153.940 ;
     END
   END la1_oenb[26]
   PIN la1_oenb[27]
@@ -1596,7 +1596,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 156.140 150.000 157.340 ;
+        RECT 176.000 152.740 180.000 153.940 ;
     END
   END la1_oenb[27]
   PIN la1_oenb[28]
@@ -1604,7 +1604,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 35.370 0.000 35.930 4.000 ;
+        RECT 38.590 0.000 39.150 4.000 ;
     END
   END la1_oenb[28]
   PIN la1_oenb[29]
@@ -1612,7 +1612,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 64.350 0.000 64.910 4.000 ;
+        RECT 70.790 0.000 71.350 4.000 ;
     END
   END la1_oenb[29]
   PIN la1_oenb[2]
@@ -1620,7 +1620,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 30.340 4.000 31.540 ;
+        RECT 0.000 33.740 4.000 34.940 ;
     END
   END la1_oenb[2]
   PIN la1_oenb[30]
@@ -1628,7 +1628,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 152.740 150.000 153.940 ;
+        RECT 176.000 149.340 180.000 150.540 ;
     END
   END la1_oenb[30]
   PIN la1_oenb[31]
@@ -1636,7 +1636,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 99.770 0.000 100.330 4.000 ;
+        RECT 109.430 0.000 109.990 4.000 ;
     END
   END la1_oenb[31]
   PIN la1_oenb[3]
@@ -1644,7 +1644,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 96.550 206.000 97.110 210.000 ;
+        RECT 122.310 206.000 122.870 210.000 ;
     END
   END la1_oenb[3]
   PIN la1_oenb[4]
@@ -1652,7 +1652,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 93.330 206.000 93.890 210.000 ;
+        RECT 119.090 206.000 119.650 210.000 ;
     END
   END la1_oenb[4]
   PIN la1_oenb[5]
@@ -1660,15 +1660,15 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 176.540 4.000 177.740 ;
+        RECT 0.000 190.140 4.000 191.340 ;
     END
   END la1_oenb[5]
   PIN la1_oenb[6]
     DIRECTION INPUT ;
     USE SIGNAL ;
     PORT
-      LAYER met3 ;
-        RECT 0.000 207.140 4.000 208.340 ;
+      LAYER met2 ;
+        RECT 12.830 206.000 13.390 210.000 ;
     END
   END la1_oenb[6]
   PIN la1_oenb[7]
@@ -1676,7 +1676,7 @@
     USE SIGNAL ;
     PORT
       LAYER met2 ;
-        RECT 125.530 0.000 126.090 4.000 ;
+        RECT 135.190 0.000 135.750 4.000 ;
     END
   END la1_oenb[7]
   PIN la1_oenb[8]
@@ -1684,7 +1684,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 43.940 4.000 45.140 ;
+        RECT 0.000 47.340 4.000 48.540 ;
     END
   END la1_oenb[8]
   PIN la1_oenb[9]
@@ -1692,7 +1692,7 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 0.000 152.740 4.000 153.940 ;
+        RECT 0.000 162.940 4.000 164.140 ;
     END
   END la1_oenb[9]
   PIN vccd1
@@ -1700,15 +1700,15 @@
     USE POWER ;
     PORT
       LAYER met4 ;
-        RECT 27.880 10.640 29.480 198.800 ;
+        RECT 32.880 10.640 34.480 198.800 ;
     END
     PORT
       LAYER met4 ;
-        RECT 74.200 10.640 75.800 198.800 ;
+        RECT 89.200 10.640 90.800 198.800 ;
     END
     PORT
       LAYER met4 ;
-        RECT 120.520 10.640 122.120 198.800 ;
+        RECT 145.520 10.640 147.120 198.800 ;
     END
   END vccd1
   PIN vssd1
@@ -1716,11 +1716,11 @@
     USE GROUND ;
     PORT
       LAYER met4 ;
-        RECT 51.040 10.640 52.640 198.800 ;
+        RECT 61.040 10.640 62.640 198.800 ;
     END
     PORT
       LAYER met4 ;
-        RECT 97.360 10.640 98.960 198.800 ;
+        RECT 117.360 10.640 118.960 198.800 ;
     END
   END vssd1
   PIN wb_clk_i
@@ -1728,62 +1728,65 @@
     USE SIGNAL ;
     PORT
       LAYER met3 ;
-        RECT 146.000 115.340 150.000 116.540 ;
+        RECT 176.000 105.140 180.000 106.340 ;
     END
   END wb_clk_i
   OBS
       LAYER li1 ;
-        RECT 5.520 10.795 144.440 198.645 ;
+        RECT 5.520 10.795 174.340 198.645 ;
       LAYER met1 ;
-        RECT 0.070 8.880 148.510 204.300 ;
+        RECT 3.290 10.640 177.490 204.640 ;
       LAYER met2 ;
-        RECT 0.790 205.720 2.890 206.000 ;
-        RECT 4.010 205.720 6.110 206.000 ;
-        RECT 7.230 205.720 9.330 206.000 ;
-        RECT 10.450 205.720 12.550 206.000 ;
-        RECT 13.670 205.720 15.770 206.000 ;
-        RECT 16.890 205.720 18.990 206.000 ;
-        RECT 20.110 205.720 22.210 206.000 ;
-        RECT 23.330 205.720 25.430 206.000 ;
-        RECT 26.550 205.720 28.650 206.000 ;
-        RECT 29.770 205.720 35.090 206.000 ;
-        RECT 36.210 205.720 38.310 206.000 ;
-        RECT 39.430 205.720 41.530 206.000 ;
-        RECT 42.650 205.720 44.750 206.000 ;
-        RECT 45.870 205.720 47.970 206.000 ;
-        RECT 49.090 205.720 51.190 206.000 ;
-        RECT 52.310 205.720 54.410 206.000 ;
-        RECT 55.530 205.720 57.630 206.000 ;
-        RECT 58.750 205.720 60.850 206.000 ;
-        RECT 61.970 205.720 64.070 206.000 ;
-        RECT 65.190 205.720 67.290 206.000 ;
-        RECT 68.410 205.720 70.510 206.000 ;
-        RECT 71.630 205.720 73.730 206.000 ;
-        RECT 74.850 205.720 76.950 206.000 ;
-        RECT 78.070 205.720 80.170 206.000 ;
-        RECT 81.290 205.720 83.390 206.000 ;
-        RECT 84.510 205.720 86.610 206.000 ;
-        RECT 87.730 205.720 89.830 206.000 ;
-        RECT 90.950 205.720 93.050 206.000 ;
-        RECT 94.170 205.720 96.270 206.000 ;
-        RECT 97.390 205.720 99.490 206.000 ;
-        RECT 100.610 205.720 102.710 206.000 ;
-        RECT 103.830 205.720 105.930 206.000 ;
-        RECT 107.050 205.720 109.150 206.000 ;
-        RECT 110.270 205.720 112.370 206.000 ;
-        RECT 113.490 205.720 115.590 206.000 ;
-        RECT 116.710 205.720 118.810 206.000 ;
-        RECT 119.930 205.720 122.030 206.000 ;
-        RECT 123.150 205.720 125.250 206.000 ;
-        RECT 126.370 205.720 128.470 206.000 ;
-        RECT 129.590 205.720 131.690 206.000 ;
-        RECT 132.810 205.720 134.910 206.000 ;
-        RECT 136.030 205.720 138.130 206.000 ;
-        RECT 139.250 205.720 141.350 206.000 ;
-        RECT 142.470 205.720 144.570 206.000 ;
-        RECT 145.690 205.720 147.790 206.000 ;
-        RECT 0.100 4.280 148.480 205.720 ;
-        RECT 0.790 0.155 2.890 4.280 ;
+        RECT 4.010 205.720 6.110 207.925 ;
+        RECT 7.230 205.720 9.330 207.925 ;
+        RECT 10.450 205.720 12.550 207.925 ;
+        RECT 13.670 205.720 15.770 207.925 ;
+        RECT 16.890 205.720 22.210 207.925 ;
+        RECT 23.330 205.720 25.430 207.925 ;
+        RECT 26.550 205.720 28.650 207.925 ;
+        RECT 29.770 205.720 31.870 207.925 ;
+        RECT 32.990 205.720 35.090 207.925 ;
+        RECT 36.210 205.720 38.310 207.925 ;
+        RECT 39.430 205.720 41.530 207.925 ;
+        RECT 42.650 205.720 44.750 207.925 ;
+        RECT 45.870 205.720 47.970 207.925 ;
+        RECT 49.090 205.720 54.410 207.925 ;
+        RECT 55.530 205.720 57.630 207.925 ;
+        RECT 58.750 205.720 60.850 207.925 ;
+        RECT 61.970 205.720 64.070 207.925 ;
+        RECT 65.190 205.720 67.290 207.925 ;
+        RECT 68.410 205.720 70.510 207.925 ;
+        RECT 71.630 205.720 73.730 207.925 ;
+        RECT 74.850 205.720 76.950 207.925 ;
+        RECT 78.070 205.720 80.170 207.925 ;
+        RECT 81.290 205.720 86.610 207.925 ;
+        RECT 87.730 205.720 89.830 207.925 ;
+        RECT 90.950 205.720 93.050 207.925 ;
+        RECT 94.170 205.720 96.270 207.925 ;
+        RECT 97.390 205.720 99.490 207.925 ;
+        RECT 100.610 205.720 102.710 207.925 ;
+        RECT 103.830 205.720 105.930 207.925 ;
+        RECT 107.050 205.720 109.150 207.925 ;
+        RECT 110.270 205.720 112.370 207.925 ;
+        RECT 113.490 205.720 118.810 207.925 ;
+        RECT 119.930 205.720 122.030 207.925 ;
+        RECT 123.150 205.720 125.250 207.925 ;
+        RECT 126.370 205.720 128.470 207.925 ;
+        RECT 129.590 205.720 131.690 207.925 ;
+        RECT 132.810 205.720 134.910 207.925 ;
+        RECT 136.030 205.720 138.130 207.925 ;
+        RECT 139.250 205.720 141.350 207.925 ;
+        RECT 142.470 205.720 144.570 207.925 ;
+        RECT 145.690 205.720 151.010 207.925 ;
+        RECT 152.130 205.720 154.230 207.925 ;
+        RECT 155.350 205.720 157.450 207.925 ;
+        RECT 158.570 205.720 160.670 207.925 ;
+        RECT 161.790 205.720 163.890 207.925 ;
+        RECT 165.010 205.720 167.110 207.925 ;
+        RECT 168.230 205.720 170.330 207.925 ;
+        RECT 171.450 205.720 173.550 207.925 ;
+        RECT 174.670 205.720 176.770 207.925 ;
+        RECT 3.320 4.280 177.460 205.720 ;
         RECT 4.010 0.155 6.110 4.280 ;
         RECT 7.230 0.155 9.330 4.280 ;
         RECT 10.450 0.155 12.550 4.280 ;
@@ -1791,8 +1794,7 @@
         RECT 16.890 0.155 18.990 4.280 ;
         RECT 20.110 0.155 22.210 4.280 ;
         RECT 23.330 0.155 25.430 4.280 ;
-        RECT 26.550 0.155 28.650 4.280 ;
-        RECT 29.770 0.155 31.870 4.280 ;
+        RECT 26.550 0.155 31.870 4.280 ;
         RECT 32.990 0.155 35.090 4.280 ;
         RECT 36.210 0.155 38.310 4.280 ;
         RECT 39.430 0.155 41.530 4.280 ;
@@ -1801,8 +1803,7 @@
         RECT 49.090 0.155 51.190 4.280 ;
         RECT 52.310 0.155 54.410 4.280 ;
         RECT 55.530 0.155 57.630 4.280 ;
-        RECT 58.750 0.155 60.850 4.280 ;
-        RECT 61.970 0.155 64.070 4.280 ;
+        RECT 58.750 0.155 64.070 4.280 ;
         RECT 65.190 0.155 67.290 4.280 ;
         RECT 68.410 0.155 70.510 4.280 ;
         RECT 71.630 0.155 73.730 4.280 ;
@@ -1811,151 +1812,161 @@
         RECT 81.290 0.155 83.390 4.280 ;
         RECT 84.510 0.155 86.610 4.280 ;
         RECT 87.730 0.155 89.830 4.280 ;
-        RECT 90.950 0.155 93.050 4.280 ;
-        RECT 94.170 0.155 96.270 4.280 ;
+        RECT 90.950 0.155 96.270 4.280 ;
         RECT 97.390 0.155 99.490 4.280 ;
         RECT 100.610 0.155 102.710 4.280 ;
         RECT 103.830 0.155 105.930 4.280 ;
         RECT 107.050 0.155 109.150 4.280 ;
         RECT 110.270 0.155 112.370 4.280 ;
-        RECT 113.490 0.155 118.810 4.280 ;
+        RECT 113.490 0.155 115.590 4.280 ;
+        RECT 116.710 0.155 118.810 4.280 ;
         RECT 119.930 0.155 122.030 4.280 ;
-        RECT 123.150 0.155 125.250 4.280 ;
-        RECT 126.370 0.155 128.470 4.280 ;
+        RECT 123.150 0.155 128.470 4.280 ;
         RECT 129.590 0.155 131.690 4.280 ;
         RECT 132.810 0.155 134.910 4.280 ;
         RECT 136.030 0.155 138.130 4.280 ;
         RECT 139.250 0.155 141.350 4.280 ;
         RECT 142.470 0.155 144.570 4.280 ;
         RECT 145.690 0.155 147.790 4.280 ;
+        RECT 148.910 0.155 151.010 4.280 ;
+        RECT 152.130 0.155 154.230 4.280 ;
+        RECT 155.350 0.155 160.670 4.280 ;
+        RECT 161.790 0.155 163.890 4.280 ;
+        RECT 165.010 0.155 167.110 4.280 ;
+        RECT 168.230 0.155 170.330 4.280 ;
+        RECT 171.450 0.155 173.550 4.280 ;
+        RECT 174.670 0.155 176.770 4.280 ;
       LAYER met3 ;
-        RECT 4.400 203.340 145.600 204.505 ;
-        RECT 4.000 201.940 146.000 203.340 ;
-        RECT 4.400 199.940 145.600 201.940 ;
-        RECT 4.000 198.540 146.000 199.940 ;
-        RECT 4.400 196.540 145.600 198.540 ;
-        RECT 4.000 195.140 146.000 196.540 ;
-        RECT 4.400 193.140 145.600 195.140 ;
-        RECT 4.000 191.740 146.000 193.140 ;
-        RECT 4.400 189.740 145.600 191.740 ;
-        RECT 4.000 188.340 146.000 189.740 ;
-        RECT 4.400 186.340 145.600 188.340 ;
-        RECT 4.000 184.940 146.000 186.340 ;
-        RECT 4.400 182.940 145.600 184.940 ;
-        RECT 4.000 181.540 146.000 182.940 ;
-        RECT 4.400 179.540 145.600 181.540 ;
-        RECT 4.000 178.140 146.000 179.540 ;
-        RECT 4.400 176.140 145.600 178.140 ;
-        RECT 4.000 174.740 146.000 176.140 ;
-        RECT 4.400 172.740 145.600 174.740 ;
-        RECT 4.000 171.340 146.000 172.740 ;
-        RECT 4.400 169.340 145.600 171.340 ;
-        RECT 4.000 167.940 146.000 169.340 ;
-        RECT 4.400 165.940 145.600 167.940 ;
-        RECT 4.000 164.540 146.000 165.940 ;
-        RECT 4.400 162.540 145.600 164.540 ;
-        RECT 4.000 161.140 146.000 162.540 ;
-        RECT 4.400 159.140 145.600 161.140 ;
-        RECT 4.000 157.740 146.000 159.140 ;
-        RECT 4.400 155.740 145.600 157.740 ;
-        RECT 4.000 154.340 146.000 155.740 ;
-        RECT 4.400 152.340 145.600 154.340 ;
-        RECT 4.000 150.940 146.000 152.340 ;
-        RECT 4.400 148.940 145.600 150.940 ;
-        RECT 4.000 147.540 146.000 148.940 ;
-        RECT 4.400 145.540 145.600 147.540 ;
-        RECT 4.000 144.140 146.000 145.540 ;
-        RECT 4.400 142.140 145.600 144.140 ;
-        RECT 4.000 140.740 146.000 142.140 ;
-        RECT 4.400 138.740 145.600 140.740 ;
-        RECT 4.000 137.340 146.000 138.740 ;
-        RECT 4.400 135.340 145.600 137.340 ;
-        RECT 4.000 133.940 146.000 135.340 ;
-        RECT 4.400 131.940 145.600 133.940 ;
-        RECT 4.000 130.540 146.000 131.940 ;
-        RECT 4.400 128.540 145.600 130.540 ;
-        RECT 4.000 127.140 146.000 128.540 ;
-        RECT 4.400 125.140 145.600 127.140 ;
-        RECT 4.000 123.740 146.000 125.140 ;
-        RECT 4.000 121.740 145.600 123.740 ;
-        RECT 4.000 120.340 146.000 121.740 ;
-        RECT 4.400 118.340 145.600 120.340 ;
-        RECT 4.000 116.940 146.000 118.340 ;
-        RECT 4.400 114.940 145.600 116.940 ;
-        RECT 4.000 113.540 146.000 114.940 ;
-        RECT 4.400 111.540 145.600 113.540 ;
-        RECT 4.000 110.140 146.000 111.540 ;
-        RECT 4.400 108.140 145.600 110.140 ;
-        RECT 4.000 106.740 146.000 108.140 ;
-        RECT 4.400 104.740 145.600 106.740 ;
-        RECT 4.000 103.340 146.000 104.740 ;
-        RECT 4.400 101.340 145.600 103.340 ;
-        RECT 4.000 99.940 146.000 101.340 ;
-        RECT 4.400 97.940 145.600 99.940 ;
-        RECT 4.000 96.540 146.000 97.940 ;
-        RECT 4.400 94.540 145.600 96.540 ;
-        RECT 4.000 93.140 146.000 94.540 ;
-        RECT 4.400 91.140 145.600 93.140 ;
-        RECT 4.000 89.740 146.000 91.140 ;
-        RECT 4.400 87.740 145.600 89.740 ;
-        RECT 4.000 86.340 146.000 87.740 ;
-        RECT 4.400 84.340 146.000 86.340 ;
-        RECT 4.000 82.940 146.000 84.340 ;
-        RECT 4.400 80.940 145.600 82.940 ;
-        RECT 4.000 79.540 146.000 80.940 ;
-        RECT 4.400 77.540 145.600 79.540 ;
-        RECT 4.000 76.140 146.000 77.540 ;
-        RECT 4.400 74.140 145.600 76.140 ;
-        RECT 4.000 72.740 146.000 74.140 ;
-        RECT 4.400 70.740 145.600 72.740 ;
-        RECT 4.000 69.340 146.000 70.740 ;
-        RECT 4.400 67.340 145.600 69.340 ;
-        RECT 4.000 65.940 146.000 67.340 ;
-        RECT 4.400 63.940 145.600 65.940 ;
-        RECT 4.000 62.540 146.000 63.940 ;
-        RECT 4.400 60.540 145.600 62.540 ;
-        RECT 4.000 59.140 146.000 60.540 ;
-        RECT 4.400 57.140 145.600 59.140 ;
-        RECT 4.000 55.740 146.000 57.140 ;
-        RECT 4.400 53.740 145.600 55.740 ;
-        RECT 4.000 52.340 146.000 53.740 ;
-        RECT 4.400 50.340 145.600 52.340 ;
-        RECT 4.000 48.940 146.000 50.340 ;
-        RECT 4.400 46.940 145.600 48.940 ;
-        RECT 4.000 45.540 146.000 46.940 ;
-        RECT 4.400 43.540 145.600 45.540 ;
-        RECT 4.000 42.140 146.000 43.540 ;
-        RECT 4.400 40.140 145.600 42.140 ;
-        RECT 4.000 38.740 146.000 40.140 ;
-        RECT 4.400 36.740 145.600 38.740 ;
-        RECT 4.000 35.340 146.000 36.740 ;
-        RECT 4.400 33.340 145.600 35.340 ;
-        RECT 4.000 31.940 146.000 33.340 ;
-        RECT 4.400 29.940 145.600 31.940 ;
-        RECT 4.000 28.540 146.000 29.940 ;
-        RECT 4.400 26.540 145.600 28.540 ;
-        RECT 4.000 25.140 146.000 26.540 ;
-        RECT 4.400 23.140 145.600 25.140 ;
-        RECT 4.000 21.740 146.000 23.140 ;
-        RECT 4.400 19.740 145.600 21.740 ;
-        RECT 4.000 18.340 146.000 19.740 ;
-        RECT 4.400 16.340 145.600 18.340 ;
-        RECT 4.000 14.940 146.000 16.340 ;
-        RECT 4.400 12.940 145.600 14.940 ;
-        RECT 4.000 11.540 146.000 12.940 ;
-        RECT 4.400 9.540 145.600 11.540 ;
-        RECT 4.000 8.140 146.000 9.540 ;
-        RECT 4.400 6.140 145.600 8.140 ;
-        RECT 4.000 4.740 146.000 6.140 ;
-        RECT 4.400 2.740 145.600 4.740 ;
-        RECT 4.000 1.340 146.000 2.740 ;
-        RECT 4.000 0.175 145.600 1.340 ;
+        RECT 4.400 206.740 176.330 207.905 ;
+        RECT 4.000 205.340 176.330 206.740 ;
+        RECT 4.400 203.340 175.600 205.340 ;
+        RECT 4.000 201.940 176.330 203.340 ;
+        RECT 4.000 199.940 175.600 201.940 ;
+        RECT 4.000 198.540 176.330 199.940 ;
+        RECT 4.400 196.540 175.600 198.540 ;
+        RECT 4.000 195.140 176.330 196.540 ;
+        RECT 4.400 193.140 175.600 195.140 ;
+        RECT 4.000 191.740 176.330 193.140 ;
+        RECT 4.400 189.740 175.600 191.740 ;
+        RECT 4.000 188.340 176.330 189.740 ;
+        RECT 4.400 186.340 175.600 188.340 ;
+        RECT 4.000 184.940 176.330 186.340 ;
+        RECT 4.400 182.940 175.600 184.940 ;
+        RECT 4.000 181.540 176.330 182.940 ;
+        RECT 4.400 179.540 175.600 181.540 ;
+        RECT 4.000 178.140 176.330 179.540 ;
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+        RECT 4.000 11.540 176.330 12.940 ;
+        RECT 4.400 9.540 175.600 11.540 ;
+        RECT 4.000 8.140 176.330 9.540 ;
+        RECT 4.400 6.140 176.330 8.140 ;
+        RECT 4.000 4.740 176.330 6.140 ;
+        RECT 4.400 2.740 175.600 4.740 ;
+        RECT 4.000 1.340 176.330 2.740 ;
+        RECT 4.000 0.175 175.600 1.340 ;
       LAYER met4 ;
-        RECT 36.175 80.415 50.640 198.385 ;
-        RECT 53.040 80.415 73.800 198.385 ;
-        RECT 76.200 80.415 96.960 198.385 ;
-        RECT 99.360 80.415 120.120 198.385 ;
-        RECT 122.520 80.415 133.105 198.385 ;
+        RECT 60.095 199.200 164.385 204.505 ;
+        RECT 60.095 92.655 60.640 199.200 ;
+        RECT 63.040 92.655 88.800 199.200 ;
+        RECT 91.200 92.655 116.960 199.200 ;
+        RECT 119.360 92.655 145.120 199.200 ;
+        RECT 147.520 92.655 164.385 199.200 ;
   END
 END wrapped_rgb_mixer
 END LIBRARY
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 99445f6..3c274ea 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647520307
+timestamp 1647523150
 << metal1 >>
 rect 201494 703196 201500 703248
 rect 201552 703236 201558 703248
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index ab25464..0c8e6bb 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647520338
+timestamp 1647523183
 << obsli1 >>
 rect 71104 98159 279931 579729
 << obsm1 >>
diff --git a/sdc/user_proj_example.sdc b/sdc/user_proj_example.sdc
new file mode 100644
index 0000000..a6cf8bd
--- /dev/null
+++ b/sdc/user_proj_example.sdc
@@ -0,0 +1,1234 @@
+###############################################################################
+# Created by write_sdc
+# Thu Mar  3 16:36:09 2022
+###############################################################################
+current_design user_proj_example
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty 0.2500 wb_clk_i
+set_propagated_clock [get_clocks {wb_clk_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[100]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[101]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[102]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[103]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[104]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[105]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[106]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[107]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[108]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[109]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[110]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[111]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[112]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[113]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[114]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[115]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[116]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[117]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[118]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[119]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[120]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[121]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[122]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[123]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[124]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[125]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[126]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[127]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[45]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[46]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[47]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[48]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[49]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[50]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[51]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[52]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[53]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[54]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[55]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[56]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[57]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[58]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[59]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[60]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[61]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[62]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[63]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[64]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[65]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[66]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[67]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[68]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[69]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[70]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[71]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[72]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[73]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[74]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[75]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[76]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[77]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[78]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[79]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[80]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[81]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[82]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[83]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[84]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[85]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[86]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[87]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[88]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[89]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[90]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[91]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[92]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[93]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[94]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[95]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[96]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[97]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[98]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[99]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[100]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[101]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[102]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[103]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[104]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[105]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[106]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[107]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[108]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[109]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[110]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[111]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[112]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[113]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[114]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[115]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[116]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[117]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[118]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[119]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[120]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[121]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[122]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[123]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[124]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[125]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[126]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[127]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[32]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[33]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[34]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[35]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[36]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[37]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[38]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[39]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[40]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[41]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[42]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[43]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[44]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[45]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[46]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[47]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[48]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[49]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[50]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[51]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[52]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[53]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[54]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[55]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[56]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[57]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[58]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[59]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[60]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[61]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[62]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[63]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[64]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[65]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[66]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[67]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[68]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[69]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[70]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[71]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[72]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[73]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[74]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[75]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[76]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[77]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[78]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[79]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[80]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[81]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[82]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[83]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[84]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[85]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[86]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[87]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[88]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[89]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[90]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[91]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[92]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[93]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[94]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[95]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[96]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[97]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[98]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[99]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_oenb[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {irq[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[100]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[101]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[102]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[103]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[104]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[105]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[106]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[107]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[108]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[109]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[110]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[111]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[112]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[113]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[114]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[115]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[116]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[117]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[118]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[119]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[120]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[121]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[122]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[123]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[124]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[125]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[126]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[127]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[45]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[46]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[47]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[48]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[49]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[50]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[51]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[52]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[53]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[54]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[55]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[56]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[57]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[58]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[59]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[60]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[61]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[62]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[63]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[64]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[65]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[66]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[67]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[68]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[69]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[70]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[71]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[72]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[73]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[74]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[75]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[76]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[77]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[78]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[79]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[80]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[81]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[82]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[83]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[84]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[85]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[86]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[87]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[88]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[89]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[90]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[91]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[92]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[93]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[94]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[95]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[96]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[97]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[98]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[99]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la_data_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq[2]}]
+set_load -pin_load 0.0334 [get_ports {irq[1]}]
+set_load -pin_load 0.0334 [get_ports {irq[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
new file mode 100644
index 0000000..f6c586e
--- /dev/null
+++ b/sdc/user_project_wrapper.sdc
@@ -0,0 +1,1351 @@
+###############################################################################
+# Created by write_sdc
+# Thu Mar 17 13:18:26 2022
+###############################################################################
+current_design user_project_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}]
+set_clock_transition 0.1500 [get_clocks {user_clock2}]
+set_clock_uncertainty 0.2500 user_clock2
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[10]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[11]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[12]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[13]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[14]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[15]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[16]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[17]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[18]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[19]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[20]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[21]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[22]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[23]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[24]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[25]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[26]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[27]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[28]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[4]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[5]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[6]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[7]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[8]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[9]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[100]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[101]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[102]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[103]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[104]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[105]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[106]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[107]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[108]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[109]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[110]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[111]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[112]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[113]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[114]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[115]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[116]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[117]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[118]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[119]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[120]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[121]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[122]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[123]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[124]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[125]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[126]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[127]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[45]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[46]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[47]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[48]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[49]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[50]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[51]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[52]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[53]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[54]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[55]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[56]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[57]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[58]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[59]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[60]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[61]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[62]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[63]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[64]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[65]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[66]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[67]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[68]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[69]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[70]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[71]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[72]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[73]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[74]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[75]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[76]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[77]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[78]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[79]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[80]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[81]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[82]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[83]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[84]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[85]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[86]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[87]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[88]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[89]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[90]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[91]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[92]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[93]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[94]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[95]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[96]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[97]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[98]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[99]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[100]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[101]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[102]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[103]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[104]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[105]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[106]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[107]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[108]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[109]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[10]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[110]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[111]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[112]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[113]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[114]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[115]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[116]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[117]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[118]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[119]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[11]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[120]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[121]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[122]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[123]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[124]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[125]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[126]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[127]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[12]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[13]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[14]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[15]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[16]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[17]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[18]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[19]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[20]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[21]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[22]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[23]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[24]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[25]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[26]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[27]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[28]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[29]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[30]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[31]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[32]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[33]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[34]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[35]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[36]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[37]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[38]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[39]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[40]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[41]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[42]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[43]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[44]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[45]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[46]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[47]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[48]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[49]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[4]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[50]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[51]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[52]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[53]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[54]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[55]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[56]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[57]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[58]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[59]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[5]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[60]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[61]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[62]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[63]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[64]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[65]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[66]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[67]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[68]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[69]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[6]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[70]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[71]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[72]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[73]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[74]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[75]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[76]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[77]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[78]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[79]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[7]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[80]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[81]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[82]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[83]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[84]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[85]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[86]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[87]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[88]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[89]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[8]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[90]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[91]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[92]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[93]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[94]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[95]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[96]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[97]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[98]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[99]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_oenb[9]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wb_clk_i}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wb_rst_i}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_we_i}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[0]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[10]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[11]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[12]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[13]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[14]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[15]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[16]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[17]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[18]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[19]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[1]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[20]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[21]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[22]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[23]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[24]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[25]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[26]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[27]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[28]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[2]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[3]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[4]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[5]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[6]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[7]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[8]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {analog_io[9]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[0]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[10]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[11]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[12]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[13]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[14]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[15]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[16]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[17]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[18]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[19]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[1]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[20]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[21]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[22]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[23]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[24]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[25]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[26]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[27]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[28]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[29]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[2]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[30]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[31]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[32]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[33]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[34]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[35]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[36]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[37]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[3]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[4]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[5]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[6]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[7]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[8]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_oeb[9]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {io_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[100]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[101]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[102]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[103]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[104]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[105]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[106]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[107]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[108]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[109]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[110]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[111]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[112]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[113]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[114]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[115]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[116]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[117]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[118]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[119]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[120]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[121]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[122]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[123]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[124]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[125]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[126]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[127]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[45]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[46]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[47]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[48]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[49]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[50]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[51]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[52]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[53]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[54]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[55]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[56]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[57]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[58]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[59]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[60]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[61]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[62]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[63]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[64]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[65]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[66]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[67]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[68]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[69]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[70]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[71]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[72]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[73]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[74]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[75]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[76]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[77]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[78]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[79]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[80]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[81]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[82]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[83]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[84]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[85]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[86]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[87]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[88]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[89]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[90]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[91]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[92]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[93]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[94]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[95]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[96]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[97]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[98]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[99]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {la_data_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {user_irq[0]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {user_irq[1]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {user_irq[2]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {user_clock2}] -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/sdc/wrapped_frequency_counter.sdc b/sdc/wrapped_frequency_counter.sdc
new file mode 100644
index 0000000..70ed89c
--- /dev/null
+++ b/sdc/wrapped_frequency_counter.sdc
@@ -0,0 +1,444 @@
+###############################################################################
+# Created by write_sdc
+# Wed Mar 16 19:05:42 2022
+###############################################################################
+current_design wrapped_frequency_counter
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty 0.2500 wb_clk_i
+set_propagated_clock [get_clocks {wb_clk_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {active}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {active}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/sdc/wrapped_function_generator.sdc b/sdc/wrapped_function_generator.sdc
new file mode 100644
index 0000000..2110ac7
--- /dev/null
+++ b/sdc/wrapped_function_generator.sdc
@@ -0,0 +1,630 @@
+###############################################################################
+# Created by write_sdc
+# Fri Mar  4 16:59:16 2022
+###############################################################################
+current_design wrapped_function_generator
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 20.0000 [get_ports {wb_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty 0.2500 wb_clk_i
+set_propagated_clock [get_clocks {wb_clk_i}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {active}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_rst_i}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_we_i}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_adr_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_clk_o}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_rst_o}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rambus_wb_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {rambus_wb_clk_o}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_rst_o}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_stb_o}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {rambus_wb_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {active}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rambus_wb_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/sdc/wrapped_rgb_mixer.sdc b/sdc/wrapped_rgb_mixer.sdc
new file mode 100644
index 0000000..ff77371
--- /dev/null
+++ b/sdc/wrapped_rgb_mixer.sdc
@@ -0,0 +1,444 @@
+###############################################################################
+# Created by write_sdc
+# Thu Mar 17 11:31:06 2022
+###############################################################################
+current_design wrapped_rgb_mixer
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty 0.2500 wb_clk_i
+set_propagated_clock [get_clocks {wb_clk_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {active}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {active}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/sdc/wrapped_vga_clock.sdc b/sdc/wrapped_vga_clock.sdc
new file mode 100644
index 0000000..b6f9720
--- /dev/null
+++ b/sdc/wrapped_vga_clock.sdc
@@ -0,0 +1,444 @@
+###############################################################################
+# Created by write_sdc
+# Thu Mar 17 11:36:50 2022
+###############################################################################
+current_design wrapped_vga_clock
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 30.0000 [get_ports {wb_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty 0.2500 wb_clk_i
+set_propagated_clock [get_clocks {wb_clk_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {active}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la1_data_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {active}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 5.0000 [current_design]
diff --git a/sdf/user_proj_example.sdf b/sdf/user_proj_example.sdf
new file mode 100644
index 0000000..be238ad
--- /dev/null
+++ b/sdf/user_proj_example.sdf
@@ -0,0 +1,9719 @@
+(DELAYFILE
+ (SDFVERSION "3.0")
+ (DESIGN "user_proj_example")
+ (DATE "Thu Mar  3 16:39:57 2022")
+ (VENDOR "Parallax")
+ (PROGRAM "STA")
+ (VERSION "2.3.1")
+ (DIVIDER .)
+ (VOLTAGE 1.800::1.800)
+ (PROCESS "1.000::1.000")
+ (TEMPERATURE 25.000::25.000)
+ (TIMESCALE 1ns)
+ (CELL
+  (CELLTYPE "user_proj_example")
+  (INSTANCE)
+  (DELAY
+   (ABSOLUTE
+    (INTERCONNECT la_data_in[32] input1.A (0.088:0.088:0.088) (0.044:0.044:0.044))
+    (INTERCONNECT la_data_in[32] ANTENNA_input1_A.DIODE (0.088:0.088:0.088) (0.044:0.044:0.044))
+    (INTERCONNECT la_data_in[33] input2.A (0.067:0.067:0.067) (0.033:0.033:0.033))
+    (INTERCONNECT la_data_in[33] ANTENNA_input2_A.DIODE (0.067:0.067:0.067) (0.033:0.033:0.033))
+    (INTERCONNECT la_data_in[34] input3.A (0.084:0.084:0.084) (0.042:0.042:0.042))
+    (INTERCONNECT la_data_in[34] ANTENNA_input3_A.DIODE (0.085:0.085:0.085) (0.042:0.042:0.042))
+    (INTERCONNECT la_data_in[35] input4.A (0.063:0.063:0.063) (0.030:0.030:0.030))
+    (INTERCONNECT la_data_in[35] ANTENNA_input4_A.DIODE (0.063:0.063:0.063) (0.031:0.031:0.031))
+    (INTERCONNECT la_data_in[36] input5.A (0.056:0.056:0.056) (0.027:0.027:0.027))
+    (INTERCONNECT la_data_in[36] ANTENNA_input5_A.DIODE (0.056:0.056:0.056) (0.027:0.027:0.027))
+    (INTERCONNECT la_data_in[37] input6.A (0.058:0.058:0.058) (0.028:0.028:0.028))
+    (INTERCONNECT la_data_in[37] ANTENNA_input6_A.DIODE (0.058:0.058:0.058) (0.028:0.028:0.028))
+    (INTERCONNECT la_data_in[38] input7.A (0.070:0.070:0.070) (0.035:0.035:0.035))
+    (INTERCONNECT la_data_in[38] ANTENNA_input7_A.DIODE (0.071:0.071:0.071) (0.035:0.035:0.035))
+    (INTERCONNECT la_data_in[39] input8.A (0.050:0.050:0.050) (0.024:0.024:0.024))
+    (INTERCONNECT la_data_in[39] ANTENNA_input8_A.DIODE (0.050:0.050:0.050) (0.024:0.024:0.024))
+    (INTERCONNECT la_data_in[40] input9.A (0.051:0.051:0.051) (0.024:0.024:0.024))
+    (INTERCONNECT la_data_in[40] ANTENNA_input9_A.DIODE (0.051:0.051:0.051) (0.024:0.024:0.024))
+    (INTERCONNECT la_data_in[41] input10.A (0.057:0.057:0.057) (0.028:0.028:0.028))
+    (INTERCONNECT la_data_in[41] ANTENNA_input10_A.DIODE (0.058:0.058:0.058) (0.028:0.028:0.028))
+    (INTERCONNECT la_data_in[42] input11.A (0.046:0.046:0.046) (0.022:0.022:0.022))
+    (INTERCONNECT la_data_in[42] ANTENNA_input11_A.DIODE (0.046:0.046:0.046) (0.022:0.022:0.022))
+    (INTERCONNECT la_data_in[43] input12.A (0.060:0.060:0.060) (0.029:0.029:0.029))
+    (INTERCONNECT la_data_in[43] ANTENNA_input12_A.DIODE (0.061:0.061:0.061) (0.030:0.030:0.030))
+    (INTERCONNECT la_data_in[44] input13.A (0.049:0.049:0.049) (0.024:0.024:0.024))
+    (INTERCONNECT la_data_in[44] ANTENNA_input13_A.DIODE (0.049:0.049:0.049) (0.024:0.024:0.024))
+    (INTERCONNECT la_data_in[45] input14.A (0.044:0.044:0.044) (0.021:0.021:0.021))
+    (INTERCONNECT la_data_in[45] ANTENNA_input14_A.DIODE (0.044:0.044:0.044) (0.021:0.021:0.021))
+    (INTERCONNECT la_data_in[46] input15.A (0.031:0.031:0.031) (0.015:0.015:0.015))
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+    (INTERCONNECT output203.X la_data_out[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output204.X la_data_out[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output205.X la_data_out[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output206.X la_data_out[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output207.X la_data_out[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output208.X la_data_out[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output209.X la_data_out[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output210.X wbs_ack_o (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output211.X wbs_dat_o[0] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output212.X wbs_dat_o[10] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output213.X wbs_dat_o[11] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output214.X wbs_dat_o[12] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output215.X wbs_dat_o[13] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output216.X wbs_dat_o[14] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output217.X wbs_dat_o[15] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output218.X wbs_dat_o[16] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output219.X wbs_dat_o[17] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output220.X wbs_dat_o[18] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output221.X wbs_dat_o[19] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output222.X wbs_dat_o[1] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output223.X wbs_dat_o[20] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output224.X wbs_dat_o[21] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output225.X wbs_dat_o[22] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output226.X wbs_dat_o[23] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output227.X wbs_dat_o[24] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output228.X wbs_dat_o[25] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output229.X wbs_dat_o[26] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output230.X wbs_dat_o[27] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output231.X wbs_dat_o[28] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output232.X wbs_dat_o[29] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output233.X wbs_dat_o[2] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output234.X wbs_dat_o[30] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output235.X wbs_dat_o[31] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output236.X wbs_dat_o[3] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output237.X wbs_dat_o[4] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output238.X wbs_dat_o[5] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output239.X wbs_dat_o[6] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output240.X wbs_dat_o[7] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output241.X wbs_dat_o[8] (0.001:0.001:0.001) (0.001:0.001:0.001))
+    (INTERCONNECT output242.X wbs_dat_o[9] (0.001:0.001:0.001) (0.001:0.001:0.001))
+   )
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