verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
//  0 Function generator             : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_function_generator
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_function_generator/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_function_generator/function_generator/src/generator.v
//  1 VGA Clock                      : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_vga_clock
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/button_pulse.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/digit.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/fontROM.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/top.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/vga_clock.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_vga_clock/vga_clock/rtl/VgaSyncGen.v
//  2 Frequency counter              : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_frequency_counter
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/frequency_counter/src/edge_detect.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/frequency_counter/src/frequency_counter.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_frequency_counter/frequency_counter/src/seven_segment.v
//  3 RGB Mixer                      : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_rgb_mixer
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/debounce.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/encoder.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/pwm.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_rgb_mixer/rgb_mixer/src/rgb_mixer.v
// 11 Hack soc                       : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_hack_soc
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/wrapped_hack_soc_dffram.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/dmux8way.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_alu.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_clock.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_cpu.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/hack_soc.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/pc.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/register.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/spi_sram_encoder.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/video_signal_generator_640x480.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/spi_video_ram_2.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/vram_write_fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/rom_stream_loader.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/boot_logo.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hack_soc/hack_soc/src/DFFRF_2R1W.v
// 13 teras                          : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_teras
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/arith_to_s3.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/dspblock_6x6_f400_uid35.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/fifo.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/intmultiplier_f400_uid31.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/l2a.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/leftshifter12_by_max_31_f400_uid38.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/lzocshifter_6_to_6_counting_8_f400_uid18.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/lzocshiftersticky_32_to_7_counting_64_f400_uid22.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/pe_s3.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/rightshiftersticky8_by_max_8_f400_uid24.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/s3fdp.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/scsdpram.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/shiftreg.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/systolicarraykernel.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/systolicarray.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/teras_bridge_mpw5.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_teras/teras/src/teras.v
//  7 ALU74181                       : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_alu74181
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_alu74181/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_alu74181/alu74181/src/alu74181.v
//  5 vga demo                       : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped-vgademo-on-fpga
-v $(USER_PROJECT_VERILOG)/rtl/wrapped-vgademo-on-fpga/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped-vgademo-on-fpga/vgademo-on-fpga/src/sphere.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped-vgademo-on-fpga/vgademo-on-fpga/src/top.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped-vgademo-on-fpga/vgademo-on-fpga/src/vga_core.v
//  4 SiLife                         : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_silife
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/buf_reg.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/cell.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/grid_32x32.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/grid_loader.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/grid_sync.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/grid_sync_edge.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/grid_trng_loader.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/grid_wishbone.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/spi_master.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/max7219.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/trng.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_silife/silife/src/silife.v
//  9 wrapped_acorn_prng             : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_acorn_prng
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_acorn_prng/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_acorn_prng/acorn_prng/src/acorn_prng.v
// 10 HSV Mixer                      : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_hsv_mixer
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hsv_mixer/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hsv_mixer/hsv_mixer/src/debounce.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hsv_mixer/hsv_mixer/src/encoder.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hsv_mixer/hsv_mixer/src/pwm.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hsv_mixer/hsv_mixer/src/hsv_mixer.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_hsv_mixer/hsv_mixer/src/hsv2rgb.v
//  6 SkullFET                       : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wrapped_skullfet
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_skullfet/wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/wrapped_skullfet/src/skullfet-functional.v
// shared Bridge                     : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wb_bridge
// shared Wrapper                    : /home/matt/work/asic-workshop/shuttle5/openlane/designs/wb_openram_wrapper
// shared OpenRAM 1kybte             : /home/matt/work/asic-workshop/shuttle5/openlane/designs/openram_z2a
-v $(USER_PROJECT_VERILOG)/rtl/wb_bridge/src/wb_bridge_2way.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_openram_wrapper/src/register_rw.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_openram_wrapper/src/wb_port_control.v
-v $(USER_PROJECT_VERILOG)/rtl/wb_openram_wrapper/src/wb_openram_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/openram_z2a/src/sky130_sram_1kbyte_1rw1r_32x256_8.v