sdc/wrapped_hack_soc_dffram.sdc

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# Created by write_sdc
# Fri Mar 18 00:59:48 2022
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current_design wrapped_hack_soc_dffram
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# Timing Constraints
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create_clock -name wb_clk_i -period 20.0000 [get_ports {wb_clk_i}]
set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
set_clock_uncertainty 0.2500 wb_clk_i
set_propagated_clock [get_clocks {wb_clk_i}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {active}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[32]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[33]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[34]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[35]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[36]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[37]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_in[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_in[9]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[0]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[10]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[11]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[12]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[13]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[14]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[15]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[16]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[17]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[18]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[19]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[1]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[20]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[21]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[22]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[23]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[24]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[25]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[26]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[27]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[28]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[29]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[2]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[30]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[31]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[3]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[4]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[5]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[6]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[7]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[8]}]
set_input_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_oenb[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[32]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[33]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[34]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[35]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[36]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[37]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_oeb[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[32]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[33]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[34]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[35]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[36]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[37]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {io_out[9]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[0]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[10]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[11]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[12]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[13]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[14]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[15]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[16]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[17]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[18]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[19]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[1]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[20]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[21]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[22]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[23]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[24]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[25]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[26]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[27]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[28]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[29]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[2]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[30]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[31]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[3]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[4]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[5]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[6]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[7]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[8]}]
set_output_delay 4.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {la1_data_out[9]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[0]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[10]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[11]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[12]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[13]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[14]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[15]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[16]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[17]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[18]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[19]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[1]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[20]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[21]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[22]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[23]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[24]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[25]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[26]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[27]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[28]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[29]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[2]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[30]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[31]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[3]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[4]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[5]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[6]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[7]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[8]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/DW[9]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RA[0]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RA[1]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RA[2]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RA[3]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RA[4]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RB[0]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RB[1]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RB[2]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RB[3]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RB[4]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RW[0]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RW[1]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RW[2]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RW[3]}]
set_output_delay -1.0000 -add_delay -reference_pin [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/CLK}] [get_pins {soc.spi_video_ram_1.write_fifo.dffrf/RW[4]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
set_load -pin_load 0.0334 [get_ports {io_out[37]}]
set_load -pin_load 0.0334 [get_ports {io_out[36]}]
set_load -pin_load 0.0334 [get_ports {io_out[35]}]
set_load -pin_load 0.0334 [get_ports {io_out[34]}]
set_load -pin_load 0.0334 [get_ports {io_out[33]}]
set_load -pin_load 0.0334 [get_ports {io_out[32]}]
set_load -pin_load 0.0334 [get_ports {io_out[31]}]
set_load -pin_load 0.0334 [get_ports {io_out[30]}]
set_load -pin_load 0.0334 [get_ports {io_out[29]}]
set_load -pin_load 0.0334 [get_ports {io_out[28]}]
set_load -pin_load 0.0334 [get_ports {io_out[27]}]
set_load -pin_load 0.0334 [get_ports {io_out[26]}]
set_load -pin_load 0.0334 [get_ports {io_out[25]}]
set_load -pin_load 0.0334 [get_ports {io_out[24]}]
set_load -pin_load 0.0334 [get_ports {io_out[23]}]
set_load -pin_load 0.0334 [get_ports {io_out[22]}]
set_load -pin_load 0.0334 [get_ports {io_out[21]}]
set_load -pin_load 0.0334 [get_ports {io_out[20]}]
set_load -pin_load 0.0334 [get_ports {io_out[19]}]
set_load -pin_load 0.0334 [get_ports {io_out[18]}]
set_load -pin_load 0.0334 [get_ports {io_out[17]}]
set_load -pin_load 0.0334 [get_ports {io_out[16]}]
set_load -pin_load 0.0334 [get_ports {io_out[15]}]
set_load -pin_load 0.0334 [get_ports {io_out[14]}]
set_load -pin_load 0.0334 [get_ports {io_out[13]}]
set_load -pin_load 0.0334 [get_ports {io_out[12]}]
set_load -pin_load 0.0334 [get_ports {io_out[11]}]
set_load -pin_load 0.0334 [get_ports {io_out[10]}]
set_load -pin_load 0.0334 [get_ports {io_out[9]}]
set_load -pin_load 0.0334 [get_ports {io_out[8]}]
set_load -pin_load 0.0334 [get_ports {io_out[7]}]
set_load -pin_load 0.0334 [get_ports {io_out[6]}]
set_load -pin_load 0.0334 [get_ports {io_out[5]}]
set_load -pin_load 0.0334 [get_ports {io_out[4]}]
set_load -pin_load 0.0334 [get_ports {io_out[3]}]
set_load -pin_load 0.0334 [get_ports {io_out[2]}]
set_load -pin_load 0.0334 [get_ports {io_out[1]}]
set_load -pin_load 0.0334 [get_ports {io_out[0]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[31]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[30]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[29]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[28]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[27]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[26]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[25]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[24]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[23]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[22]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[21]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[20]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[19]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[18]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[17]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[16]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[15]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[14]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[13]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[12]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[11]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[10]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[9]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[8]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[7]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[6]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[5]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[4]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[3]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[2]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[1]}]
set_load -pin_load 0.0334 [get_ports {la1_data_out[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {active}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_data_in[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la1_oenb[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]