commit 62c3a3cd48171fc392d4feb7d6dff9d3df89c4db
author shivani269 <shivani.shah269@gmail.com> Thu Dec 30 11:15:35 2021 +0530
committer shivani269 <shivani.shah269@gmail.com> Thu Dec 30 11:15:35 2021 +0530
tree be6d038f1e6b94d5db97338c914cab2a0cca1e7f
parent 85ed3406f9a950586c77f0008002dd8b21217b74

Updating test file

verilog/dv/la_test/la_test.c

diff --git a/verilog/dv/la_test/la_test.c b/verilog/dv/la_test/la_test.c
index a1adf44..44f2047 100644
--- a/verilog/dv/la_test/la_test.c
+++ b/verilog/dv/la_test/la_test.c
@@ -3206,7 +3206,7 @@
       }
 
         // Wait for the expected result
-        while (((reg_la1_data & 0x00FFC000) != 0x) && ((reg_la1_data & 0xFF000000) != 0x) && ((reg_la2_data & 0x000000FF) != 0x) && ((reg_la2_data & 0x0000FF00) != 0x) && ((reg_la2_data & 0x00FF0000) != 0x) && ((reg_la2_data & 0xFF000000) != 0x) && ((reg_la3_data & 0x000000FF) != 0x) && ((reg_la3_data & 0x0000FF00) != 0x) && ((reg_la3_data & 0x00FF0000) != 0x) && ((reg_la2_data & 0x7F000000) != 0x)); // L1 hit count, L2 hit count4, L2 hit count8, L2 hit count16, L2 ss1 count4, L2 ss1 count 8, L2 hit count16, L2 ss2 hit count4, L2 ss2 count8, L2 ss2 count16.
+        while (((reg_la1_data & 0x00FFC000) != 0x3d6) && ((reg_la1_data & 0xFF000000) != 0x0) && ((reg_la2_data & 0x000000FF) != 0x0) && ((reg_la2_data & 0x0000FF00) != 0x0) && ((reg_la2_data & 0x00FF0000) != 0x0) && ((reg_la2_data & 0xFF000000) != 0x0) && ((reg_la3_data & 0x000000FF) != 0x0) && ((reg_la3_data & 0x0000FF00) != 0x0) && ((reg_la3_data & 0x00FF0000) != 0x0) && ((reg_la2_data & 0x7F000000) != 0x0)); // L1 hit count, L2 hit count4, L2 hit count8, L2 hit count16, L2 ss1 count4, L2 ss1 count 8, L2 hit count16, L2 ss2 hit count4, L2 ss2 count8, L2 ss2 count16.
         
         // Test has been done successfully
 	reg_mprj_datal = 0xAB610000;