commit	85ed3406f9a950586c77f0008002dd8b21217b74	[log] [tgz]
author	shivani269 <shivani.shah269@gmail.com>	Thu Dec 30 10:46:41 2021 +0530
committer	shivani269 <shivani.shah269@gmail.com>	Thu Dec 30 10:46:41 2021 +0530
tree	37af316c51787b10703526e0f19d8d09699a6e21
parent	010c61aa2a7501e51305d4b9d79fda671d41ab40 [diff]

Adding verilog and gds of 32x1024 SRAM

gds/sram_32_1024_sky130A.gds[Added - diff]
verilog/rtl/sram_32_1024_sky130A.v[Added - diff]
verilog/rtl/user_project_wrapper.v[diff]

3 files changed

tree: 37af316c51787b10703526e0f19d8d09699a6e21

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md

README.md

Test Project

RISC-V based Microprocessor

This repository contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

Demo test by Shivani Shah Test counter Example.