Adding verilog and gds of 32x1024 SRAM
diff --git a/gds/sram_32_1024_sky130A.gds b/gds/sram_32_1024_sky130A.gds
new file mode 100644
index 0000000..e234253
--- /dev/null
+++ b/gds/sram_32_1024_sky130A.gds
Binary files differ
diff --git a/verilog/rtl/sram_32_1024_sky130A.v b/verilog/rtl/sram_32_1024_sky130A.v
new file mode 100644
index 0000000..f19fa4f
--- /dev/null
+++ b/verilog/rtl/sram_32_1024_sky130A.v
@@ -0,0 +1,72 @@
+// OpenRAM SRAM model
+// Words: 1024
+// Word size: 32
+
+module sram_32_1024_sky130A(
+`ifdef USE_POWER_PINS
+ vccd1,
+ vssd1,
+`endif
+// Port 0: RW
+ clk0,csb0,web0,addr0,din0,dout0
+ );
+
+ parameter DATA_WIDTH = 32 ;
+ parameter ADDR_WIDTH = 10 ;
+ parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+ // FIXME: This delay is arbitrary.
+ parameter DELAY = 3 ;
+ parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+ parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+ inout vccd1;
+ inout vssd1;
+`endif
+ input clk0; // clock
+ input csb0; // active low chip select
+ input web0; // active low write control
+ input [ADDR_WIDTH-1:0] addr0;
+ input [DATA_WIDTH-1:0] din0;
+ output [DATA_WIDTH-1:0] dout0;
+
+ reg csb0_reg;
+ reg web0_reg;
+ reg [ADDR_WIDTH-1:0] addr0_reg;
+ reg [DATA_WIDTH-1:0] din0_reg;
+ reg [DATA_WIDTH-1:0] dout0;
+
+ // All inputs are registers
+ always @(posedge clk0)
+ begin
+ csb0_reg = csb0;
+ web0_reg = web0;
+ addr0_reg = addr0;
+ din0_reg = din0;
+ #(T_HOLD) dout0 = 32'bx;
+ if ( !csb0_reg && web0_reg && VERBOSE )
+ $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+ if ( !csb0_reg && !web0_reg && VERBOSE )
+ $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+ end
+
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+ // Memory Write Block Port 0
+ // Write Operation : When web0 = 0, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_WRITE0
+ if ( !csb0_reg && !web0_reg ) begin
+ mem[addr0_reg][31:0] = din0_reg[31:0];
+ end
+ end
+
+ // Memory Read Block Port 0
+ // Read Operation : When web0 = 1, csb0 = 0
+ always @ (negedge clk0)
+ begin : MEM_READ0
+ if (!csb0_reg && web0_reg)
+ dout0 <= #(DELAY) mem[addr0_reg];
+ end
+
+endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5f0bc92..4b36f35 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -106,7 +106,7 @@
);
-sram_32_256_sky130A mem (
+sram_32_1024_sky130A mem (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V supply
.vssd1(vssd1), // User area 1 digital ground
