commit	62c3a3cd48171fc392d4feb7d6dff9d3df89c4db	[log] [tgz]
author	shivani269 <shivani.shah269@gmail.com>	Thu Dec 30 11:15:35 2021 +0530
committer	shivani269 <shivani.shah269@gmail.com>	Thu Dec 30 11:15:35 2021 +0530
tree	be6d038f1e6b94d5db97338c914cab2a0cca1e7f
parent	85ed3406f9a950586c77f0008002dd8b21217b74 [diff]

Updating test file

verilog/dv/la_test/la_test.c[diff]

1 file changed

tree: be6d038f1e6b94d5db97338c914cab2a0cca1e7f

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md

README.md

Test Project

RISC-V based Microprocessor

This repository contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

Demo test by Shivani Shah Test counter Example.